This commit was manufactured by cvs2svn to create tag 'EMAC_R1'.

git-svn-id: http://moon:8086/svn/vhdl/tags/EMAC_R1@856 cc03376c-175c-47c8-b038-4cd826a8556b

lib/emac/emac_jb.vhd

@@ -0,0 +1,657 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+use std.textio.all; --  Imports the standard textio package.
+
+use work.utils_pkg.all;
+
+ENTITY emac_jb IS
+	Generic
+	(
+		f_sysclk	: real		:= 100.0;
+		TX_RAM_SIZE	: natural	:= 2048
+	);
+	Port
+	(
+		CLK_I		: in  STD_LOGIC;
+		RST_I		: in  STD_LOGIC;
+		INT_O		: out STD_LOGIC;
+		CYC_I		: in  STD_LOGIC;
+		STB_I		: in  STD_LOGIC;
+		SEL_I		: in  unsigned(3 downto 0);
+		WE_I		: in  STD_LOGIC;
+		ACK_O		: out STD_LOGIC;
+		SRDY_O		: out STD_LOGIC;
+		MRDY_I		: in  STD_LOGIC;
+		ADDR_I		: in  unsigned(31 downto 0);
+		DAT_I		: in  unsigned(31 downto 0);
+		DAT_O		: out unsigned(31 downto 0);
+		mii_rx_clk	: in  STD_LOGIC;
+		mii_rx_dv	: in  STD_LOGIC;
+		mii_rx_er	: in  STD_LOGIC;
+		mii_rx		: in unsigned(7 downto 0);
+		mii_tx_clk	: in  STD_LOGIC;
+		mii_tx_en	: out STD_LOGIC;
+		mii_tx_er	: out STD_LOGIC;
+		mii_tx		: out unsigned(7 downto 0);
+		mii_gtx_clk	: out STD_LOGIC;
+		mii_crs		: in  STD_LOGIC;
+		mii_col		: in  STD_LOGIC
+		
+	);
+END emac_jb;
+
+ARCHITECTURE behavior OF emac_jb IS
+
+	constant TX_RAM_ADDR_WIDTH	: natural := NextExpBaseTwo(TX_RAM_SIZE);
+	
+	subtype word_ptr_t is unsigned(TX_RAM_ADDR_WIDTH-1 downto 0);
+	
+	-- Signals for EMAC connections
+	signal tx_fifo_din		: unsigned(35 downto 0);
+	signal tx_fifo_dout		: unsigned(35 downto 0);
+	signal tx_fifo_we		: std_logic;
+	signal tx_fifo_re		: std_logic;
+	signal tx_fifo_empty	: std_logic;
+	signal tx_fifo_full		: std_logic;
+	signal rx_int_en		: std_logic;
+	signal tx_int_en		: std_logic;
+	signal irq_rx			: std_logic;
+	signal irq_tx			: std_logic;
+	signal tx_err			: std_logic;
+
+	signal tx_flush_en		: std_logic;
+	signal tx_flush_rdy		: std_logic;
+	signal tx_flush_ptr_set	: std_logic;
+
+	signal tx_commit_en		: std_logic;
+	signal tx_flush_ptr		: word_ptr_t;
+	
+	signal host_data_we		: std_logic;
+	signal host_data_reg	: unsigned(31 downto 0);
+	signal host_tx_size		: unsigned(15 downto 0);
+
+	signal tx_fill_size		: word_ptr_t;
+	signal tx_fill_cnt		: word_ptr_t;
+	signal tx_fill_ptr		: word_ptr_t;
+	signal tx_fill_rdy		: std_logic;
+	signal tx_fill_cnt_set	: std_logic;
+	signal tx_fill_cnt_adv	: std_logic;
+	signal tx_fill_ptr_set	: std_logic;
+	signal tx_fill_ptr_adv	: std_logic;
+
+	signal tx_alloc_OK		: std_logic;
+	signal tx_alloc_req_en	: std_logic;
+	signal tx_alloc_req		: std_logic;
+	signal tx_alloc_ack		: std_logic;
+	
+	signal tx_nwords_free	: word_ptr_t;
+	signal tx_alloc_base	: word_ptr_t;
+	signal tx_alloc_size	: word_ptr_t;
+	signal tx_alloc_en		: std_logic;
+
+	signal tx_free_en		: std_logic;
+	signal tx_uncommit_en	: std_logic;
+	signal tx_fill_remain	: unsigned(1 downto 0);
+
+	signal tx_xfer_size		: word_ptr_t;
+	signal tx_xfer_ptr		: word_ptr_t;
+	signal tx_xfer_cnt		: word_ptr_t;
+	signal tx_xfer_en		: std_logic;
+	signal tx_xfer_ptr_set	: std_logic;
+	signal tx_xfer_ptr_adv	: std_logic;
+	signal tx_xfer_cnt_set	: std_logic;
+	signal tx_xfer_cnt_adv	: std_logic;
+	signal tx_xfer_rdy		: std_logic;
+	signal xfer_tag			: unsigned(3 downto 0);
+	signal xfer_remain		: unsigned(1 downto 0);
+	signal xfer_odd			: std_logic;
+	signal xfer_remain_en	: std_logic;
+
+	signal tx_ram_en_a		: std_logic;
+	signal tx_ram_we_a		: std_logic;
+	signal tx_ram_addr_a	: unsigned(TX_RAM_ADDR_WIDTH-1 downto 0);
+	signal tx_ram_din_a		: unsigned(35 downto 0);
+	signal tx_ram_dout_a	: unsigned(35 downto 0);
+	signal tx_ram_en_b		: std_logic;
+	signal tx_ram_we_b		: std_logic;
+	signal tx_ram_addr_b	: unsigned(TX_RAM_ADDR_WIDTH-1 downto 0);
+	signal tx_ram_din_b		: unsigned(35 downto 0);
+	signal tx_ram_dout_b	: unsigned(35 downto 0);
+
+	signal piso_din_be		: unsigned(3 downto 0);
+	signal piso_din_rdy		: std_logic;
+	signal tx_data_vld		: std_logic;
+	
+	subtype inter_frame_gap_cnt_t is natural range 0 to natural(1.0*f_sysclk)-1;
+	signal inter_frame_gap_cnt	: inter_frame_gap_cnt_t;
+	signal inter_frame_gap_rdy	: std_logic;
+	
+	alias tx_ram_data_in_a is tx_ram_din_a(31 downto 0);
+	alias tx_ram_tag_in_a is tx_ram_din_a(35 downto 32);
+	alias tx_ram_data_out_a is tx_ram_dout_a(31 downto 0);
+	alias tx_ram_tag_out_a is tx_ram_dout_a(35 downto 32);
+	
+	alias tx_ram_data_in_b is tx_ram_din_b(31 downto 0);
+	alias tx_ram_tag_in_b is tx_ram_din_b(35 downto 32);
+	alias tx_ram_data_out_b is tx_ram_dout_b(31 downto 0);
+	alias tx_ram_tag_out_b is tx_ram_dout_b(35 downto 32);
+
+	type host_tx_state_t is (host_tx_init, host_tx_flush, host_tx_idle, host_tx_alloc, host_tx_setup, host_tx_arm, host_tx_fill, host_tx_commit);
+	signal host_tx_s, host_tx_sn : host_tx_state_t;
+	
+	type xfer_tx_state_t is (xfer_tx_init, xfer_tx_idle, xfer_tx_setup, xfer_wait, xfer_tx_active, xfer_tx_free);
+	signal xfer_tx_s, xfer_tx_sn : xfer_tx_state_t;
+
+
+	type piso_byte_mask_array_t is array (0 to 3) of unsigned (3 downto 0);
+	constant piso_byte_mask_rom : piso_byte_mask_array_t :=
+	(
+		"1111",
+		"0001",
+		"0011",
+		"0111"
+	);
+	
+	
+begin
+
+	SRDY_O				<= CYC_I;
+	INT_O				<= irq_rx or irq_tx;
+	mii_gtx_clk			<= '0';
+	mii_tx_er			<= tx_err;
+
+	tx_ram_tag_in_b		<= "0000";
+	tx_ram_en_b			<= '1';
+	tx_ram_we_b			<= tx_uncommit_en or tx_flush_en;
+	tx_ram_addr_b		<= tx_flush_ptr when (tx_flush_en = '1' or tx_uncommit_en = '1') else tx_xfer_ptr;
+	xfer_tag			<= tx_ram_tag_out_b;
+	
+	tx_ram_en_a			<= '1';
+	tx_ram_we_a			<= tx_commit_en or tx_fill_cnt_adv;
+	tx_ram_tag_in_a		<= tx_fill_remain & "01" when tx_commit_en = '1' else "0000";
+	tx_ram_data_in_a	<= resize(tx_fill_size, 16) & resize(tx_alloc_base, 16) when tx_commit_en = '1' else host_data_reg;
+	tx_ram_addr_a		<= tx_alloc_base when tx_commit_en = '1' else tx_fill_ptr;
+
+	piso_din_be			<= (others => '1');
+	tx_fifo_re			<= piso_din_rdy;
+	tx_data_vld			<= not tx_fifo_empty;
+	
+	tx_fifo_din(35 downto 32)	<= piso_byte_mask_rom(to_integer(xfer_remain)) when xfer_remain_en = '1' else "1111";
+	tx_fifo_din(31 downto 0)	<= tx_ram_data_out_b;
+	
+------------------------------------------------------------------
+host_tx_state_next:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				host_tx_s	<= host_tx_init;
+			else
+				host_tx_s	<= host_tx_sn;
+			end if;
+		end if;
+	end process;	
+
+host_tx_state:
+	process(host_tx_s, tx_flush_rdy, tx_alloc_req, tx_alloc_OK, tx_fill_rdy, host_data_we)
+	begin
+	
+		tx_flush_en			<= '0';
+		tx_flush_ptr_set	<= '0';
+		tx_alloc_ack		<= '0';
+		tx_fill_cnt_set		<= '0';
+		tx_fill_cnt_adv		<= '0';
+		tx_fill_ptr_set		<= '0';
+		tx_fill_ptr_adv		<= '0';
+		tx_commit_en		<= '0';
+		tx_alloc_en			<= '0';
+		
+		host_tx_sn			<= host_tx_s;
+		
+		case host_tx_s is
+		
+		when host_tx_init =>
+			tx_flush_ptr_set	<= '1';
+			host_tx_sn <= host_tx_flush;
+		
+		when host_tx_flush =>
+			tx_flush_en	<= '1';
+			if tx_flush_rdy = '1' then
+				tx_flush_en	<= '0';
+				host_tx_sn <= host_tx_idle;
+			end if;
+			
+		when host_tx_idle =>
+			if tx_alloc_req = '1' then
+				host_tx_sn	<= host_tx_alloc;
+			end if;
+
+		when host_tx_alloc =>
+			if tx_alloc_OK = '1' then
+				host_tx_sn			<= host_tx_setup;
+				tx_alloc_ack		<= '1';
+			end if;
+
+		when host_tx_setup =>
+			tx_fill_cnt_set	<= '1';
+			tx_fill_ptr_set	<= '1';
+			host_tx_sn		<= host_tx_arm;
+
+		when host_tx_arm =>
+			tx_fill_ptr_adv	<= '1';
+			tx_fill_cnt_adv	<= '1';
+			host_tx_sn		<= host_tx_fill;
+
+		when host_tx_fill =>
+			tx_fill_cnt_adv	<= host_data_we;
+			tx_fill_ptr_adv	<= not tx_fill_rdy and host_data_we;
+			if tx_alloc_req = '1' then
+				host_tx_sn	<= host_tx_alloc;
+			elsif tx_fill_rdy = '1' then
+				host_tx_sn		<= host_tx_commit;
+			end if;
+		
+		when host_tx_commit =>
+			tx_commit_en	<= '1';
+			tx_alloc_en		<= '1';
+			host_tx_sn		<= host_tx_idle;
+
+		when others => 
+			host_tx_sn	<= host_tx_idle;
+		end case;
+
+	end process;
+
+------------------------------------------------------------------
+-- Allocation stuff
+------------------------------------------------------------------
+alloc_request_logic:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				tx_alloc_req		<= '0';
+			elsif tx_alloc_req_en = '1' and tx_alloc_req = '0' then
+				tx_alloc_req		<= '1';
+				tx_fill_remain		<= host_tx_size(1 downto 0);
+				tx_fill_size		<= host_tx_size(word_ptr_t'left+2 downto 2);
+				if host_tx_size(1 downto 0) /= "00" then
+					tx_fill_size	<= host_tx_size(word_ptr_t'left+2 downto 2) + 1;
+				end if;
+			elsif tx_alloc_ack = '1' then
+				tx_alloc_req		<= '0';
+				tx_alloc_size		<= tx_fill_size;
+			end if;
+		end if;
+	end process;	
+
+------------------------------------------------------------------
+alloc_base_logic:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if tx_flush_en = '1' then
+				tx_alloc_base		<= (others => '0');
+			elsif tx_commit_en = '1' then
+				tx_alloc_base		<= tx_fill_ptr;
+			end if;
+		end if;
+	end process;	
+
+------------------------------------------------------------------
+alloc_eval_logic:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			tx_alloc_OK		<= '0';
+			if tx_alloc_req = '1' then
+				if tx_fill_size < tx_nwords_free then
+					tx_alloc_OK		<= '1';
+				end if;
+			end if;
+		end if;
+	end process;	
+
+------------------------------------------------------------------
+tx_nwords_free_counter:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if tx_flush_en = '1' then
+				tx_nwords_free		<= (others => '1');
+			elsif tx_alloc_en = '1' then
+				tx_nwords_free		<= tx_nwords_free - tx_fill_size;
+			elsif tx_free_en = '1' then
+				tx_nwords_free		<= tx_nwords_free + tx_xfer_size;
+			end if;
+		end if;
+	end process;	
+
+------------------------------------------------------------------
+tx_flush_counter:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if tx_flush_en = '0' then
+				tx_flush_rdy	<= '0';
+				if tx_flush_ptr_set = '1' then
+					tx_flush_ptr	<= (others => '1');
+				elsif tx_xfer_ptr_set = '1' then
+					tx_flush_ptr	<= tx_ram_data_out_b(tx_flush_ptr'left downto 0);
+				end if;	
+			elsif tx_flush_ptr /= 0 then
+				tx_flush_ptr	<= tx_flush_ptr - 1;
+			else
+				tx_flush_rdy	<= '1';
+			end if;
+		end if;
+	end process;	
+
+------------------------------------------------------------------
+-- Fill stuff
+------------------------------------------------------------------
+tx_fill_counter:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if tx_fill_cnt_set = '1' then	
+				tx_fill_rdy			<= '0';
+				tx_fill_cnt			<= tx_alloc_size;
+			elsif tx_fill_cnt_adv = '1' then
+				if tx_fill_cnt /= 0 then
+					tx_fill_cnt		<= tx_fill_cnt - 1;
+				else
+					tx_fill_rdy		<= '1';
+				end if;
+			end if;
+		end if;
+	end process;	
+
+tx_fill_pointer:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if tx_fill_ptr_set = '1' then
+				tx_fill_ptr		<= tx_alloc_base;
+			elsif tx_fill_ptr_adv = '1' then
+				tx_fill_ptr		<= tx_fill_ptr + 1;
+			end if;
+		end if;
+	end process;	
+
+------------------------------------------------------------------
+-- Transfer stuff
+------------------------------------------------------------------
+xfer_tx_state_next:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				xfer_tx_s	<= xfer_tx_init;
+			else
+				xfer_tx_s	<= xfer_tx_sn;
+			end if;
+		end if;
+	end process;	
+
+xfer_tx_state:
+	process(xfer_tx_s, xfer_tag, xfer_odd, tx_xfer_rdy, inter_frame_gap_rdy, tx_alloc_en, tx_fifo_full)
+	begin
+	
+		tx_xfer_cnt_set		<= '0';
+		tx_xfer_cnt_adv		<= '0';
+		tx_xfer_ptr_set		<= '0';
+		tx_xfer_ptr_adv		<= '0';
+		tx_xfer_en			<= '0';
+		xfer_remain_en		<= '0';
+		tx_free_en			<= '0';
+		tx_uncommit_en		<= '0';
+		
+		xfer_tx_sn			<= xfer_tx_s;
+		
+		case xfer_tx_s is
+		
+		when xfer_tx_init =>
+			xfer_tx_sn <= xfer_tx_idle;
+		
+		when xfer_tx_idle =>
+			if xfer_tag(0) = '1' then
+				tx_xfer_ptr_set	<= '1';
+				tx_xfer_cnt_set	<= '1';
+				xfer_tx_sn		<= xfer_wait;
+			end if;
+			
+		when xfer_wait =>
+			if inter_frame_gap_rdy = '1' then
+				xfer_tx_sn			<= xfer_tx_setup;
+			end if;			
+		
+		when xfer_tx_setup =>
+			tx_uncommit_en		<= '1';
+			tx_xfer_ptr_adv		<= '1';
+			tx_xfer_cnt_adv		<= '1';
+			xfer_tx_sn			<= xfer_tx_active;
+
+		when xfer_tx_active =>
+			tx_xfer_en			<= '1';
+			tx_xfer_cnt_adv		<= not tx_fifo_full;
+			tx_xfer_ptr_adv		<= not tx_fifo_full;
+			if tx_xfer_rdy = '1' then
+				xfer_remain_en	<= xfer_odd;
+				tx_xfer_en		<= '0';
+				tx_xfer_cnt_adv	<= '0';
+				tx_xfer_ptr_adv	<= '0';
+				xfer_tx_sn		<= xfer_tx_free;
+			end if;	
+
+		when xfer_tx_free =>
+			tx_free_en			<= not tx_alloc_en;
+			if tx_alloc_en = '0' then
+				xfer_tx_sn			<= xfer_tx_idle;
+			end if;
+
+		when others => 
+			xfer_tx_sn	<= xfer_tx_idle;
+		end case;
+
+	end process;
+
+------------------------------------------------------------------
+interframe_gap_counter:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if tx_flush_en = '1' then
+				inter_frame_gap_rdy	<= '1';
+			elsif tx_fifo_empty = '0' then
+				inter_frame_gap_rdy	<= '0';
+				inter_frame_gap_cnt <= inter_frame_gap_cnt_t'high;
+			elsif inter_frame_gap_cnt /= 0 then
+				inter_frame_gap_cnt <= inter_frame_gap_cnt - 1;
+			else
+				inter_frame_gap_rdy	<= '1';
+			end if;
+		end if;
+	end process;
+
+------------------------------------------------------------------
+tx_xfer_counter:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if tx_xfer_cnt_set = '1' then
+				tx_xfer_size	<= (others => '0');
+				tx_xfer_rdy		<= '0';
+				tx_xfer_cnt 	<= tx_ram_data_out_b(tx_xfer_ptr'left+16 downto 16);
+			elsif tx_xfer_cnt_adv = '1' then
+				if tx_xfer_cnt /= 0 then
+					tx_xfer_cnt		<= tx_xfer_cnt - 1;
+					tx_xfer_size	<= tx_xfer_size + 1;
+				else
+					tx_xfer_rdy		<= '1';
+				end if;
+			end if;
+		end if;	
+			
+	end process;	
+	
+tx_xfer_pointer:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			tx_fifo_we			<= tx_xfer_en;
+			if tx_xfer_ptr_set = '1' then
+				tx_xfer_ptr		<= tx_ram_data_out_b(tx_xfer_ptr'left downto 0);
+				xfer_remain		<= xfer_tag(3 downto 2);
+				xfer_odd 		<= '0';
+				if xfer_tag(3 downto 2) /= "00" then
+					xfer_odd <= '1';
+				end if;
+			elsif tx_xfer_ptr_adv = '1' then
+				tx_xfer_ptr		<= tx_xfer_ptr + 1;
+			end if;
+		end if;	
+			
+	end process;	
+	
+------------------------------------------------------------------
+registers_write: 
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			host_data_we	<= '0';
+			tx_alloc_req_en	<= '0';
+			if RST_I = '1' then
+				rx_int_en		<= '0';
+				tx_int_en		<= '0';
+				tx_err			<= '0';
+		elsif (STB_I and CYC_I and WE_I) = '1' then
+				case ADDR_I(5 downto 2) is
+				
+				when "0000" =>
+					tx_err				<= DAT_I(31);
+					tx_alloc_req_en		<= DAT_I(16);
+					tx_int_en			<= DAT_I(5);
+					rx_int_en			<= DAT_I(4);
+					
+				when "0001" => 
+					if tx_alloc_req = '0' then
+						host_tx_size		<= DAT_I(31 downto 16);
+					end if;	
+					
+				when "0010" =>
+					host_data_we		<= '1';
+					host_data_reg		<= DAT_I;
+					
+				when others => null;
+				end case;
+			end if;	
+		end if;	
+	end process;
+
+registers_read: 
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			ACK_O			<= '0';
+			if (STB_I and CYC_I) = '1' then
+				ACK_O		<= not WE_I;
+				DAT_O		<= (others => '0');
+				case ADDR_I(5 downto 2) is
+
+				when "0000" =>
+					DAT_O(31)	<= tx_err;
+					DAT_O(30)	<= mii_rx_er;
+					DAT_O(29)	<= mii_col;
+					DAT_O(28)	<= mii_crs;
+					DAT_O(16)	<= tx_alloc_req;
+					DAT_O(5)	<= tx_int_en;
+					DAT_O(4)	<= rx_int_en;
+
+				when "0001" => 
+					DAT_O(31 downto 16)	<= host_tx_size;
+
+				when "0010" =>
+
+				when others => null;
+				end case;
+			end if;
+		end if;	
+	end process;
+
+inst_tx_ram : entity work.dpram_2w2r
+	GENERIC MAP 
+	(
+		addr_width	=> TX_RAM_ADDR_WIDTH,
+		data_width	=> 36
+	)
+	PORT MAP 
+	(
+		clk_a	=> CLK_I,
+		clk_b	=> CLK_I,
+		en_a	=> tx_ram_en_a,
+		en_b	=> tx_ram_en_b,
+		we_a	=> tx_ram_we_a,
+		we_b	=> tx_ram_we_b,
+		addr_a	=> tx_ram_addr_a,
+		addr_b	=> tx_ram_addr_b,
+		din_a	=> tx_ram_din_a,
+		din_b	=> tx_ram_din_b,
+		dout_a	=> tx_ram_dout_a,
+		dout_b	=> tx_ram_dout_b
+	);
+
+-- Instantiate synchronous FIFO
+inst_tx_fifo: entity work.fifo_async
+	GENERIC MAP
+	(
+		addr_width			=> 5,
+		data_width			=> 36,
+		do_last_read_update	=> true
+	)
+	PORT MAP
+	(
+		rst			=>	RST_I,
+		clk_w		=>	CLK_I,
+		clk_r		=>	mii_tx_clk,
+		we			=>	tx_fifo_we,
+		re			=>	tx_fifo_re,
+		fifo_full	=>	tx_fifo_full,
+		fifo_empty	=>	tx_fifo_empty,
+		fifo_afull	=>	open,
+		fifo_aempty	=>	open,
+		data_w		=>  tx_fifo_din,
+		data_r		=>  tx_fifo_dout
+	);
+
+inst_piso : entity work.piso
+	GENERIC MAP
+	(
+		data_width_in	=> 32,
+		data_width_out	=> 8,
+		msb_first		=> false
+	)
+	PORT MAP
+	(
+		rst			=> RST_I,
+		clk			=> mii_tx_clk,
+		din_vld		=> tx_data_vld,
+		din_rdy		=> piso_din_rdy,
+		din_be		=> tx_fifo_dout(35 downto 32),
+		din			=> tx_fifo_dout(31 downto 0),
+		dout_en		=> mii_tx_en,
+		dout		=> mii_tx
+		
+	);
+
+irq_register:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			irq_tx		<= tx_int_en;
+			irq_rx		<= rx_int_en;
+		end if;
+	end process;
+
+end behavior;

lib/emac/sim/tb_emac_jb.fdo

@@ -0,0 +1,19 @@
+## NOTE:  Do not edit this file.
+## Autogenerated by ProjNav (creatfdo.tcl) on Thu Jul 06 20:49:07 Westeuropäische Sommerzeit 2006
+##
+vlib work
+vcom -explicit  -93 "../../misc/utils_pkg.vhd"
+vcom -explicit  -93 "../../misc/dpram_1w1r.vhd"
+vcom -explicit  -93 "../../FIFO/src/fifo_ctrl_pkg.vhd"
+vcom -explicit  -93 "../../FIFO/src/gray_counter.vhd"
+vcom -explicit  -93 "../../FIFO/src/fifo_async_ctrl.vhd"
+vcom -explicit  -93 "../../FIFO/src/fifo_async.vhd"
+vcom -explicit  -93 "../src/emac_jb.vhd"
+vcom -explicit  -93 "../src/tb_emac_jb.vhd"
+vsim -t 1ps   -lib work tb_emac_jb
+view wave
+do {tb_emac_jb.wdo}
+view structure
+view signals
+
+run 20 us

lib/emac/sim/tb_emac_jb.wdo

@@ -0,0 +1,169 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_emac_jb/clk
+add wave -noupdate -format Logic /tb_emac_jb/rst
+add wave -noupdate -format Logic /tb_emac_jb/cyc_i
+add wave -noupdate -format Logic /tb_emac_jb/stb_i
+add wave -noupdate -format Logic /tb_emac_jb/we_i
+add wave -noupdate -format Literal /tb_emac_jb/sel_i
+add wave -noupdate -format Logic /tb_emac_jb/ack_o
+add wave -noupdate -format Logic /tb_emac_jb/int_o
+add wave -noupdate -format Logic /tb_emac_jb/mrdy_i
+add wave -noupdate -format Logic /tb_emac_jb/srdy_o
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/addr_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/dat_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/dat_o
+add wave -noupdate -format Logic /tb_emac_jb/mii_rx_clk
+add wave -noupdate -format Logic /tb_emac_jb/mii_tx_clk
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/mii_rx
+add wave -noupdate -format Logic /tb_emac_jb/mii_rx_dv
+add wave -noupdate -format Logic /tb_emac_jb/mii_rx_er
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/mii_tx
+add wave -noupdate -format Logic /tb_emac_jb/mii_tx_en
+add wave -noupdate -format Logic /tb_emac_jb/mii_tx_er
+add wave -noupdate -format Logic /tb_emac_jb/mii_crs
+add wave -noupdate -format Logic /tb_emac_jb/mii_col
+add wave -noupdate -format Logic /tb_emac_jb/mii_gtx_clk
+add wave -noupdate -divider {Ethernet MAC}
+add wave -noupdate -format Logic /tb_emac_jb/clk
+add wave -noupdate -format Literal /tb_emac_jb/emac_action
+add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_err
+add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_flush_en
+add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_flush_rdy
+add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_free_en
+add wave -noupdate -format Literal -radix unsigned /tb_emac_jb/inst_emac_jb/tx_nwords_free
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_flush_ptr
+add wave -noupdate -format Logic /tb_emac_jb/clk
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_fill_size
+add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_fill_cnt_set
+add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_fill_cnt_adv
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_fill_cnt
+add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_fill_ptr_set
+add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_fill_ptr_adv
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_fill_ptr
+add wave -noupdate -format Logic /tb_emac_jb/clk
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_alloc_base
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_alloc_size
+add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_alloc_ok
+add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_alloc_req_en
+add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_commit_en
+add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_alloc_req
+add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_alloc_ack
+add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_ram_en_a
+add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_ram_en_b
+add wave -noupdate -format Literal /tb_emac_jb/inst_emac_jb/host_tx_s
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_tag_out_b
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_data_out_b
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_tag_in_b
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_data_in_b
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_addr_b
+add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_ram_we_b
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_tag_out_a
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_data_out_a
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_tag_in_a
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_data_in_a
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_addr_a
+add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_ram_we_a
+add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_free_en
+add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_xfer_ptr_set
+add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_xfer_ptr_adv
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_xfer_ptr
+add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_xfer_cnt_set
+add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_xfer_cnt_adv
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_xfer_cnt
+add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_xfer_rdy
+add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_xfer_en
+add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_data_vld
+add wave -noupdate -format Literal /tb_emac_jb/inst_emac_jb/xfer_tag
+add wave -noupdate -format Literal /tb_emac_jb/inst_emac_jb/xfer_remain
+add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/xfer_odd
+add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/xfer_remain_en
+add wave -noupdate -format Literal /tb_emac_jb/inst_emac_jb/xfer_tx_s
+add wave -noupdate -format Literal /tb_emac_jb/inst_emac_jb/piso_din_be
+add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/piso_din_rdy
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_xfer_size
+add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_fifo_we
+add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_fifo_full
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_fifo_din
+add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_fifo_empty
+add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_fifo_re
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_fifo_dout
+add wave -noupdate -format Logic /tb_emac_jb/mii_tx_clk
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/host_tx_size
+add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/host_data_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/host_data_reg
+add wave -noupdate -format Literal /tb_emac_jb/inst_emac_jb/inter_frame_gap_cnt
+add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/inter_frame_gap_rdy
+add wave -noupdate -divider Shifter
+add wave -noupdate -format Logic /tb_emac_jb/clk
+add wave -noupdate -format Literal /tb_emac_jb/shift_sa
+add wave -noupdate -format Logic /tb_emac_jb/shift_din_vld
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/shift_din
+add wave -noupdate -format Logic /tb_emac_jb/shift_dout_vld
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/shift_dout
+add wave -noupdate -divider PiSo
+add wave -noupdate -format Logic /tb_emac_jb/clk
+add wave -noupdate -format Logic /tb_emac_jb/piso_din_vld
+add wave -noupdate -format Logic /tb_emac_jb/piso_din_rdy
+add wave -noupdate -format Literal /tb_emac_jb/piso_din_be
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/piso_din
+add wave -noupdate -format Logic /tb_emac_jb/piso_dout_en
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/piso_dout
+add wave -noupdate -format Logic /tb_emac_jb/inst_piso/pre_fin
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_piso/din_reg
+add wave -noupdate -format Literal /tb_emac_jb/inst_piso/din_be_reg
+add wave -noupdate -format Logic /tb_emac_jb/inst_piso/din_vld_reg
+add wave -noupdate -format Literal /tb_emac_jb/inst_piso/shift_cnt_pipe
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_piso/shift_pipe
+add wave -noupdate -format Literal /tb_emac_jb/inst_piso/vld_pipe
+add wave -noupdate -format Logic /tb_emac_jb/piso2_din_vld
+add wave -noupdate -format Logic /tb_emac_jb/piso2_din_rdy
+add wave -noupdate -format Literal /tb_emac_jb/piso2_din_be
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/piso2_din
+add wave -noupdate -format Logic /tb_emac_jb/piso2_dout_en
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/piso2_dout
+add wave -noupdate -format Logic /tb_emac_jb/piso2_enable
+add wave -noupdate -format Logic /tb_emac_jb/inst_piso2/pre_fin
+add wave -noupdate -format Logic /tb_emac_jb/inst_piso2/rdy
+add wave -noupdate -format Literal /tb_emac_jb/inst_piso2/shift_cnt_pipe
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_piso2/shift_pipe
+add wave -noupdate -format Literal /tb_emac_jb/inst_piso2/vld_pipe
+add wave -noupdate -divider SiPo
+add wave -noupdate -format Logic /tb_emac_jb/inst_sipo/clk
+add wave -noupdate -format Logic /tb_emac_jb/sipo_enable
+add wave -noupdate -format Logic /tb_emac_jb/sipo_din_vld
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/sipo_din
+add wave -noupdate -format Logic /tb_emac_jb/sipo_dout_en
+add wave -noupdate -format Logic /tb_emac_jb/sipo_dout_vld
+add wave -noupdate -format Literal /tb_emac_jb/sipo_dout_be
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/sipo_dout
+add wave -noupdate -format Logic /tb_emac_jb/inst_sipo/pre_fin
+add wave -noupdate -format Logic /tb_emac_jb/inst_sipo/abort
+add wave -noupdate -format Literal /tb_emac_jb/inst_sipo/shift_cnt_pipe
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_sipo/shift_pipe
+add wave -noupdate -format Logic /tb_emac_jb/sipo2_enable
+add wave -noupdate -format Logic /tb_emac_jb/sipo2_rst
+add wave -noupdate -format Logic /tb_emac_jb/sipo2_din_vld
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/sipo2_din
+add wave -noupdate -format Logic /tb_emac_jb/sipo2_dout_en
+add wave -noupdate -format Logic /tb_emac_jb/sipo2_dout_vld
+add wave -noupdate -format Literal /tb_emac_jb/sipo2_dout_be
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/sipo2_dout
+add wave -noupdate -format Literal /tb_emac_jb/inst_sipo2/shift_cnt_pipe
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_sipo2/shift_pipe
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {19622640 ps} 0} {{Cursor 2} {121551751 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 100
+configure wave -griddelta 40
+configure wave -timeline 1
+update
+WaveRestoreZoom {0 ps} {21 us}

lib/emac/sim/tb_emac_top_jb.fdo

@@ -0,0 +1,28 @@
+## NOTE:  Do not edit this file.
+## Autogenerated by ProjNav (creatfdo.tcl) on Thu Jul 06 20:49:07 Westeuropäische Sommerzeit 2006
+##
+vlib work
+vcom -explicit  -93 "../../misc/utils_pkg.vhd"
+vcom -explicit  -93 "../../misc/dpram_1w1r.vhd"
+vcom -explicit  -93 "../../misc/dpram_2w2r.vhd"
+vcom -explicit  -93 "../../FIFO/src/fifo_ctrl_pkg.vhd"
+vcom -explicit  -93 "../../FIFO/src/fifo_sync_ctrl.vhd"
+vcom -explicit  -93 "../../FIFO/src/fifo_sync.vhd"
+vcom -explicit  -93 "../../FIFO/src/gray_counter.vhd"
+vcom -explicit  -93 "../../FIFO/src/fifo_async_ctrl.vhd"
+vcom -explicit  -93 "../../FIFO/src/fifo_async.vhd"
+vcom -explicit  -93 "../src/piso.vhd"
+vcom -explicit  -93 "../src/sipo.vhd"
+vcom -explicit  -93 "../src/shifter.vhd"
+vcom -explicit  -93 "../src/emac_types.vhd"
+vcom -explicit  -93 "../src/emac_rx.vhd"
+vcom -explicit  -93 "../src/emac_tx.vhd"
+vcom -explicit  -93 "../src/emac_top_jb.vhd"
+vcom -explicit  -93 "../src/tb_emac_top_jb.vhd"
+vsim -t 1ps   -lib work tb_emac_top_jb
+view wave
+do {tb_emac_top_jb.wdo}
+view structure
+view signals
+
+run 250 us

lib/emac/sim/tb_emac_top_jb.wdo

@@ -0,0 +1,207 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -divider {Ethernet MAC}
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/clk_i
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/rst_i
+add wave -noupdate -format Logic -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/int_o
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/cyc_i
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/stb_i
+add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/sel_i
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/we_i
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/ack_o
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/srdy_o
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mrdy_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/addr_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/dat_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/dat_o
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_rx_clk
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_rx_dv
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_rx_er
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/mii_rx
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_tx_clk
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_tx_en
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_tx_er
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/mii_tx
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_gtx_clk
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_crs
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_col
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/dat_o_reg
+add wave -noupdate -format Literal /tb_emac_top_jb/emac_action
+add wave -noupdate -format Logic /tb_emac_top_jb/dat_o_cnt_rst
+add wave -noupdate -format Literal /tb_emac_top_jb/dat_o_cnt
+add wave -noupdate -format Literal /tb_emac_top_jb/pkt_count
+add wave -noupdate -divider {Packet generator}
+add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/tx_packets
+add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/tx_bytes
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_pkt_gen/pkt_data
+add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_pkt_gen/pkt_nbytes
+add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_pkt_gen/pkt_nwords
+add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/pkt_delay
+add wave -noupdate -divider RX
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/clk
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/rst
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/dout_vld
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/dout
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ctrl_in
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ctrl_out
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_rx_clk
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_rx_dv
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_rx_er
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_rx
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_crs
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_col
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_fifo_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_fifo_dout
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_fifo_we
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_fifo_re
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_fifo_empty
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_fifo_full
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_dout
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_we
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_re
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_empty
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_full
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/fill_ptr
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/commit_en
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_ram_limit
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_ram_full
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_base
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_size
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_ptr
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_ptr_set
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_ptr_adv
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_cnt_set
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_cnt_adv
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_rdy
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_en_a
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_we_a
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_addr_a
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_din_a
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_dout_a
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_en_b
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_we_b
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_addr_b
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_din_b
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo_32bit_dout
+add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo_32bit_dout_be
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo_32bit_dout_vld
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo_32bit_dout_en
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo_32bit_en
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo_32bit_rst
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo_8bit_dout
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo_8bit_rst
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo_8bit_dout_vld
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo_8bit_dout_en
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo_8bit_en
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/byte_count_en
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/byte_count
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/byte_count_reg
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/word_count
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/word_count_en
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/size_fifo_full
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/size_fifo_empty
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/size_fifo_we
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/size_fifo_re
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/size_fifo_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/size_fifo_dout
+add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/host_s
+add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_s
+add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/stream_s
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/preamble_rst
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/preamble_bsy
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/preamble_ok
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/preamble_rdy
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_rdy
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_ok
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_rst
+add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_num_ok
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_addr
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo_8bit_dout_vld
+add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_cnt
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo_8bit_dout
+add wave -noupdate -divider TX
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/clk
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/rst
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/din_vld
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/din
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ctrl_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ctrl_out
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_tx_clk
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_tx_en
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_tx_er
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_tx
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_dout
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_we
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_re
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_empty
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_full
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_pre_rdy
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_bsy
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_set
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_en
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_cnt_en
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_base
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_size
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_cnt
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_ptr
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_remain
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/alloc_ok
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/alloc_req
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/alloc_ack
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/nwords_free
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/alloc_size
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mem_alloc_en
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mem_free_en
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/commit_en
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/uncommit_en
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_bsy
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_size
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_ptr
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_cnt
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_cnt_en
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_en
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_set
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_en_a
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_we_a
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_addr_a
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_din_a
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_dout_a
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_en_b
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_addr_b
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_din_b
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_dout_b
+add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ifg_cnt
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ifg_idle
+add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_din_be
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_din_rdy
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_din_vld
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_dout
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_dout_vld
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_dout_en
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_dout
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_we
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_re
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_empty
+add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_full
+add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/stream_s
+add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/host_s
+add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_s
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {18401055846 ps} 0} {{Cursor 2} {49999375873 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 100
+configure wave -griddelta 40
+configure wave -timeline 1
+update
+WaveRestoreZoom {3250153138 ps} {28560670888 ps}

lib/emac/src/emac_rx.vhd

@@ -0,0 +1,701 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+use std.textio.all; --  Imports the standard textio package.
+
+use work.emac_types.all;
+use work.utils_pkg.all;
+
+ENTITY emac_rx IS
+	Generic
+	(
+		f_sysclk		: real		:= 100.0;
+		RAM_SIZE		: natural	:= 2048
+	);
+	Port
+	(
+		clk				: in  STD_LOGIC;
+		rst				: in  STD_LOGIC;
+		dout_vld		: out STD_LOGIC;
+		dout			: out unsigned(31 downto 0);
+		ctrl_in			: in  rx_ctrl_in_t;
+		ctrl_out		: out rx_ctrl_out_t;
+		mii_rx_clk		: in  STD_LOGIC;
+		mii_rx_dv		: in  STD_LOGIC;
+		mii_rx_er		: in  STD_LOGIC;
+		mii_rx			: in  unsigned(7 downto 0);
+		mii_crs			: in  STD_LOGIC;
+		mii_col			: in  STD_LOGIC
+		
+	);
+END emac_rx;
+
+ARCHITECTURE behavior OF emac_rx IS
+
+	constant RAM_ADDR_WIDTH	: natural := NextExpBaseTwo(RAM_SIZE);
+	
+	subtype word_ptr_t is unsigned(RAM_ADDR_WIDTH-1 downto 0);
+	
+	-- Signals for EMAC connections
+	signal mii_fifo_din		: unsigned(31 downto 0);
+	signal mii_fifo_dout	: unsigned(31 downto 0);
+	signal mii_fifo_we		: std_logic;
+	signal mii_fifo_re		: std_logic;
+	signal mii_fifo_empty	: std_logic;
+	signal mii_fifo_full	: std_logic;
+
+	signal cmd_fifo_din		: unsigned(2*word_ptr_t'length+2 downto 0);
+	signal cmd_fifo_dout	: unsigned(2*word_ptr_t'length+2 downto 0);
+	signal cmd_fifo_we		: std_logic;
+	signal cmd_fifo_re		: std_logic;
+	signal cmd_fifo_empty	: std_logic;
+	signal cmd_fifo_full	: std_logic;
+
+	signal reset_en			: std_logic;
+	
+	signal fill_ptr			: word_ptr_t;
+
+	signal commit_en		: std_logic;
+
+	signal xfer_ram_limit	: word_ptr_t;
+	signal xfer_ram_full	: std_logic;
+	signal xfer_base		: word_ptr_t;
+	signal xfer_size		: word_ptr_t;
+	signal xfer_ptr			: word_ptr_t;
+	signal xfer_ptr_set		: std_logic;
+	signal xfer_ptr_adv		: std_logic;
+	signal xfer_cnt_set		: std_logic;
+	signal xfer_cnt_adv		: std_logic;
+	signal xfer_rdy			: std_logic;
+	signal xfer_vld			: std_logic;
+
+	signal ram_en_a			: std_logic;
+	signal ram_we_a			: std_logic;
+	signal ram_addr_a		: word_ptr_t;
+	signal ram_din_a		: unsigned(31 downto 0);
+	signal ram_dout_a		: unsigned(31 downto 0);
+	signal ram_en_b			: std_logic;
+	signal ram_we_b			: std_logic;
+	signal ram_addr_b		: word_ptr_t;
+	signal ram_din_b		: unsigned(31 downto 0);
+
+	signal sipo_32bit_dout		: unsigned(31 downto 0);
+	signal sipo_32bit_dout_be	: unsigned(3 downto 0);
+	signal sipo_32bit_dout_vld	: std_logic;
+	signal sipo_32bit_dout_en	: std_logic;
+	signal sipo_32bit_en		: std_logic;
+	signal sipo_32bit_rst		: std_logic;
+	
+	signal sipo_8bit_dout		: unsigned(7 downto 0);
+	signal sipo_8bit_rst		: std_logic;
+	signal sipo_8bit_dout_vld	: std_logic;
+	signal sipo_8bit_dout_en	: std_logic;
+	signal sipo_8bit_en		: std_logic;
+
+	signal byte_count_en	: std_logic;
+	signal byte_count		: word_ptr_t;
+	signal byte_count_reg	: word_ptr_t;
+
+	signal word_count		: word_ptr_t;
+	signal word_count_en	: std_logic;
+
+	signal size_fifo_full	: std_logic;
+	signal size_fifo_empty	: std_logic;
+	signal size_fifo_we		: std_logic;
+	signal size_fifo_re		: std_logic;
+	signal size_fifo_din	: unsigned(2*word_ptr_t'length+2 downto 0);
+	signal size_fifo_dout	: unsigned(2*word_ptr_t'length+2 downto 0);
+
+	signal reset_pipe		: unsigned(31 downto 0);
+
+	signal preamble_rst		: std_logic;
+	signal preamble_rdy		: std_logic;
+	signal preamble_bsy		: std_logic;
+	signal preamble_OK		: std_logic;
+
+	signal mac_chk_rdy		: std_logic;
+	signal mac_chk_BC		: std_logic;
+	signal mac_chk_OK		: std_logic;
+	signal mac_chk_rst		: std_logic;
+	signal mac_chk_num_OK	: natural range 0 to 6;
+	signal mac_chk_num_BC	: natural range 0 to 6;
+	signal mac_chk_cnt		: natural range 0 to 5;
+	signal mac_chk_addr		: mac_addr_t;
+	
+	type host_state_t is (host_init, host_flush, host_idle);
+	signal host_s, host_sn : host_state_t;
+
+	type xfer_state_t is (xfer_init, xfer_idle, xfer_setup, xfer_active, xfer_drop, xfer_commit, xfer_free);
+	signal xfer_s, xfer_sn : xfer_state_t;
+
+	type stream_state_t is (stream_init, stream_reset, stream_idle, stream_active, stream_stop, stream_finish);
+	signal stream_s, stream_sn : stream_state_t;
+
+	alias cmd_mac_ok_in is cmd_fifo_din(cmd_fifo_din'left);
+	alias cmd_bcast_in is cmd_fifo_din(cmd_fifo_din'left-1);
+	alias cmd_invalid_in is cmd_fifo_din(cmd_fifo_din'left-2);
+	alias cmd_nbytes_in is cmd_fifo_din(word_ptr_t'length-1 downto 0);
+	alias cmd_base_in is cmd_fifo_din(2*word_ptr_t'length-1 downto word_ptr_t'length);
+
+	alias cmd_mac_ok_out is cmd_fifo_dout(cmd_fifo_dout'left);
+	alias cmd_bcast_out is cmd_fifo_dout(cmd_fifo_dout'left-1);
+	alias cmd_invalid_out is cmd_fifo_dout(cmd_fifo_dout'left-2);
+	alias cmd_nbytes_out is cmd_fifo_dout(word_ptr_t'length-1 downto 0);
+	alias cmd_base_out is cmd_fifo_dout(2*word_ptr_t'length-1 downto word_ptr_t'length);
+
+	alias stream_mac_ok_in is size_fifo_din(size_fifo_din'left);
+	alias stream_broadcast_in is size_fifo_din(size_fifo_din'left-1);
+	alias stream_badcrc_in is size_fifo_din(size_fifo_din'left-2);
+	alias stream_nbytes_in is size_fifo_din(word_ptr_t'length-1 downto 0);
+	alias stream_nwords_in is size_fifo_din(2*word_ptr_t'length-1 downto word_ptr_t'length);
+
+	alias stream_mac_ok_out is size_fifo_dout(size_fifo_dout'left);
+	alias stream_broadcast_out is size_fifo_dout(size_fifo_dout'left-1);
+	alias stream_badcrc_out is size_fifo_dout(size_fifo_dout'left-2);
+	alias stream_nbytes_out is size_fifo_dout(word_ptr_t'length-1 downto 0);
+	alias stream_nwords_out is size_fifo_dout(2*word_ptr_t'length-1 downto word_ptr_t'length);
+
+begin
+
+	ctrl_out.rx_size		<= resize(cmd_nbytes_out, 16);
+	ctrl_out.pkt_avail		<= not cmd_fifo_empty;
+	ctrl_out.rx_er			<= mii_rx_er;
+	ctrl_out.reset_busy		<= reset_en;
+	ctrl_out.pkt_bcast		<= cmd_bcast_out;
+	ctrl_out.pkt_mac_match	<= cmd_mac_ok_out;
+
+	dout					<= ram_dout_a;
+
+	mii_fifo_din			<= sipo_32bit_dout;
+	mii_fifo_we				<= word_count_en and sipo_32bit_dout_vld;
+
+	ram_en_a				<= '1';
+	ram_din_a				<= (others => '-');
+	ram_addr_a				<= fill_ptr;
+	ram_we_a				<= '0';
+
+	ram_en_b				<= '1';
+	ram_din_b				<= mii_fifo_dout;
+	ram_addr_b				<= xfer_ptr;
+	ram_we_b				<= xfer_ptr_adv;
+	
+	cmd_fifo_we				<= commit_en;
+	cmd_fifo_re				<= ctrl_in.pkt_free_en;
+
+	cmd_mac_ok_in			<= stream_mac_ok_out;
+	cmd_bcast_in			<= stream_broadcast_out;
+	cmd_invalid_in			<= stream_badcrc_out;
+	cmd_nbytes_in			<= stream_nbytes_out;
+	cmd_base_in				<= xfer_base;
+	
+	stream_nbytes_in		<= byte_count_reg;
+	stream_nwords_in		<= word_count;
+	stream_mac_ok_in		<= mac_chk_OK;
+	stream_broadcast_in		<= mac_chk_BC;
+	stream_badcrc_in		<= '0';
+	
+	reset_en				<= reset_pipe(reset_pipe'left);
+	
+------------------------------------------------------------------
+reset_gen:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if rst = '1' or ctrl_in.reset = '1' then
+				reset_pipe	<= (others => '1');
+			else
+				reset_pipe	<= reset_pipe(reset_pipe'left-1 downto 0) & '0';
+			end if;
+		end if;
+	end process;	
+
+------------------------------------------------------------------
+-- Fill stuff
+------------------------------------------------------------------
+fill_pointer:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			dout_vld			<= ctrl_in.pkt_read_en;
+			if ctrl_in.pkt_req_en = '1' then
+				fill_ptr		<= cmd_base_out;
+			elsif ctrl_in.pkt_read_en = '1' then
+				fill_ptr		<= fill_ptr + 1;
+			end if;
+		end if;
+	end process;	
+
+------------------------------------------------------------------
+-- Transfer stuff
+------------------------------------------------------------------
+xfer_state_next:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if reset_en = '1' then
+				xfer_s	<= xfer_init;
+			else
+				xfer_s	<= xfer_sn;
+			end if;
+		end if;
+	end process;	
+
+xfer_state:
+	process(xfer_s, size_fifo_empty, mii_fifo_empty, xfer_rdy, xfer_vld, xfer_ram_full)
+	begin
+	
+		commit_en			<= '0';
+		xfer_ptr_set		<= '0';
+		xfer_ptr_adv		<= '0';
+		xfer_cnt_set		<= '0';
+		xfer_cnt_adv		<= '0';
+		size_fifo_re		<= '0';
+		mii_fifo_re			<= '0';
+
+		xfer_sn				<= xfer_s;
+		
+		case xfer_s is
+		
+		when xfer_init =>
+			xfer_sn 		<= xfer_idle;
+		
+		when xfer_idle =>
+			if mii_fifo_empty = '0' then
+				xfer_sn		<= xfer_setup;
+			end if;	
+			
+		when xfer_setup =>
+			xfer_cnt_set	<= '1';
+			xfer_ptr_set	<= '1';
+			xfer_sn			<= xfer_active;
+		
+		when xfer_active =>
+			mii_fifo_re		<= '1';
+			xfer_cnt_adv	<= not mii_fifo_empty;
+			xfer_ptr_adv	<= not mii_fifo_empty;
+			if xfer_ram_full = '1' then
+				xfer_sn		<= xfer_drop;
+			elsif size_fifo_empty = '0' then
+				if xfer_rdy = '1' then
+					xfer_sn		<= xfer_free;
+				end if;
+			end if;	
+
+		when xfer_drop =>
+			mii_fifo_re		<= '1';
+			xfer_cnt_adv	<= not mii_fifo_empty;
+			if size_fifo_empty = '0' then
+				if xfer_rdy = '1' then
+					xfer_sn		<= xfer_free;
+				end if;
+			end if;			
+
+		when xfer_free =>
+			size_fifo_re	<= '1';
+			commit_en		<= not xfer_ram_full and xfer_vld;
+			xfer_sn			<= xfer_idle;
+
+		when others => 
+			xfer_sn				<= xfer_idle;
+		end case;
+
+	end process;
+
+------------------------------------------------------------------
+pkt_lost_register:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if reset_en = '1' then
+				ctrl_out.pkt_lost	<= '0';
+			elsif size_fifo_re = '1' and xfer_ram_full = '1' then
+				ctrl_out.pkt_lost	<= '1';
+			elsif ctrl_in.pkt_free_en = '1' then
+				ctrl_out.pkt_lost	<= '0';
+			end if;
+		end if;	
+			
+	end process;	
+
+xfer_limit_register:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if xfer_ptr_set = '1' then
+				if cmd_fifo_empty = '1' then
+					xfer_ram_limit	<= xfer_base - 1;
+				else
+					xfer_ram_limit <= cmd_base_out - 1;
+				end if;
+			end if;
+		end if;	
+			
+	end process;	
+
+xfer_ram_full_detect:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if xfer_ptr_set = '1' or reset_en = '1' then
+				xfer_ram_full	<= '0';
+			elsif xfer_ptr_adv = '1' then
+				if xfer_ptr = xfer_ram_limit then
+					xfer_ram_full <= '1';
+				end if;
+			end if;
+		end if;	
+			
+	end process;	
+
+xfer_counter:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if xfer_cnt_set = '1' then
+				xfer_rdy	<= '0';
+				xfer_vld	<= '0';
+			elsif xfer_size = stream_nwords_out then
+				xfer_rdy	<= '1';
+				xfer_vld	<= stream_mac_ok_out or stream_broadcast_out or ctrl_in.promiscious;
+			end if;			
+			if xfer_cnt_set = '1' then
+				xfer_size		<= (others => '0');
+			elsif xfer_cnt_adv = '1' then
+				xfer_size	<= xfer_size + 1;
+			end if;
+		end if;	
+			
+	end process;	
+	
+xfer_pointer:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if xfer_ptr_set = '1' then
+				xfer_ptr		<= xfer_base;
+			elsif xfer_ptr_adv = '1' then
+				xfer_ptr		<= xfer_ptr + 1;
+			end if;
+		end if;	
+			
+	end process;	
+	
+xfer_base_logic:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if reset_en = '1' then
+				xfer_base		<= (others => '0');
+			elsif commit_en = '1' then
+				xfer_base		<= xfer_ptr;
+			end if;
+		end if;
+	end process;	
+
+------------------------------------------------------------------
+byte_counter:
+	process(mii_rx_clk)
+	begin
+		if rising_edge(mii_rx_clk) then
+			if sipo_8bit_rst = '1' then
+				byte_count		<= (others => '0');
+			elsif byte_count_en = '1' and sipo_8bit_dout_vld = '1' then
+				byte_count		<= byte_count + 1;
+			end if;
+		end if;
+	end process;	
+
+byte_count_register:
+	process(mii_rx_clk)
+	begin
+		if rising_edge(mii_rx_clk) then
+			if sipo_8bit_rst = '1' then
+				byte_count_reg		<= byte_count;
+			end if;
+		end if;
+	end process;	
+
+word_counter:
+	process(mii_rx_clk)
+	begin
+		if rising_edge(mii_rx_clk) then
+			if sipo_32bit_rst = '1' then
+				word_count		<= (others => '0');
+			elsif word_count_en = '1' and sipo_32bit_dout_vld = '1' then
+				word_count		<= word_count + 1;
+			end if;
+		end if;
+	end process;	
+
+preamble_sync_logic:
+	process(mii_rx_clk)
+	begin
+		if rising_edge(mii_rx_clk) then
+			if preamble_rst = '1' then
+				preamble_rdy	<= '0';
+				preamble_bsy	<= '0';
+				preamble_OK		<= '0';
+			elsif sipo_8bit_dout_vld = '1' then
+				if preamble_bsy = '1' then
+					if sipo_8bit_dout = X"D5" then
+						preamble_OK		<= '1';
+					end if;
+				end if;
+				if sipo_8bit_dout /= X"55" then
+					preamble_bsy	<= '0';
+					preamble_rdy	<= preamble_bsy;
+				else
+					preamble_bsy	<= '1';
+				end if;
+			end if;
+		end if;
+	end process;	
+
+mac_check_logic:
+	process(mii_rx_clk)
+	begin
+		if rising_edge(mii_rx_clk) then
+			if mac_chk_rst = '1' then
+				mac_chk_rdy			<= '0';
+				mac_chk_OK			<= '0';
+				mac_chk_BC			<= '0';
+				mac_chk_cnt			<= 0;
+				mac_chk_num_OK		<= 0;
+				mac_chk_num_BC		<= 0;
+				mac_chk_addr		<= ctrl_in.mac_addr;
+			elsif mac_chk_rdy = '1' then
+				if mac_chk_num_OK = 6 then 
+					mac_chk_OK	<= '1';
+				end if;
+				if mac_chk_num_BC = 6 then 
+					mac_chk_BC	<= '1';
+				end if;
+			elsif sipo_8bit_dout_vld = '1' then
+				if sipo_8bit_dout = mac_chk_addr(mac_chk_cnt) then
+					mac_chk_num_OK	<= mac_chk_num_OK + 1;
+				end if;
+				if sipo_8bit_dout = X"FF" then
+					mac_chk_num_BC	<= mac_chk_num_BC + 1;
+				end if;
+				if mac_chk_cnt /= 5 then
+					mac_chk_cnt			<= mac_chk_cnt + 1;
+				else
+					mac_chk_rdy			<= '1';
+				end if;
+			end if;
+		end if;
+	end process;	
+
+------------------------------------------------------------------
+stream_state_next:
+	process(mii_rx_clk)
+	begin
+		if rising_edge(mii_rx_clk) then
+			if reset_en = '1' then
+				stream_s	<= stream_init;
+			else
+				stream_s	<= stream_sn;
+			end if;
+		end if;
+	end process;	
+
+stream_state:
+	process(stream_s, reset_en, sipo_8bit_dout_en, sipo_8bit_dout, sipo_32bit_dout_en, sipo_32bit_dout_vld, preamble_rdy, preamble_OK)
+	begin
+	
+		sipo_32bit_en		<= '0';
+		sipo_32bit_rst		<= reset_en;
+		sipo_8bit_rst		<= reset_en;
+		word_count_en		<= '0';
+		byte_count_en		<= '0';
+		size_fifo_we		<= '0';
+		preamble_rst		<= reset_en;
+		mac_chk_rst			<= reset_en;
+		
+		sipo_32bit_en		<= sipo_8bit_dout_en;
+
+		stream_sn			<= stream_s;
+		
+		case stream_s is
+		
+		when stream_init =>
+			if sipo_8bit_dout_en = '0' then
+				stream_sn 			<= stream_reset;
+			end if;
+			
+		when stream_reset =>
+			sipo_32bit_rst		<= '1';
+			sipo_8bit_rst		<= '1';
+			preamble_rst		<= '1';
+			stream_sn 			<= stream_idle;
+
+		when stream_idle =>
+			sipo_32bit_en		<= '0';
+			if preamble_rdy = '1' then
+				stream_sn 		<= stream_init;
+				if preamble_OK = '1' then
+					byte_count_en	<= '1';
+					mac_chk_rst		<= '1';
+					sipo_32bit_rst	<= '1';
+					stream_sn 		<= stream_active;
+				end if;
+			end if;			
+			
+		when stream_active =>
+			word_count_en		<= sipo_32bit_dout_en;
+			byte_count_en		<= sipo_8bit_dout_en;
+			if sipo_8bit_dout_en = '0' then
+				stream_sn 		<= stream_stop;
+				sipo_8bit_rst	<= '1';
+			end if;
+
+		when stream_stop =>
+			word_count_en		<= sipo_32bit_dout_en;
+			byte_count_en		<= sipo_8bit_dout_en;
+			if sipo_32bit_dout_en = '0' then
+				stream_sn 		<= stream_finish;
+			end if;
+
+		when stream_finish =>
+			size_fifo_we	<= '1';
+			stream_sn		<= stream_init;
+
+		when others => 
+			stream_sn		<= stream_init;
+		end case;
+
+	end process;
+
+------------------------------------------------------------------
+-- Instantiate synchronous FIFO
+inst_cmd_fifo: entity work.fifo_sync
+	GENERIC MAP
+	(
+		addr_width			=> NextExpBaseTwo(RAM_SIZE) - 4,	-- RAMSIZE(words)/MIN_PACKET_LEN(words)
+		data_width			=> cmd_fifo_din'length,
+		do_last_read_update	=> false
+	)
+	PORT MAP
+	(
+		rst			=>	reset_en,
+		clk			=>	clk,
+		we			=>	cmd_fifo_we,
+		re			=>	cmd_fifo_re,
+		fifo_full	=>	cmd_fifo_full,
+		fifo_empty	=>	cmd_fifo_empty,
+		fifo_afull	=>	open,
+		fifo_aempty	=>	open,
+		data_w		=>  cmd_fifo_din,
+		data_r		=>  cmd_fifo_dout
+	);
+
+inst_ram : entity work.dpram_1w1r
+	GENERIC MAP 
+	(
+		addr_width	=> RAM_ADDR_WIDTH,
+		data_width	=> 32
+	)
+	PORT MAP 
+	(
+		clka		=> clk,
+		clkb		=> clk,
+		en_a		=> ram_en_b,
+		en_b		=> ram_en_a,
+		we_a		=> ram_we_b,
+		addr_a		=> ram_addr_b,
+		addr_b		=> ram_addr_a,
+		din_a		=> ram_din_b,
+		dout_b		=> ram_dout_a
+	);
+
+-- Instantiate synchronous FIFO
+inst_mii_fifo: entity work.fifo_async
+	GENERIC MAP
+	(
+		addr_width			=> 4,
+		data_width			=> mii_fifo_din'length,
+		do_last_read_update	=> true
+	)
+	PORT MAP
+	(
+		rst			=>	reset_en,
+		clk_w		=>	mii_rx_clk,
+		clk_r		=>	clk,
+		we			=>	mii_fifo_we,
+		re			=>	mii_fifo_re,
+		fifo_full	=>	mii_fifo_full,
+		fifo_empty	=>	mii_fifo_empty,
+		fifo_afull	=>	open,
+		fifo_aempty	=>	open,
+		data_w		=>  mii_fifo_din,
+		data_r		=>  mii_fifo_dout
+	);
+
+-- Instantiate synchronous FIFO
+inst_size_fifo: entity work.fifo_async
+	GENERIC MAP
+	(
+		addr_width			=> 1,
+		data_width			=> size_fifo_din'length,
+		do_last_read_update	=> true
+	)
+	PORT MAP
+	(
+		rst			=>	reset_en,
+		clk_w		=>	mii_rx_clk,
+		clk_r		=>	clk,
+		we			=>	size_fifo_we,
+		re			=>	size_fifo_re,
+		fifo_full	=>	size_fifo_full,
+		fifo_empty	=>	size_fifo_empty,
+		fifo_afull	=>	open,
+		fifo_aempty	=>	open,
+		data_w		=>  size_fifo_din,
+		data_r		=>  size_fifo_dout
+	);
+
+inst_sipo : entity work.sipo
+	GENERIC MAP
+	(
+		data_width_in	=> 8,
+		data_width_out	=> 32,
+		msb_first		=> true
+	)
+	PORT MAP
+	(
+		rst			=> sipo_32bit_rst,
+		clk			=> mii_rx_clk,
+		din_vld		=> sipo_8bit_dout_vld,
+		din_en		=> sipo_32bit_en,
+		din			=> sipo_8bit_dout,
+		dout_be		=> sipo_32bit_dout_be,
+		dout_vld	=> sipo_32bit_dout_vld,
+		dout		=> sipo_32bit_dout,
+		dout_en		=> sipo_32bit_dout_en
+		
+	);
+	
+
+inst_sipo_8bit : entity work.sipo
+	GENERIC MAP
+	(
+		data_width_in	=> 4,
+		data_width_out	=> 8,
+		msb_first		=> false
+	)
+	PORT MAP
+	(
+		rst			=> sipo_8bit_rst,
+		clk			=> mii_rx_clk,
+		din_vld		=> mii_rx_dv,
+		din_en		=> sipo_8bit_en,
+		din			=> mii_rx(3 downto 0),
+		dout_be		=> open,
+		dout_vld	=> sipo_8bit_dout_vld,
+		dout		=> sipo_8bit_dout,
+		dout_en		=> sipo_8bit_dout_en
+		
+	);
+	sipo_8bit_en	<= mii_rx_dv;
+	
+end behavior;

lib/emac/src/emac_top_jb.vhd

@@ -0,0 +1,238 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+use std.textio.all; --  Imports the standard textio package.
+
+use work.emac_types.all;
+use work.utils_pkg.all;
+
+ENTITY emac_top_jb IS
+	Generic
+	(
+		f_sysclk	: real		:= 100.0;
+		TX_RAM_SIZE	: natural	:= 2048;
+		RX_RAM_SIZE	: natural	:= 2048
+	);
+	Port
+	(
+		CLK_I		: in  STD_LOGIC;
+		RST_I		: in  STD_LOGIC;
+		INT_O		: out STD_LOGIC;
+		CYC_I		: in  STD_LOGIC;
+		STB_I		: in  STD_LOGIC;
+		SEL_I		: in  unsigned(3 downto 0);
+		WE_I		: in  STD_LOGIC;
+		ACK_O		: out STD_LOGIC;
+		SRDY_O		: out STD_LOGIC;
+		MRDY_I		: in  STD_LOGIC;
+		ADDR_I		: in  unsigned(31 downto 0);
+		DAT_I		: in  unsigned(31 downto 0);
+		DAT_O		: out unsigned(31 downto 0);
+		mii_rx_clk	: in  STD_LOGIC;
+		mii_rx_dv	: in  STD_LOGIC;
+		mii_rx_er	: in  STD_LOGIC;
+		mii_rx		: in unsigned(7 downto 0);
+		mii_tx_clk	: in  STD_LOGIC;
+		mii_tx_en	: out STD_LOGIC;
+		mii_tx_er	: out STD_LOGIC;
+		mii_tx		: out unsigned(7 downto 0);
+		mii_gtx_clk	: out STD_LOGIC;
+		mii_crs		: in  STD_LOGIC;
+		mii_col		: in  STD_LOGIC
+		
+	);
+END emac_top_jb;
+
+ARCHITECTURE behavior OF emac_top_jb IS
+
+	-- Signals for EMAC connections
+	signal tx_ctrl_in		: tx_ctrl_in_t;
+	signal tx_ctrl_out		: tx_ctrl_out_t;
+	signal tx_din			: unsigned(31 downto 0);
+	signal tx_din_vld		: std_logic;
+
+	signal rx_ctrl_in		: rx_ctrl_in_t;
+	signal rx_ctrl_out		: rx_ctrl_out_t;
+
+	signal rx_dout			: unsigned(31 downto 0);
+	signal rx_dout_vld		: std_logic;
+	
+	signal rx_int_en		: std_logic;
+	signal tx_int_en		: std_logic;
+	signal irq_rx			: std_logic;
+	signal irq_tx			: std_logic;
+
+	signal ready			: std_logic;
+
+begin
+
+	SRDY_O				<= CYC_I and ready;
+	mii_gtx_clk			<= '0';
+
+	ready				<= not tx_ctrl_in.pkt_alloc_en;
+	
+------------------------------------------------------------------
+registers_write: 
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			tx_din_vld					<= '0';
+			tx_ctrl_in.pkt_alloc_en		<= '0';
+			tx_ctrl_in.pkt_commit_en	<= '0';
+			tx_ctrl_in.reset			<= '0';
+			rx_ctrl_in.pkt_free_en		<= '0';
+			rx_ctrl_in.pkt_req_en		<= '0';
+			rx_ctrl_in.reset			<= '0';
+			if RST_I = '1' then
+				rx_int_en				<= '0';
+				tx_int_en				<= '0';
+				tx_ctrl_in.tx_er		<= '0';
+				tx_ctrl_in.tx_size		<= (others => '0');
+				rx_ctrl_in.mac_addr		<= (X"03", X"02", X"01", X"00", X"07", X"06");
+				rx_ctrl_in.promiscious	<= '1';
+			elsif (STB_I and CYC_I and WE_I) = '1' then
+				case ADDR_I(5 downto 2) is
+				
+				when "0000" =>
+					tx_ctrl_in.tx_er			<= DAT_I(31);
+					tx_ctrl_in.reset			<= DAT_I(27);
+					tx_ctrl_in.pkt_alloc_en		<= DAT_I(25);
+					tx_ctrl_in.pkt_commit_en	<= DAT_I(24);
+					rx_ctrl_in.reset			<= DAT_I(23);
+					rx_ctrl_in.pkt_free_en		<= DAT_I(17);
+					rx_ctrl_in.pkt_req_en		<= DAT_I(16);
+					tx_int_en					<= DAT_I(5);
+					rx_int_en					<= DAT_I(4);
+					rx_ctrl_in.promiscious		<= DAT_I(3);
+					
+				when "0001" => 
+					tx_ctrl_in.tx_size			<= DAT_I(31 downto 16);
+					
+				when "0010" =>
+					tx_din_vld					<= '1';
+					tx_din						<= DAT_I;
+					
+				when "0100" =>
+					rx_ctrl_in.mac_addr(0)		<= DAT_I(31 downto 24);
+					rx_ctrl_in.mac_addr(1)		<= DAT_I(23 downto 16);
+					rx_ctrl_in.mac_addr(2)		<= DAT_I(15 downto 8);
+					rx_ctrl_in.mac_addr(3)		<= DAT_I(7 downto 0);
+					
+				when "0101" =>
+					rx_ctrl_in.mac_addr(4)		<= DAT_I(31 downto 24);
+					rx_ctrl_in.mac_addr(5)		<= DAT_I(23 downto 16);
+
+				when others => null;
+				end case;
+			end if;	
+		end if;	
+	end process;
+
+registers_read: 
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			rx_ctrl_in.pkt_read_en	<= '0';
+			ACK_O					<= rx_dout_vld and CYC_I and not WE_I;
+			DAT_O					<= rx_dout;
+			if (STB_I and CYC_I) = '1' and WE_I = '0' then
+				case ADDR_I(5 downto 2) is
+
+				when "0000" =>
+					ACK_O		<= ready;
+					DAT_O		<= (others => '0');
+					DAT_O(31)	<= tx_ctrl_in.tx_er;
+					DAT_O(30)	<= mii_rx_er;			-- remove that
+					DAT_O(29)	<= mii_col;				-- remove that
+					DAT_O(28)	<= mii_crs;				-- remove that
+					DAT_O(27)	<= tx_ctrl_out.reset_busy;
+					DAT_O(26)	<= tx_ctrl_out.pkt_done;
+					DAT_O(25)	<= tx_ctrl_out.pkt_alloc_req;
+					DAT_O(24)	<= tx_ctrl_out.pkt_armed;
+					DAT_O(23)	<= rx_ctrl_out.reset_busy;
+					DAT_O(19)	<= rx_ctrl_out.pkt_bcast;
+					DAT_O(18)	<= rx_ctrl_out.pkt_mac_match;
+					DAT_O(17)	<= rx_ctrl_out.pkt_lost;
+					DAT_O(16)	<= rx_ctrl_out.pkt_avail;
+					DAT_O(5)	<= tx_int_en;
+					DAT_O(4)	<= rx_int_en;
+					DAT_O(3)	<= rx_ctrl_in.promiscious;
+					
+				when "0001" => 
+					ACK_O		<= '1';
+					DAT_O		<= tx_ctrl_out.tx_size & rx_ctrl_out.rx_size;
+
+				when "0010" =>
+					rx_ctrl_in.pkt_read_en	<= '1';
+						
+				when "0100" =>
+					ACK_O		<= '1';
+					DAT_O		<= rx_ctrl_in.mac_addr(0) & rx_ctrl_in.mac_addr(1) & rx_ctrl_in.mac_addr(2) & rx_ctrl_in.mac_addr(3);
+	
+				when "0101" =>
+					ACK_O		<= '1';
+					DAT_O		<= rx_ctrl_in.mac_addr(4) & rx_ctrl_in.mac_addr(5) & X"0000";
+				
+				when others => null;
+				end case;
+			end if;
+		end if;	
+	end process;
+
+irq_register:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			INT_O		<= irq_rx or irq_tx;
+			irq_tx		<= tx_int_en and tx_ctrl_out.pkt_done;
+			irq_rx		<= rx_int_en and rx_ctrl_out.pkt_avail;
+		end if;
+	end process;
+
+inst_emac_rx : entity work.emac_rx
+	GENERIC MAP
+	(
+		f_sysclk	=> f_sysclk,
+		RAM_SIZE	=> RX_RAM_SIZE
+	)
+	PORT MAP
+	(
+		clk			=> CLK_I,
+		rst			=> RST_I,
+		dout_vld	=> rx_dout_vld,
+		dout		=> rx_dout,
+		ctrl_in		=> rx_ctrl_in,
+		ctrl_out	=> rx_ctrl_out,
+		mii_rx_clk	=> mii_rx_clk,
+		mii_rx_dv	=> mii_rx_dv,
+		mii_rx_er	=> mii_rx_er,
+		mii_rx		=> mii_rx,
+		mii_crs		=> mii_crs,
+		mii_col		=> mii_col
+		
+	);
+
+
+inst_emac_tx : entity work.emac_tx
+	GENERIC MAP
+	(
+		f_sysclk	=> f_sysclk,
+		RAM_SIZE	=> TX_RAM_SIZE
+	)
+	PORT MAP
+	(
+		clk			=> CLK_I,
+		rst			=> RST_I,
+		din_vld		=> tx_din_vld,
+		din			=> tx_din,
+		ctrl_in		=> tx_ctrl_in,
+		ctrl_out	=> tx_ctrl_out,
+		mii_tx_clk	=> mii_tx_clk,
+		mii_tx_en	=> mii_tx_en,
+		mii_tx_er	=> mii_tx_er,
+		mii_tx		=> mii_tx
+		
+	);
+
+
+end behavior;

lib/emac/src/emac_tx.vhd

@@ -0,0 +1,703 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+use std.textio.all; --  Imports the standard textio package.
+
+use work.emac_types.all;
+use work.utils_pkg.all;
+
+ENTITY emac_tx IS
+	Generic
+	(
+		f_sysclk		: real		:= 100.0;
+		RAM_SIZE		: natural	:= 2048
+	);
+	Port
+	(
+		clk				: in  STD_LOGIC;
+		rst				: in  STD_LOGIC;
+		din_vld			: in  STD_LOGIC;
+		din				: in  unsigned(31 downto 0);
+		ctrl_in			: in  tx_ctrl_in_t;
+		ctrl_out		: out tx_ctrl_out_t;
+		mii_tx_clk		: in  STD_LOGIC;
+		mii_tx_en		: out STD_LOGIC;
+		mii_tx_er		: out STD_LOGIC;
+		mii_tx			: out unsigned(7 downto 0)
+		
+	);
+END emac_tx;
+
+ARCHITECTURE behavior OF emac_tx IS
+
+	constant RAM_ADDR_WIDTH	: natural := NextExpBaseTwo(RAM_SIZE);
+	
+	subtype word_ptr_t is unsigned(RAM_ADDR_WIDTH-1 downto 0);
+	
+	signal mii_fifo_din		: unsigned(35 downto 0);
+	signal mii_fifo_dout	: unsigned(35 downto 0);
+	signal mii_fifo_we		: std_logic;
+	signal mii_fifo_re		: std_logic;
+	signal mii_fifo_empty	: std_logic;
+	signal mii_fifo_full	: std_logic;
+
+	signal cmd_fifo_din		: unsigned(2*word_ptr_t'length-1 downto 0);
+	signal cmd_fifo_dout	: unsigned(2*word_ptr_t'length-1 downto 0);
+	signal cmd_fifo_we		: std_logic;
+	signal cmd_fifo_re		: std_logic;
+	signal cmd_fifo_empty	: std_logic;
+	signal cmd_fifo_full	: std_logic;
+
+	signal reset_en			: std_logic;
+
+	signal fill_base		: word_ptr_t;
+	signal fill_size		: word_ptr_t;
+	signal fill_cnt			: word_ptr_t;
+	signal fill_ptr			: word_ptr_t;
+	signal fill_pre_rdy		: std_logic;
+	signal fill_bsy			: std_logic;
+	signal fill_remain		: unsigned(1 downto 0);
+	signal fill_set			: std_logic;
+	signal fill_en			: std_logic;
+	signal fill_cnt_en		: std_logic;
+
+	signal alloc_OK			: std_logic;
+	signal alloc_req		: std_logic;
+	signal alloc_ack		: std_logic;
+	signal alloc_size		: word_ptr_t;
+	signal alloc_remain		: unsigned(1 downto 0);
+	
+	signal commit_en		: std_logic;
+	signal uncommit_en		: std_logic;
+	signal mem_alloc_en		: std_logic;
+	signal mem_free_en		: std_logic;
+	signal nwords_free		: word_ptr_t;
+
+	signal xfer_size		: word_ptr_t;
+	signal xfer_ptr			: word_ptr_t;
+	signal xfer_cnt			: word_ptr_t;
+	signal xfer_set			: std_logic;
+	signal xfer_en			: std_logic;
+	signal xfer_sync		: unsigned(1 downto 0);
+	signal xfer_cnt_en		: std_logic;
+	signal xfer_bsy			: std_logic;
+
+	signal ram_en_a			: std_logic;
+	signal ram_we_a			: std_logic;
+	signal ram_addr_a		: word_ptr_t;
+	signal ram_din_a		: unsigned(35 downto 0);
+	signal ram_dout_a		: unsigned(35 downto 0);
+	signal ram_en_b			: std_logic;
+	signal ram_addr_b		: word_ptr_t;
+	signal ram_din_b		: unsigned(35 downto 0);
+	signal ram_dout_b		: unsigned(35 downto 0);
+
+	signal piso8_din		: unsigned(31 downto 0);
+	signal piso8_din_be		: unsigned(3 downto 0);
+	signal piso8_din_rdy	: std_logic;
+	signal piso8_din_vld	: std_logic;
+
+	signal piso8_dout		: unsigned(7 downto 0);
+	signal piso8_dout_vld	: std_logic;
+	signal piso8_dout_en	: std_logic;
+	
+	signal piso4_dout_vld	: std_logic;
+	signal piso4_din_rdy	: std_logic;
+	signal piso4_dout		: unsigned(3 downto 0);
+	
+	signal reset_pipe		: unsigned(31 downto 0);
+
+	subtype ifg_cnt_t is natural range 0 to 23;		-- 10/100 mbps
+--	subtype ifg_cnt_t is natural range 0 to 11;		-- 1000 mbps
+
+	signal ifg_cnt			: ifg_cnt_t;
+	signal ifg_idle			: std_logic;
+
+	type host_state_t is (host_init, host_idle, host_alloc, host_setup, host_arm, host_fill, host_commit);
+	signal host_s, host_sn : host_state_t;
+	
+	type xfer_state_t is (xfer_init, xfer_idle, xfer_setup, xfer_arm, xfer_active, xfer_uncommit, xfer_free);
+	signal xfer_s, xfer_sn : xfer_state_t;
+
+	type stream_state_t is (stream_init, stream_idle, stream_start, stream_preamble0, stream_preamble1, stream_active, stream_crc, stream_stop, stream_finish);
+	signal stream_s, stream_sn : stream_state_t;
+
+	type piso_byte_mask_array_t is array (0 to 3) of unsigned (3 downto 0);
+	constant piso_byte_mask_rom : piso_byte_mask_array_t :=
+	(
+		"1111",
+		"1000",
+		"1100",
+		"1110"
+	);
+	
+	signal preamble_en		: std_logic;
+	signal preamble_addr	: natural range 0 to 1;
+	type preamble_t is array (0 to 1) of unsigned(31 downto 0);
+	constant preamble : preamble_t :=
+	(
+		X"55555555",
+		X"555555D5"
+	);
+	
+
+begin
+
+	ctrl_out.pkt_alloc_req	<= alloc_req;
+	ctrl_out.pkt_done		<= cmd_fifo_empty;
+	ctrl_out.reset_busy		<= reset_en;
+	mii_tx_er				<= ctrl_in.tx_er;
+
+	
+	ram_en_a				<= din_vld;
+	ram_we_a				<= fill_bsy;
+	ram_din_a(31 downto 0)	<= din;
+	ram_din_a(35 downto 32)	<= piso_byte_mask_rom(to_integer(fill_remain)) when fill_pre_rdy = '1' else "1111";
+	ram_addr_a				<= fill_ptr;
+	
+	mii_fifo_din			<= ram_dout_b;
+	
+	piso8_din				<= preamble(preamble_addr) when preamble_en = '1' else mii_fifo_dout(31 downto 0);
+	piso8_din_be			<= "1111" when preamble_en = '1' else mii_fifo_dout(35 downto 32);
+
+	cmd_fifo_we				<= commit_en;
+	cmd_fifo_re				<= uncommit_en;
+	cmd_fifo_din			<= fill_size & fill_base;
+	ram_en_b				<= not mii_fifo_full;
+	ram_addr_b				<= xfer_ptr;
+	
+	reset_en				<= reset_pipe(reset_pipe'left);
+	
+	mii_fifo_we				<= xfer_bsy;
+	xfer_cnt_en				<= xfer_bsy and not mii_fifo_full;
+	fill_cnt_en				<= fill_bsy and din_vld;
+	
+------------------------------------------------------------------
+reset_gen:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if rst = '1' or ctrl_in.reset = '1' then
+				reset_pipe	<= (others => '1');
+			else
+				reset_pipe	<= reset_pipe(reset_pipe'left-1 downto 0) & '0';
+			end if;
+		end if;
+	end process;	
+
+------------------------------------------------------------------
+host_state_next:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if reset_en = '1' then
+				host_s	<= host_init;
+			else
+				host_s	<= host_sn;
+			end if;
+		end if;
+	end process;	
+
+host_state:
+	process(host_s, alloc_OK, fill_bsy, ctrl_in.pkt_commit_en, alloc_req)
+	begin
+	
+		fill_set			<= '0';
+		fill_en				<= '0';
+		commit_en			<= '0';
+		alloc_ack			<= '0';
+		mem_alloc_en		<= '0';
+		
+		host_sn				<= host_s;
+		
+		case host_s is
+		
+		when host_init =>
+			host_sn 		<= host_idle;
+		
+		when host_idle =>
+			if alloc_req = '1' then
+				host_sn		<= host_alloc;
+			end if;
+
+		when host_alloc =>
+			if alloc_OK = '1' then
+				host_sn		<= host_setup;
+			else
+				host_sn 	<= host_idle;
+				alloc_ack	<= '1';
+			end if;
+
+		when host_setup =>
+			fill_set		<= '1';
+			host_sn			<= host_arm;
+
+		when host_arm =>
+			fill_en			<= '1';
+			alloc_ack		<= '1';
+			host_sn			<= host_fill;
+
+		when host_fill =>
+			fill_en			<= '1';
+			if alloc_req = '1' then
+				host_sn		<= host_alloc;
+			elsif ctrl_in.pkt_commit_en = '1' then
+				host_sn		<= host_commit;
+			end if;
+		
+		when host_commit =>
+			commit_en		<= '1';
+			mem_alloc_en	<= '1';
+			host_sn			<= host_idle;
+
+		when others => 
+			host_sn			<= host_idle;
+		end case;
+
+	end process;
+
+------------------------------------------------------------------
+-- Allocation stuff
+------------------------------------------------------------------
+alloc_request_logic:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if reset_en = '1' then
+				alloc_req		<= '0';
+			elsif ctrl_in.pkt_alloc_en = '1' and alloc_req = '0' then
+				alloc_req		<= '1';
+				alloc_remain	<= ctrl_in.tx_size(1 downto 0);
+				alloc_size		<= ctrl_in.tx_size(word_ptr_t'left+2 downto 2);
+				if ctrl_in.tx_size(1 downto 0) /= "00" then
+					alloc_size	<= ctrl_in.tx_size(word_ptr_t'left+2 downto 2) + 1;
+				end if;
+				ctrl_out.tx_size	<= resize(ctrl_in.tx_size(word_ptr_t'left downto 0), 16);
+			elsif alloc_ack = '1' then
+				alloc_req				<= '0';
+			end if;
+		end if;
+	end process;	
+
+------------------------------------------------------------------
+host_alloc_armed_register:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if reset_en = '1' or commit_en = '1' then
+				ctrl_out.pkt_armed		<= '0';
+			elsif alloc_ack = '1' then
+				ctrl_out.pkt_armed		<= alloc_OK;
+			end if;
+		end if;
+	end process;	
+
+------------------------------------------------------------------
+alloc_eval_logic:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			alloc_OK	<= '0';
+			if alloc_size < nwords_free then
+				alloc_OK	<= '1';
+			end if;
+		end if;
+	end process;	
+
+------------------------------------------------------------------
+fill_base_logic:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if reset_en = '1' then
+				fill_base		<= (others => '0');
+			elsif commit_en = '1' then
+				fill_base		<= fill_ptr;
+			end if;
+		end if;
+	end process;	
+
+------------------------------------------------------------------
+nwords_free_counter:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if reset_en = '1' then
+				nwords_free		<= (others => '1');
+			elsif mem_alloc_en = '1' then
+				nwords_free		<= nwords_free - fill_size;
+			elsif mem_free_en = '1' then
+				nwords_free		<= nwords_free + xfer_size;
+			end if;
+		end if;
+	end process;	
+
+------------------------------------------------------------------
+-- Fill stuff
+------------------------------------------------------------------
+fill_counter:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if fill_set = '1' then	
+				fill_bsy		<= '0';
+				fill_pre_rdy	<= '0';
+				fill_cnt		<= alloc_size;
+				fill_size		<= alloc_size;
+				fill_remain		<= alloc_remain;
+			elsif fill_en = '1' then
+				fill_bsy	<= '1';
+				if fill_cnt_en = '1' or fill_bsy = '0' then
+					if fill_cnt /= 1 then
+						fill_cnt	<= fill_cnt - 1;
+					else
+						fill_pre_rdy	<= '1';
+					end if;
+					if fill_pre_rdy = '1' then
+						fill_bsy	<= '0';
+					end if;
+				end if;
+			end if;
+		end if;
+	end process;	
+
+fill_pointer:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if fill_set = '1' then
+				fill_ptr		<= fill_base;
+			elsif fill_cnt_en = '1' then
+				fill_ptr		<= fill_ptr + 1;
+			end if;
+		end if;
+	end process;	
+
+------------------------------------------------------------------
+-- Transfer stuff
+------------------------------------------------------------------
+xfer_state_next:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if reset_en = '1' then
+				xfer_s	<= xfer_init;
+			else
+				xfer_s	<= xfer_sn;
+			end if;
+		end if;
+	end process;	
+
+xfer_state:
+	process(xfer_s, cmd_fifo_empty, xfer_bsy, xfer_sync, mem_alloc_en)
+	begin
+	
+		xfer_set			<= '0';
+		xfer_en				<= '0';
+		mem_free_en			<= '0';
+		uncommit_en			<= '0';
+		
+		xfer_sn				<= xfer_s;
+		
+		case xfer_s is
+		
+		when xfer_init =>
+			xfer_sn <= xfer_idle;
+		
+		when xfer_idle =>
+			if cmd_fifo_empty = '0' then
+				xfer_sn			<= xfer_setup;
+			end if;
+			
+		when xfer_setup =>
+			xfer_set			<= '1';
+			xfer_sn				<= xfer_arm;
+
+		when xfer_arm =>
+			xfer_en				<= '1';
+			xfer_sn				<= xfer_active;
+
+		when xfer_active =>
+			xfer_en				<= '1';
+			if xfer_bsy = '0' then
+				xfer_sn			<= xfer_uncommit;
+			end if;	
+
+		when xfer_uncommit =>
+			mem_free_en			<= not mem_alloc_en;
+			if mem_alloc_en = '0' then
+				uncommit_en		<= '1';
+				xfer_sn			<= xfer_free;
+			end if;
+
+		when xfer_free =>
+			if xfer_sync(1) = '1' then
+				xfer_sn			<= xfer_idle;
+			end if;
+
+		when others => 
+			xfer_sn				<= xfer_idle;
+		end case;
+
+	end process;
+
+------------------------------------------------------------------
+interframe_gap_ready:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			xfer_sync(1)	<= xfer_sync(0);
+			xfer_sync(0)	<= mii_fifo_empty;
+		end if;
+	end process;
+
+------------------------------------------------------------------
+interframe_gap_counter:
+	process(mii_tx_clk)
+	begin
+		if rising_edge(mii_tx_clk) then
+			ifg_idle	<= '0';
+			if reset_en = '1' or piso8_dout_vld = '1' then
+				ifg_cnt 	<= ifg_cnt_t'high;
+				ifg_idle	<= '1';
+			elsif ifg_cnt /= 0 then
+				ifg_cnt		<= ifg_cnt - 1;
+			else
+				ifg_idle	<= '1';
+			end if;
+		end if;
+	end process;
+
+------------------------------------------------------------------
+xfer_counter:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			xfer_bsy		<= '0';
+			if xfer_set = '1' then
+				xfer_cnt 		<= cmd_fifo_dout(cmd_fifo_dout'left downto word_ptr_t'length);
+				xfer_size		<= (others => '0');
+			elsif xfer_en = '1' then
+				xfer_bsy	<= '1';
+				if xfer_cnt_en = '1' or xfer_bsy = '0' then
+					if xfer_cnt /= 0 then
+						xfer_cnt	<= xfer_cnt - 1;
+						xfer_size	<= xfer_size + 1;
+					else
+						xfer_bsy	<= '0';
+					end if;
+				end if;
+			end if;
+		end if;	
+			
+	end process;	
+	
+xfer_pointer:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if xfer_set = '1' then
+				xfer_ptr		<= cmd_fifo_dout(xfer_ptr'left downto 0);
+			elsif xfer_en = '1' then
+				if xfer_bsy = '0' or xfer_cnt_en = '1' then
+					xfer_ptr		<= xfer_ptr + 1;
+				end if;
+			end if;
+		end if;	
+			
+	end process;	
+	
+------------------------------------------------------------------
+stream_state_next:
+	process(mii_tx_clk)
+	begin
+		if rising_edge(mii_tx_clk) then
+			if reset_en = '1' then
+				stream_s	<= stream_init;
+			else
+				stream_s	<= stream_sn;
+			end if;
+		end if;
+	end process;	
+
+stream_state:
+	process(stream_s, ifg_idle, mii_fifo_empty, piso8_din_rdy, piso8_dout_vld)
+	begin
+		
+		piso8_din_vld		<= '0';
+		mii_fifo_re			<= '0';
+		preamble_en			<= '0';
+		preamble_addr		<= 0;
+		
+		stream_sn			<= stream_s;
+		
+		case stream_s is
+		
+		when stream_init =>
+			if mii_fifo_empty = '1' then
+				stream_sn 		<= stream_idle;
+			end if;
+			
+		when stream_idle =>
+			if mii_fifo_empty = '0' and piso8_din_rdy = '1' then
+				stream_sn 		<= stream_start;
+			end if;
+			
+		when stream_start =>
+			stream_sn 		<= stream_preamble0;
+
+		when stream_preamble0 =>
+			preamble_addr	<= 0;
+			preamble_en		<= '1';
+			piso8_din_vld	<= '1';
+			if piso8_din_rdy = '1' then
+				stream_sn 		<= stream_preamble1;
+			end if;
+
+		when stream_preamble1 =>
+			preamble_addr	<= 1;
+			preamble_en		<= '1';
+			piso8_din_vld	<= '1';
+			if piso8_din_rdy = '1' then
+				stream_sn 		<= stream_active;
+			end if;
+
+		when stream_active =>
+			piso8_din_vld	<= not mii_fifo_empty;
+			mii_fifo_re		<= piso8_din_rdy;
+			if mii_fifo_empty = '1' then
+				stream_sn 		<= stream_crc;
+			end if;
+
+		when stream_crc =>
+			stream_sn 		<= stream_stop;
+			
+		when stream_stop =>
+			if piso8_dout_vld = '0' then
+				stream_sn 		<= stream_finish;
+			end if;
+
+		when stream_finish =>
+			if ifg_idle = '0' then
+				stream_sn		<= stream_idle;
+			end if;
+
+		when others => 
+			stream_sn		<= stream_idle;
+		end case;
+
+	end process;
+
+------------------------------------------------------------------
+inst_ram : entity work.dpram_1w1r
+	GENERIC MAP 
+	(
+		addr_width	=> RAM_ADDR_WIDTH,
+		data_width	=> ram_din_a'length
+	)
+	PORT MAP 
+	(
+		clka		=> clk,
+		clkb		=> clk,
+		en_a		=> ram_en_a,
+		en_b		=> ram_en_b,
+		we_a		=> ram_we_a,
+		addr_a		=> ram_addr_a,
+		addr_b		=> ram_addr_b,
+		din_a		=> ram_din_a,
+		dout_b		=> ram_dout_b
+	);
+
+-- Instantiate synchronous FIFO
+inst_cmd_fifo: entity work.fifo_sync
+	GENERIC MAP
+	(
+		addr_width			=> NextExpBaseTwo(RAM_SIZE) - 4,	-- RAMSIZE(words)/MIN_PACKET_LEN(words)
+		data_width			=> cmd_fifo_din'length,
+		do_last_read_update	=> true
+	)
+	PORT MAP
+	(
+		rst			=>	reset_en,
+		clk			=>	clk,
+		we			=>	cmd_fifo_we,
+		re			=>	cmd_fifo_re,
+		fifo_full	=>	cmd_fifo_full,
+		fifo_empty	=>	cmd_fifo_empty,
+		fifo_afull	=>	open,
+		fifo_aempty	=>	open,
+		data_w		=>  cmd_fifo_din,
+		data_r		=>  cmd_fifo_dout
+	);
+
+-- Instantiate synchronous FIFO
+inst_mii_fifo: entity work.fifo_async
+	GENERIC MAP
+	(
+		addr_width			=> 4,
+		data_width			=> mii_fifo_din'length,
+		do_last_read_update	=> true
+	)
+	PORT MAP
+	(
+		rst			=>	reset_en,
+		clk_w		=>	clk,
+		clk_r		=>	mii_tx_clk,
+		we			=>	mii_fifo_we,
+		re			=>	mii_fifo_re,
+		fifo_full	=>	mii_fifo_full,
+		fifo_empty	=>	mii_fifo_empty,
+		fifo_afull	=>	open,
+		fifo_aempty	=>	open,
+		data_w		=>  mii_fifo_din,
+		data_r		=>  mii_fifo_dout
+	);
+
+inst_piso8 : entity work.piso
+	GENERIC MAP
+	(
+		data_width_in	=> 32,
+		data_width_out	=> 8,
+		msb_first		=> true
+	)
+	PORT MAP
+	(
+		rst			=> reset_en,
+		clk			=> mii_tx_clk,
+		din_vld		=> piso8_din_vld,
+		din_rdy		=> piso8_din_rdy,
+		din_be		=> piso8_din_be,
+		din			=> piso8_din,
+		dout_vld	=> piso8_dout_vld,
+		dout_en		=> piso8_dout_en,
+		dout		=> piso8_dout
+		
+	);
+
+	piso8_dout_en	<= piso4_din_rdy and ifg_idle;
+	
+inst_piso4 : entity work.piso
+	GENERIC MAP
+	(
+		data_width_in	=> 8,
+		data_width_out	=> 4,
+		msb_first		=> false
+	)
+	PORT MAP
+	(
+		rst			=> reset_en,
+		clk			=> mii_tx_clk,
+		din_vld		=> piso8_dout_vld,
+		din_rdy		=> piso4_din_rdy,
+		din_be		=> "11",
+		din			=> piso8_dout,
+		dout_vld	=> piso4_dout_vld,
+		dout_en		=> '1',
+		dout		=> piso4_dout
+		
+	);
+
+	mii_tx_en		<= piso4_dout_vld;
+	mii_tx			<= "0000" & piso4_dout;
+
+end behavior;

lib/emac/src/emac_types.vhd

@@ -0,0 +1,62 @@
+--	Package File Template
+--
+--	Purpose: This package defines supplemental types, subtypes, 
+--		 constants, and functions 
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+use IEEE.MATH_REAL.ALL;
+
+package emac_types is
+	
+	-- Constants
+	type mac_addr_t is array (0 to 5) of unsigned (7 downto 0);
+	
+	-- Types
+	type tx_ctrl_in_t is record
+		tx_er				: std_logic;
+		tx_size				: unsigned(15 downto 0);
+		pkt_commit_en		: std_logic;
+		pkt_alloc_en		: std_logic;
+		reset				: std_logic;
+	end record;
+
+	type tx_ctrl_out_t is record
+		tx_size				: unsigned(15 downto 0);
+		pkt_done			: std_logic;
+		pkt_alloc_req		: std_logic;
+		pkt_armed			: std_logic;
+		reset_busy			: std_logic;
+	end record;
+	
+	type rx_ctrl_in_t is record
+		reset				: std_logic;
+		pkt_read_en			: std_logic;
+		pkt_req_en			: std_logic;
+		pkt_free_en			: std_logic;
+		mac_addr			: mac_addr_t;
+		promiscious			: std_logic;
+	end record;
+
+	type rx_ctrl_out_t is record
+		rx_er				: std_logic;
+		pkt_avail			: std_logic;
+		pkt_lost			: std_logic;
+		pkt_bcast			: std_logic;
+		pkt_mac_match		: std_logic;
+		rx_size				: unsigned(15 downto 0);
+		reset_busy			: std_logic;
+	end record;
+
+	-- Functions
+	
+end emac_types;
+
+
+package body emac_types is
+
+end emac_types;
+
+

lib/emac/src/piso.vhd

@@ -0,0 +1,142 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+use std.textio.all; --  Imports the standard textio package.
+
+use work.utils_pkg.all; --  Imports the standard textio package.
+
+ENTITY piso IS
+	Generic
+	(
+		data_width_in	: natural := 32;
+		data_width_out	: natural := 8;
+		msb_first		: boolean := false
+	);
+	Port
+	(
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		din_vld		: in  STD_LOGIC;
+		din_rdy		: out STD_LOGIC;
+		din_be		: in  unsigned(data_width_in/data_width_out-1 downto 0);
+		din			: in  unsigned(data_width_in-1 downto 0);
+		dout_vld	: out STD_LOGIC;
+		dout_en		: in  STD_LOGIC;
+		dout		: out unsigned(data_width_out-1 downto 0)
+		
+	);
+END piso;
+
+ARCHITECTURE behavior OF piso IS
+
+	constant num_shifts		: natural := data_width_in/data_width_out;
+	signal pre_fin			: STD_LOGIC;
+	signal rdy				: STD_LOGIC;
+	signal shift_cnt_pipe	: unsigned(num_shifts-1 downto 0);
+	signal shift_pipe		: unsigned(data_width_in-1 downto 0);
+	signal vld_pipe			: unsigned(num_shifts-1 downto 0);
+	signal din_reg			: unsigned(data_width_in-1 downto 0);
+	signal din_be_reg		: unsigned(num_shifts-1 downto 0);
+	signal din_vld_reg		: STD_LOGIC;
+	
+--------------------------------------------------------------------------
+begin
+
+	pre_fin		<= shift_cnt_pipe(shift_cnt_pipe'left-1);
+	din_rdy		<= rdy;
+	dout_vld	<= vld_pipe(vld_pipe'left) when msb_first else vld_pipe(0);
+	dout		<= 		shift_pipe(shift_pipe'left downto shift_pipe'left-data_width_out+1) when msb_first
+				else	shift_pipe(data_width_out-1 downto 0);
+
+--------------------------------------------------------------------------
+process(clk)
+begin
+	if rising_edge(clk) then
+		if rst = '1' then
+			rdy			<= '0';
+		elsif pre_fin = '1' and rdy = '0' then
+			rdy		<= '1';
+		elsif din_vld = '1' then
+			rdy			<= '0';
+		end if;
+	end if;
+end process;
+
+process(clk)
+begin
+	if rising_edge(clk) then
+		if rst = '1' then
+			din_vld_reg	<= '0';
+		elsif (pre_fin = '1' and dout_en = '1') or din_vld_reg = '0' then
+			din_vld_reg	<= din_vld;
+		end if;
+	end if;
+end process;
+
+process(clk)
+begin
+	if rising_edge(clk) then
+		if din_vld = '1' and rdy = '1' then
+			din_reg		<= din;
+			din_be_reg	<= din_be;
+		end if;
+	end if;
+end process;
+
+process(clk)
+begin
+	if rising_edge(clk) then
+		if rst = '1' then
+			shift_cnt_pipe	<= (others => '1');
+		elsif (din_vld = '1' and din_vld_reg = '0') then
+			shift_cnt_pipe	<= (others => '0');
+		elsif dout_en = '1' then
+			if (pre_fin = '1' and din_vld_reg = '1') then
+				shift_cnt_pipe	<= (others => '0');
+			else
+				shift_cnt_pipe	<= shift_cnt_pipe(shift_cnt_pipe'left-1 downto 0)  & '1';
+			end if;
+		end if;
+	end if;
+end process;
+
+--------------------------------------------------------------------------
+process(clk)
+begin
+	if rising_edge(clk) then
+		if dout_en = '1' then
+			if pre_fin = '1' and din_vld_reg = '1' then
+				shift_pipe		<= din_reg;
+			else	
+				if (msb_first) then
+					shift_pipe		<= shift_pipe(shift_pipe'left-data_width_out downto 0) & (data_width_out-1 downto 0 => '0');
+				else
+					shift_pipe		<= (data_width_out-1 downto 0 => '0') & shift_pipe(shift_pipe'left downto data_width_out);
+				end if;
+			end if;
+		end if;
+	end if;
+end process;
+
+--------------------------------------------------------------------------
+process(clk)
+begin
+	if rising_edge(clk) then
+		if rst = '1' then
+			vld_pipe	<= (others => '0');
+		elsif dout_en = '1' then
+			if pre_fin = '1' and din_vld_reg = '1' then
+				vld_pipe		<= din_be_reg;
+			else
+				if (msb_first) then
+					vld_pipe		<= vld_pipe(vld_pipe'left-1 downto 0) & '0';
+				else
+					vld_pipe		<= '0' & vld_pipe(vld_pipe'left downto 1);
+				end if;
+			end if;
+		end if;
+	end if;
+end process;
+
+--------------------------------------------------------------------------
+end behavior;

lib/emac/src/pkt_gen.vhd

@@ -0,0 +1,442 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE IEEE.MATH_REAL.ALL;
+use std.textio.all; --  Imports the standard textio package.
+
+use work.emac_types.all;
+use work.utils_pkg.all;
+
+ENTITY pkt_gen IS
+	Generic
+	(
+		f_sysclk		: real		:= 100.0;
+		PKT_DLY_MIN		: real		:= 1.0E-6;
+		PKT_DLY_MAX		: real		:= 100.0E-6;
+		PKT_SIZE_MIN	: natural	:= 64;
+		PKT_SIZE_MAX	: natural	:= 1518
+		
+	);
+	Port
+	(
+		clk				: in  STD_LOGIC;
+		rst				: in  STD_LOGIC;
+		mii_tx_clk		: in  STD_LOGIC;
+		mii_tx_en		: out STD_LOGIC;
+		mii_tx_er		: out STD_LOGIC;
+		mii_tx			: out unsigned(7 downto 0)
+		
+	);
+END pkt_gen;
+
+ARCHITECTURE behavior OF pkt_gen IS
+
+	subtype word_ptr_t is unsigned(15 downto 0);
+
+	signal pkt_data			: unsigned(31 downto 0);
+	signal pkt_nbytes		: word_ptr_t := X"0040";
+	signal pkt_nwords		: word_ptr_t := X"0010";
+	signal pkt_delay		: natural := natural(1.0*f_sysclk);
+	
+	signal tx_packets		: natural;
+	signal tx_bytes			: natural;
+	
+	signal mii_fifo_din		: unsigned(35 downto 0);
+	signal mii_fifo_dout	: unsigned(35 downto 0);
+	signal mii_fifo_we		: std_logic;
+	signal mii_fifo_re		: std_logic;
+	signal mii_fifo_empty	: std_logic;
+	signal mii_fifo_full	: std_logic;
+
+	signal xfer_size		: word_ptr_t;
+	signal xfer_ptr			: word_ptr_t;
+	signal xfer_cnt			: word_ptr_t;
+	signal xfer_set			: std_logic;
+	signal xfer_en			: std_logic;
+	signal xfer_sync		: unsigned(1 downto 0);
+	signal xfer_cnt_en		: std_logic;
+	signal xfer_bsy			: std_logic;
+	signal xfer_pre_rdy		: std_logic;
+	signal uncommit_en		: std_logic;
+
+	signal piso8_din			: unsigned(31 downto 0);
+	signal piso8_din_be		: unsigned(3 downto 0);
+	signal piso8_din_rdy		: std_logic;
+	signal piso8_din_vld			: std_logic;
+
+	signal piso8_dout			: unsigned(7 downto 0);
+	signal piso8_dout_vld		: std_logic;
+	signal piso8_dout_en		: std_logic;
+	signal piso4_din_rdy		: std_logic;
+	signal tx_en				: std_logic;
+	
+	subtype ifg_cnt_t is natural range 0 to 23;		-- 10/100 mbps
+--	subtype ifg_cnt_t is natural range 0 to 11;		-- 1000 mbps
+
+	signal ifg_cnt			: ifg_cnt_t;
+	signal ifg_idle			: std_logic;
+	
+	type xfer_state_t is (xfer_init, xfer_idle, xfer_setup, xfer_arm, xfer_active, xfer_uncommit, xfer_free);
+	signal xfer_s, xfer_sn : xfer_state_t;
+
+	type stream_state_t is (stream_init, stream_idle, stream_start, stream_preamble0, stream_preamble1, stream_active, stream_crc, stream_stop, stream_finish);
+	signal stream_s, stream_sn : stream_state_t;
+
+	type piso_byte_mask_array_t is array (0 to 3) of unsigned (3 downto 0);
+	constant piso_byte_mask_rom : piso_byte_mask_array_t :=
+	(
+		"1111",
+		"1000",
+		"1100",
+		"1110"
+	);
+	
+	signal preamble_en		: std_logic;
+	signal preamble_addr	: natural range 0 to 1;
+	type preamble_t is array (0 to 1) of unsigned(31 downto 0);
+	constant preamble : preamble_t :=
+	(
+		X"55555555",
+		X"555555D5"
+	);
+	
+begin
+
+	mii_tx_er				<= '0';
+
+	piso8_din				<= preamble(preamble_addr) when preamble_en = '1' else mii_fifo_dout(31 downto 0);
+	piso8_din_be			<= "1111" when preamble_en = '1' else mii_fifo_dout(35 downto 32);
+
+	mii_fifo_we				<= xfer_bsy;
+	xfer_cnt_en				<= xfer_bsy and not mii_fifo_full;
+
+	mii_fifo_din(35 downto 32)	<= piso_byte_mask_rom(to_integer(pkt_nbytes(1 downto 0))) when xfer_pre_rdy = '1' else "1111";
+	mii_fifo_din(31 downto 0)	<= pkt_data;
+
+	
+------------------------------------------------------------------
+-- Transfer stuff
+------------------------------------------------------------------
+xfer_state_next:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				xfer_s	<= xfer_init;
+			else
+				xfer_s	<= xfer_sn;
+			end if;
+		end if;
+	end process;	
+
+xfer_state:
+	process(xfer_s, xfer_bsy, xfer_sync)
+	begin
+	
+		uncommit_en			<= '0';
+		xfer_set			<= '0';
+		xfer_en				<= '0';
+		
+		xfer_sn				<= xfer_s;
+		
+		case xfer_s is
+		
+		when xfer_init =>
+			xfer_sn <= xfer_idle;
+		
+		when xfer_idle =>
+			xfer_sn			<= xfer_setup;
+			
+		when xfer_setup =>
+			xfer_set			<= '1';
+			xfer_sn				<= xfer_arm;
+
+		when xfer_arm =>
+			xfer_en				<= '1';
+			xfer_sn				<= xfer_active;
+
+		when xfer_active =>
+			xfer_en				<= '1';
+			if xfer_bsy = '0' then
+				xfer_sn			<= xfer_uncommit;
+			end if;	
+
+		when xfer_uncommit =>
+			uncommit_en		<= '1';
+			xfer_sn			<= xfer_free;
+
+		when xfer_free =>
+			if xfer_sync(1) = '1' then
+				xfer_sn			<= xfer_idle;
+			end if;
+
+		when others => 
+			xfer_sn				<= xfer_idle;
+		end case;
+
+	end process;
+
+------------------------------------------------------------------
+interframe_gap_ready:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			xfer_sync(1)	<= xfer_sync(0);
+			xfer_sync(0)	<= mii_fifo_empty;
+		end if;
+	end process;
+
+------------------------------------------------------------------
+interframe_gap_counter:
+	process(mii_tx_clk)
+	begin
+		if rising_edge(mii_tx_clk) then
+			ifg_idle	<= '0';
+			if rst = '1' or piso8_dout_vld = '1' then
+				ifg_cnt 	<= ifg_cnt_t'high;
+				ifg_idle	<= '1';
+			elsif ifg_cnt /= 0 then
+				ifg_cnt		<= ifg_cnt - 1;
+			else
+				ifg_idle	<= '1';
+			end if;
+		end if;
+	end process;
+
+------------------------------------------------------------------
+pkt_params:
+	process(clk)
+	variable size		: word_ptr_t;
+	variable delay		: natural;
+	variable krand		: real;
+	variable seed1		: integer;
+	variable seed2		: integer;
+	
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				size		:= to_unsigned(PKT_SIZE_MIN, word_ptr_t'length);
+				delay 		:= natural(1.0E6*PKT_DLY_MIN*f_sysclk);
+				seed1		:= 31101970;
+				seed2		:= 12586901;
+				tx_packets	<= 0;
+				tx_bytes	<= 0;
+			elsif uncommit_en = '1' then
+				uniform(seed1, seed2, krand);
+				size		:= to_unsigned(PKT_SIZE_MIN + natural(real(PKT_SIZE_MAX-PKT_SIZE_MIN)*krand), word_ptr_t'length);
+				delay 		:= natural(1.0E6*f_sysclk*(PKT_DLY_MIN + (PKT_DLY_MAX-PKT_DLY_MIN)*krand));
+				tx_packets	<= tx_packets + 1;
+				tx_bytes	<= tx_bytes + to_integer(pkt_nbytes);
+			end if;
+			pkt_delay	<= delay;
+			pkt_nbytes	<= size;
+			if size(1 downto 0) = 0 then
+				pkt_nwords	<= "00" & size(word_ptr_t'left downto 2);
+			else	
+				pkt_nwords	<= "00" & size(word_ptr_t'left downto 2) + 1;
+			end if;
+		end if;
+	end process;
+
+------------------------------------------------------------------
+xfer_counter:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if xfer_set = '1' then
+				xfer_cnt 		<= pkt_nwords;
+				xfer_size		<= (others => '0');
+				xfer_bsy		<= '0';
+				xfer_pre_rdy	<= '0';
+			elsif xfer_en = '1' then
+				xfer_bsy		<= '1';
+				if xfer_cnt_en = '1' or xfer_bsy = '0' then
+					if xfer_cnt /= 1 then
+						xfer_cnt		<= xfer_cnt - 1;
+						xfer_size		<= xfer_size + 1;
+					else
+						xfer_pre_rdy	<= '1';
+					end if;
+					if xfer_pre_rdy = '1' then
+						xfer_bsy	<= '0';
+					end if;
+				end if;
+			end if;
+		end if;	
+			
+	end process;	
+	
+------------------------------------------------------------------
+pkt_data_gen:
+	process(clk)
+	variable data : unsigned(7 downto 0);
+	begin
+		if rising_edge(clk) then
+			if xfer_set = '1' then
+				data	:= (others => '0');
+			elsif xfer_cnt_en = '1' or xfer_bsy = '0' then
+				pkt_data(7 downto 0)	<= data;
+				data					:= data + 1;
+				pkt_data(15 downto 8)	<= data;
+				data					:= data + 1;
+				pkt_data(23 downto 16)	<= data;
+				data					:= data + 1;
+				pkt_data(31 downto 24)	<= data;
+				data					:= data + 1;
+			end if;
+		end if;	
+			
+	end process;	
+
+------------------------------------------------------------------
+stream_state_next:
+	process(mii_tx_clk)
+	begin
+		if rising_edge(mii_tx_clk) then
+			if rst = '1' then
+				stream_s	<= stream_init;
+			else
+				stream_s	<= stream_sn;
+			end if;
+		end if;
+	end process;	
+
+stream_state:
+	process(stream_s, ifg_idle, mii_fifo_empty, piso8_din_rdy, piso8_dout_vld)
+	begin
+		
+		piso8_din_vld		<= '0';
+		mii_fifo_re			<= '0';
+		preamble_en			<= '0';
+		preamble_addr		<= 0;
+		
+		stream_sn			<= stream_s;
+		
+		case stream_s is
+		
+		when stream_init =>
+			if mii_fifo_empty = '1' then
+				stream_sn 		<= stream_idle;
+			end if;
+			
+		when stream_idle =>
+			if mii_fifo_empty = '0' and piso8_din_rdy = '1' then
+				stream_sn 		<= stream_start;
+			end if;
+			
+		when stream_start =>
+			stream_sn 		<= stream_preamble0;
+
+		when stream_preamble0 =>
+			preamble_addr	<= 0;
+			preamble_en		<= '1';
+			piso8_din_vld	<= '1';
+			if piso8_din_rdy = '1' then
+				stream_sn 		<= stream_preamble1;
+			end if;
+
+		when stream_preamble1 =>
+			preamble_addr	<= 1;
+			preamble_en		<= '1';
+			piso8_din_vld	<= '1';
+			if piso8_din_rdy = '1' then
+				stream_sn 		<= stream_active;
+			end if;
+
+		when stream_active =>
+			piso8_din_vld	<= not mii_fifo_empty;
+			mii_fifo_re		<= piso8_din_rdy;
+			if mii_fifo_empty = '1' then
+				stream_sn 		<= stream_crc;
+			end if;
+
+		when stream_crc =>
+			stream_sn 		<= stream_stop;
+			
+		when stream_stop =>
+			if piso8_dout_vld = '0' then
+				stream_sn 		<= stream_finish;
+			end if;
+
+		when stream_finish =>
+			if ifg_idle = '0' then
+				stream_sn		<= stream_idle;
+			end if;
+
+		when others => 
+			stream_sn		<= stream_idle;
+		end case;
+
+	end process;
+
+------------------------------------------------------------------
+-- Instantiate synchronous FIFO
+inst_mii_fifo: entity work.fifo_async
+	GENERIC MAP
+	(
+		addr_width			=> 4,
+		data_width			=> mii_fifo_din'length,
+		do_last_read_update	=> true
+	)
+	PORT MAP
+	(
+		rst			=>	rst,
+		clk_w		=>	clk,
+		clk_r		=>	mii_tx_clk,
+		we			=>	mii_fifo_we,
+		re			=>	mii_fifo_re,
+		fifo_full	=>	mii_fifo_full,
+		fifo_empty	=>	mii_fifo_empty,
+		fifo_afull	=>	open,
+		fifo_aempty	=>	open,
+		data_w		=>  mii_fifo_din,
+		data_r		=>  mii_fifo_dout
+	);
+
+inst_piso : entity work.piso
+	GENERIC MAP
+	(
+		data_width_in	=> 32,
+		data_width_out	=> 8,
+		msb_first		=> true
+	)
+	PORT MAP
+	(
+		rst			=> rst,
+		clk			=> mii_tx_clk,
+		din_vld		=> piso8_din_vld,
+		din_rdy		=> piso8_din_rdy,
+		din_be		=> piso8_din_be,
+		din			=> piso8_din,
+		dout_vld	=> piso8_dout_vld,
+		dout_en		=> piso8_dout_en,
+		dout		=> piso8_dout
+		
+	);
+
+	piso8_dout_en	<= piso4_din_rdy and ifg_idle;
+
+inst_piso_10mbps : entity work.piso
+	GENERIC MAP
+	(
+		data_width_in	=> 8,
+		data_width_out	=> 4,
+		msb_first		=> false
+	)
+	PORT MAP
+	(
+		rst			=> rst,
+		clk			=> mii_tx_clk,
+		din_vld		=> piso8_dout_vld,
+		din_rdy		=> piso4_din_rdy,
+		din_be		=> "11",
+		din			=> piso8_dout,
+		dout_vld	=> tx_en,
+		dout_en		=> '1',
+		dout		=> mii_tx(3 downto 0)
+		
+	);
+	mii_tx_en			<= tx_en;
+	mii_tx(7 downto 4)	<= "0000";
+
+end behavior;

lib/emac/src/shifter.vhd

@@ -0,0 +1,111 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+use std.textio.all; --  Imports the standard textio package.
+
+use work.utils_pkg.all; --  Imports the standard textio package.
+
+ENTITY shifter IS
+	Generic
+	(
+		data_width		: natural := 32;
+		aggregate_size	: natural := 8;
+		do_pipelined	: boolean := true
+	);
+	Port
+	(
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		sa			: in  integer;
+		din_vld		: in  STD_LOGIC;
+		din			: in  unsigned(data_width-1 downto 0);
+		dout_vld	: out STD_LOGIC;
+		dout		: out unsigned(data_width-1 downto 0)
+		
+	);
+END shifter;
+
+ARCHITECTURE behavior OF shifter IS
+
+	constant num_rounds	: natural := NextExpBaseTwo(data_width/aggregate_size);
+	subtype sa_rnd_t is signed(num_rounds-1 downto 0);
+	subtype word_t is unsigned(data_width-1 downto 0);
+	type word_array_t is array (0 to num_rounds) of word_t;
+
+	signal rot_data			: word_array_t;
+	signal sa_rnd			: sa_rnd_t;
+
+	type sa_rnd_array_t is array (0 to num_rounds) of sa_rnd_t;
+	signal sa_rnd_pipe		: sa_rnd_array_t;
+	signal dout_vld_pipe	: unsigned(0 to num_rounds);
+	
+--------------------------------------------------------------------------
+function rol_stage(x : unsigned; en : std_logic; stage_num : natural; size : natural) return unsigned is
+	variable result : unsigned(x'range);
+	constant sa : natural := (2**stage_num) * size;
+	begin
+	if en = '1' then
+		result := x(x'left-sa downto 0) & x(x'left downto x'length-sa);
+	else
+		result := x;
+	end if;	
+	return result;
+end rol_stage;
+
+--------------------------------------------------------------------------
+begin
+
+--------------------------------------------------------------------------
+gen_non_pipelined:
+if do_pipelined = false generate
+begin
+	
+	rot_data(0)		<= din;
+	
+gen_rotate_right:
+	for stage in 0 to num_rounds-1 generate
+	begin
+		rot_data(stage+1) <= rol_stage(rot_data(stage), sa_rnd(stage), stage, aggregate_size);
+	end generate;
+	
+	sa_rnd			<= to_signed(sa, num_rounds);
+	dout			<= rot_data(num_rounds);
+	dout_vld		<= din_vld;
+	
+end generate;
+	
+--------------------------------------------------------------------------
+gen_pipelined:
+if do_pipelined = true generate
+begin
+	
+	rot_data(0)			<= din;
+	sa_rnd_pipe(0)		<= to_signed(sa, num_rounds);
+	dout_vld_pipe(0)	<= din_vld;
+	
+gen_rotate_right:
+	for stage in 0 to num_rounds-1 generate
+	begin
+		process(clk)
+		begin
+			if rising_edge(clk) then
+				if rst = '1' then
+					dout_vld_pipe(stage+1)	<= '0';
+				else
+					dout_vld_pipe(stage+1)	<= dout_vld_pipe(stage);
+					if dout_vld_pipe(stage) = '1' then
+						sa_rnd_pipe(stage+1)	<= sa_rnd_pipe(stage);
+						rot_data(stage+1)		<= rol_stage(rot_data(stage), sa_rnd_pipe(stage)(stage), stage, aggregate_size);
+					end if;
+				end if;
+			end if;
+		end process;
+	end generate;
+	
+	dout			<= rot_data(num_rounds);
+	dout_vld		<= dout_vld_pipe(num_rounds);
+	
+end generate;
+
+--------------------------------------------------------------------------
+end behavior;

lib/emac/src/sipo.vhd

@@ -0,0 +1,118 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+use std.textio.all; --  Imports the standard textio package.
+
+use work.utils_pkg.all; --  Imports the standard textio package.
+
+ENTITY sipo IS
+	Generic
+	(
+		data_width_in	: natural := 8;
+		data_width_out	: natural := 32;
+		msb_first		: boolean := false
+	);
+	Port
+	(
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		din_en		: in  STD_LOGIC;
+		din_vld		: in  STD_LOGIC;
+		din			: in  unsigned(data_width_in-1 downto 0);
+		dout_en		: out STD_LOGIC;
+		dout_vld	: out STD_LOGIC;
+		dout		: out unsigned(data_width_out-1 downto 0);
+		dout_be		: out unsigned(data_width_out/data_width_in-1 downto 0)
+		
+	);
+END sipo;
+
+ARCHITECTURE behavior OF sipo IS
+
+	constant num_shifts		: natural := data_width_out/data_width_in;
+	signal pre_fin			: STD_LOGIC;
+	signal shift_cnt_pipe	: unsigned(num_shifts-1 downto 0);
+	signal shift_pipe		: unsigned(data_width_out-1 downto 0);
+	signal out_en			: STD_LOGIC;
+	signal out_vld			: STD_LOGIC;
+	signal din_vld_r		: STD_LOGIC;
+	signal abort			: STD_LOGIC;
+	
+--------------------------------------------------------------------------
+begin
+
+	pre_fin		<= shift_cnt_pipe(shift_cnt_pipe'left) when msb_first else shift_cnt_pipe(0);
+	dout_en		<= out_en;
+	dout_vld	<= out_vld;
+	
+--------------------------------------------------------------------------
+process(clk)
+begin
+	if rising_edge(clk) then
+		if rst = '1' or pre_fin = '1' then
+			abort <= '0';
+		elsif din_vld_r = '1' and din_en = '0' then	
+			abort <= '1';
+		end if;
+	end if;
+end process;
+
+process(clk)
+begin
+	if rising_edge(clk) then
+		din_vld_r	<= din_vld;
+		if rst = '1' then
+			out_en <= '0';
+		elsif out_en = '0' then	
+			out_en		<= pre_fin and din_en;
+		elsif out_vld = '1' then
+			out_en		<= din_en;
+		end if;
+	end if;
+end process;
+
+process(clk)
+begin
+	if rising_edge(clk) then
+		out_vld	<= pre_fin;
+		if pre_fin = '1' then
+			dout		<= shift_pipe;
+			dout_be		<= shift_cnt_pipe;
+		end if;
+	end if;
+end process;
+
+process(clk)
+begin
+	if rising_edge(clk) then
+		if rst = '1' or pre_fin = '1' then
+			if (msb_first) then
+				shift_cnt_pipe	<= (shift_cnt_pipe'left downto 1 => '0') & din_vld;
+			else
+				shift_cnt_pipe	<= din_vld & (shift_cnt_pipe'left downto 1 => '0');
+			end if;
+		elsif din_vld = '1' or abort = '1' then
+			if (msb_first) then
+				shift_cnt_pipe	<= shift_cnt_pipe(shift_cnt_pipe'left-1 downto 0)  & din_vld;
+			else
+				shift_cnt_pipe	<= din_vld & shift_cnt_pipe(shift_cnt_pipe'left downto 1);
+			end if;
+		end if;
+	end if;
+end process;
+
+process(clk)
+begin
+	if rising_edge(clk) then
+		if din_vld = '1' or abort = '1' then
+			if (msb_first) then
+				shift_pipe		<= shift_pipe(shift_pipe'left-data_width_in downto 0) & din;
+			else
+				shift_pipe		<= din & shift_pipe(shift_pipe'left downto data_width_in);
+			end if;
+		end if;
+	end if;
+end process;
+
+--------------------------------------------------------------------------
+end behavior;

lib/emac/src/tb_emac_jb.vhd

@@ -0,0 +1,428 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: testbench for system test using Xilinx ML-402
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY tb_emac_jb IS
+END tb_emac_jb;
+
+ARCHITECTURE behavior OF tb_emac_jb IS 
+
+	constant CLK_PERIOD		: time := 10 ns;
+	constant MII_CLK_PERIOD	: time := 8 ns;
+
+	signal CLK				: std_logic := '1';
+	signal RST				: std_logic := '1';
+
+	-- Slave
+	signal CYC_I			: std_logic := '0';
+	signal STB_I			: std_logic := '0';
+	signal WE_I				: std_logic := '0';
+	signal SEL_I			: unsigned(3 downto 0);
+	signal ACK_O			: std_logic;
+	signal INT_O			: std_logic;
+	signal MRDY_I			: std_logic;
+	signal SRDY_O			: std_logic;
+	signal ADDR_I			: unsigned(31 downto 0) := (others => '-');
+	signal DAT_I			: unsigned(31 downto 0) := (others => '-');
+	signal DAT_O			: unsigned(31 downto 0) := (others => '-');
+	signal DAT_O_reg		: unsigned(31 downto 0) := (others => '-');
+
+	-- MII signals
+	signal mii_rx_clk_board	: std_logic := '1';
+	signal mii_tx_clk_board	: std_logic := '1';
+	signal mii_rx_clk		: std_logic := '1';
+	signal mii_tx_clk		: std_logic := '1';
+	signal mii_rx			: unsigned(7 downto 0) := (others => '-');
+	signal mii_tx			: unsigned(7 downto 0);
+	signal mii_rx_dv		: std_logic := '0';
+	signal mii_rx_er		: std_logic := '0';
+	signal mii_tx_en		: std_logic;
+	signal mii_tx_er		: std_logic;
+	signal mii_crs			: std_logic := '0';
+	signal mii_col			: std_logic := '0';
+	signal mii_gtx_clk		: std_logic;
+
+	signal shift_sa			: integer := 0;
+	signal shift_din_vld	: std_logic := '0';
+	signal shift_din		: unsigned(31 downto 0) := (others => '-');
+	signal shift_dout_vld	: std_logic;
+	signal shift_dout		: unsigned(31 downto 0);
+
+	signal piso_din_vld		: std_logic := '0';
+	signal piso_din_rdy		: std_logic;
+	signal piso_din_be		: unsigned(7 downto 0) := (others => '0');
+	signal piso_din			: unsigned(31 downto 0) := (others => '-');
+	signal piso_dout_en		: std_logic;
+	signal piso_dout		: unsigned(3 downto 0);
+
+	signal sipo_enable		: std_logic := '0';
+	signal sipo_din_en		: std_logic := '0';
+	signal sipo_din			: unsigned(3 downto 0) := (others => '-');
+	signal sipo_dout_vld	: std_logic;
+	signal sipo_dout_be		: unsigned(7 downto 0);
+	signal sipo_dout		: unsigned(31 downto 0);
+
+	type emac_action_t is (emac_idle, emac_alloc, emac_write, emac_read);
+	signal emac_action	: emac_action_t;
+	
+BEGIN
+
+inst_emac_jb : entity work.emac_jb
+	GENERIC MAP
+	(
+		f_sysclk	=> 100.0,
+		TX_RAM_SIZE	=> 2048
+	)
+	PORT MAP
+	(
+		CLK_I		=> CLK,
+		RST_I		=> RST,
+		INT_O		=> INT_O,
+		CYC_I		=> CYC_I,
+		STB_I		=> STB_I,
+		SEL_I		=> SEL_I,
+		WE_I		=> WE_I,
+		ACK_O		=> ACK_O,
+		SRDY_O		=> SRDY_O,
+		MRDY_I		=> MRDY_I,
+		ADDR_I		=> ADDR_I,
+		DAT_I		=> DAT_I,
+		DAT_O		=> DAT_O,
+		mii_rx_clk	=> mii_rx_clk_board,
+		mii_rx_dv	=> mii_rx_dv,
+		mii_rx_er	=> mii_rx_er,
+		mii_rx		=> mii_rx,
+		mii_tx_clk	=> mii_tx_clk_board,
+		mii_tx_en	=> mii_tx_en,
+		mii_tx_er	=> mii_tx_er,
+		mii_tx		=> mii_tx,
+		mii_gtx_clk	=> mii_gtx_clk,
+		mii_crs		=> mii_crs,
+		mii_col		=> mii_col
+		
+	);
+
+inst_shifter : entity work.shifter
+	GENERIC MAP
+	(
+		data_width		=> 32,
+		aggregate_size	=> 4,
+		do_pipelined	=> true
+	)
+	PORT MAP
+	(
+		rst			=> RST,
+		clk			=> CLK,
+		sa			=> shift_sa,
+		din_vld		=> shift_din_vld,
+		din			=> shift_din,
+		dout_vld	=> shift_dout_vld,
+		dout		=> shift_dout
+		
+	);
+
+inst_piso : entity work.piso
+	GENERIC MAP
+	(
+		data_width_in	=> 32,
+		data_width_out	=> 4,
+		msb_first		=> true
+	)
+	PORT MAP
+	(
+		rst			=> RST,
+		clk			=> CLK,
+		din_vld		=> piso_din_vld,
+		din_rdy		=> piso_din_rdy,
+		din_be		=> piso_din_be,
+		din			=> piso_din,
+		dout_en		=> piso_dout_en,
+		dout		=> piso_dout
+		
+	);
+
+inst_sipo : entity work.sipo
+	GENERIC MAP
+	(
+		data_width_in	=> 4,
+		data_width_out	=> 32,
+		msb_first		=> true
+	)
+	PORT MAP
+	(
+		rst			=> RST,
+		clk			=> CLK,
+		enable		=> sipo_enable,
+		din_en		=> sipo_din_en,
+		din			=> sipo_din,
+		dout_be		=> sipo_dout_be,
+		dout_vld	=> sipo_dout_vld,
+		dout		=> sipo_dout
+		
+	);
+	sipo_din		<= piso_dout;
+	sipo_din_en		<= piso_dout_en;
+
+CLK_GEN: process
+	begin
+		wait for CLK_PERIOD/2;
+		CLK <= not CLK;
+	end process;
+
+MII_CLK_GEN: process
+	begin
+		wait for MII_CLK_PERIOD/2;
+		mii_rx_clk <= not mii_rx_clk;
+		mii_tx_clk <= not mii_tx_clk;
+	end process;
+
+	mii_rx_clk_board <= mii_rx_clk;
+	mii_tx_clk_board <= mii_tx_clk;
+
+DAT_O_register:
+	process(CLK)
+	begin
+		if rising_edge(CLK) then
+			if ACK_O = '1' then
+				DAT_O_reg	<= DAT_O;
+			end if;
+		end if;
+	end process;
+	
+
+-- Master
+STIMULUS: process
+
+	procedure emac_alloc (size : natural) is
+	begin
+	
+		-- TX-ALLOCATION
+		-- set TX-size
+		emac_action	<= emac_alloc;
+		CYC_I	<= '1';
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		DAT_I	<= to_unsigned(size, 16) & X"55AA";
+		STB_I	<= '1';
+		WE_I	<= '1';
+		ADDR_I	<= X"0000_0004";
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		STB_I	<= '0';
+
+		-- set alloc request
+		CYC_I	<= '1';
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		DAT_I	<= X"0001_0000";
+		STB_I	<= '1';
+		WE_I	<= '1';
+		ADDR_I	<= X"0000_0000";
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		STB_I	<= '0';
+
+		WE_I	<= '0';
+
+		-- check alloc busy
+	check_bsy:
+		while (true) loop
+			CYC_I	<= '1';
+			wait until rising_edge(CLK) and SRDY_O = '1';
+			STB_I	<= '1';
+			ADDR_I	<= X"0000_0000";
+			wait until rising_edge(CLK) and SRDY_O = '1';
+			STB_I	<= '0';
+			wait until rising_edge(CLK) and ACK_O = '1';
+			wait until rising_edge(CLK);
+			if DAT_O_reg(16) = '0' then
+				exit check_bsy;
+			end if;
+		end loop;
+		emac_action	<= emac_idle;
+
+	end procedure emac_alloc;
+	
+	procedure emac_write (size : natural) is
+	variable data : unsigned (7 downto 0);
+	variable num_words : natural;
+	begin
+
+		-- FILL TX data
+		emac_action	<= emac_write;
+		if (size mod 4) = 0 then
+			num_words	:= size/4;
+		else
+			num_words	:= size/4 + 1;
+		end if;
+		
+		CYC_I	<= '1';
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		data	:= X"00";
+		ADDR_I	<= X"0000_0008";
+		WE_I	<= '1';
+		for i in 1 to num_words loop
+			STB_I	<= '1';
+			DAT_I(7 downto 0)	<= data;
+			data				:= data + 1;
+			DAT_I(15 downto 8)	<= data;
+			data				:= data + 1;
+			DAT_I(23 downto 16)	<= data;
+			data				:= data + 1;
+			DAT_I(31 downto 24)	<= data;
+			data				:= data + 1;
+			wait until rising_edge(CLK) and SRDY_O = '1';
+		end loop;
+
+		STB_I	<= '0';
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		emac_action	<= emac_idle;
+
+	end procedure emac_write;
+
+	begin
+
+		wait for 6*MII_CLK_PERIOD;
+		RST <= '0';
+		wait for 60*CLK_PERIOD;
+
+ 		emac_alloc (1536);
+ 		emac_write (1536);
+ 
+ 		emac_alloc (1536);
+ 		emac_write (1536);
+
+ 		emac_alloc (1536);
+ 		emac_write (1536);
+
+ 		emac_alloc (1536);
+ 		emac_write (1536);
+
+ 		emac_alloc (1536);
+ 		emac_write (1536);
+
+ 		emac_alloc (1536);
+ 		emac_write (1536);
+
+ 		emac_alloc (1536);
+ 		emac_write (1536);
+
+		emac_alloc (64);
+		emac_write (64);
+
+		emac_alloc (512);
+		emac_write (512);
+
+		emac_alloc (1536);
+		emac_write (1536);
+
+		emac_alloc (65);
+		emac_write (65);
+
+		emac_alloc (66);
+		emac_write (66);
+
+		emac_alloc (67);
+		emac_write (67);
+
+		emac_alloc (512);
+		emac_write (512);
+
+		wait for 4000*CLK_PERIOD;
+		
+		wait until rising_edge(CLK);
+		shift_din		<= X"12345678";
+		shift_sa		<= 0;
+		shift_din_vld	<= '1';
+		wait until rising_edge(CLK);
+		shift_sa		<= shift_sa + 1;
+		wait until rising_edge(CLK);
+		shift_sa		<= shift_sa + 1;
+		wait until rising_edge(CLK);
+		shift_sa		<= shift_sa + 1;
+		wait until rising_edge(CLK);
+		shift_sa		<= shift_sa + 1;
+		wait until rising_edge(CLK);
+		shift_sa		<= shift_sa + 1;
+		wait until rising_edge(CLK);
+		shift_sa		<= shift_sa + 1;
+		wait until rising_edge(CLK);
+		shift_sa		<= shift_sa + 1;
+		wait until rising_edge(CLK);
+
+		shift_sa		<= 0;
+		wait until rising_edge(CLK);
+		shift_sa		<= shift_sa - 1;
+		wait until rising_edge(CLK);
+		shift_sa		<= shift_sa - 1;
+		wait until rising_edge(CLK);
+		shift_sa		<= shift_sa - 1;
+		wait until rising_edge(CLK);
+		shift_sa		<= shift_sa - 1;
+		wait until rising_edge(CLK);
+		shift_sa		<= shift_sa - 1;
+		wait until rising_edge(CLK);
+		shift_sa		<= shift_sa - 1;
+		wait until rising_edge(CLK);
+		shift_sa		<= shift_sa - 1;
+
+		wait until rising_edge(CLK);
+		shift_din_vld	<= '0';
+
+		
+		for i in 1 to 10 loop
+
+			wait until rising_edge(CLK);
+			sipo_enable		<= '1';
+			piso_din_vld	<= '1';
+			piso_din		<= X"12345678";
+			piso_din_be		<= "11111111";
+			wait until rising_edge(CLK) and piso_din_rdy = '1';
+			piso_din		<= piso_din + X"12345678";
+			piso_din_be		<= "11100111";
+			wait until rising_edge(CLK) and piso_din_rdy = '1';
+			piso_din		<= piso_din + X"12345678";
+			piso_din_be		<= "11111100";
+			wait until rising_edge(CLK) and piso_din_rdy = '1';
+			piso_din		<= piso_din + X"12345678";
+			piso_din_be		<= "00111111";
+			wait until rising_edge(CLK) and piso_din_rdy = '1';
+			piso_din		<= (others => '-');
+			piso_din_vld	<= '0';
+
+
+			wait until rising_edge(CLK) and sipo_dout_vld = '1';
+			wait until rising_edge(CLK);
+			wait until rising_edge(CLK) and sipo_dout_vld = '1';
+
+			sipo_enable		<= '0';
+
+			wait for 33*CLK_PERIOD;
+		
+		end loop;
+		
+		wait; 
+	
+	end process;
+	
+END;

lib/emac/src/tb_emac_top_jb.vhd

@@ -0,0 +1,546 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: testbench for system test using Xilinx ML-402
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY tb_emac_top_jb IS
+END tb_emac_top_jb;
+
+ARCHITECTURE behavior OF tb_emac_top_jb IS 
+
+	constant CLK_PERIOD		: time := 10 ns;
+	constant MII_CLK_PERIOD	: time := 40.7 ns;
+
+	signal CLK				: std_logic := '1';
+	signal RST				: std_logic := '1';
+
+	-- Slave
+	signal CYC_I			: std_logic := '0';
+	signal STB_I			: std_logic := '0';
+	signal WE_I				: std_logic := '0';
+	signal SEL_I			: unsigned(3 downto 0) := (others => '1');
+	signal ACK_O			: std_logic;
+	signal INT_O			: std_logic;
+	signal MRDY_I			: std_logic := '0';
+	signal SRDY_O			: std_logic;
+	signal ADDR_I			: unsigned(31 downto 0) := (others => '-');
+	signal DAT_I			: unsigned(31 downto 0) := (others => '-');
+	signal DAT_O			: unsigned(31 downto 0) := (others => '-');
+	signal DAT_O_reg		: unsigned(31 downto 0) := (others => '-');
+
+	-- MII signals
+	signal mii_rx_clk_board	: std_logic := '1';
+	signal mii_tx_clk_board	: std_logic := '1';
+	signal mii_rx_clk		: std_logic := '1';
+	signal mii_tx_clk		: std_logic := '1';
+	signal mii_rx			: unsigned(7 downto 0) := (others => '-');
+	signal mii_tx			: unsigned(7 downto 0);
+	signal mii_rx_dv		: std_logic := '0';
+	signal mii_rx_er		: std_logic := '0';
+	signal mii_tx_en		: std_logic;
+	signal mii_tx_er		: std_logic;
+	signal mii_crs			: std_logic := '0';
+	signal mii_col			: std_logic := '0';
+	signal mii_gtx_clk		: std_logic;
+
+	signal loop_back_en		: std_logic := '0';
+	
+	signal pktgen_tx		: unsigned(7 downto 0);
+	signal pktgen_tx_en		: std_logic;
+	signal pktgen_tx_er		: std_logic;
+	signal pktgen_rst		: std_logic := '1';
+
+	signal dat_o_cnt_en		: std_logic := '0';
+	signal dat_o_cnt_rst	: std_logic := '1';
+	signal dat_o_cnt		: natural;
+	signal pkt_count		: natural;
+	
+	type emac_action_t is (emac_idle, emac_alloc, emac_write, emac_commit, emac_wait_data, emac_read, emac_free);
+	signal emac_action	: emac_action_t;
+	
+BEGIN
+
+inst_emac_top_jb : entity work.emac_top_jb
+	GENERIC MAP
+	(
+		f_sysclk	=> 100.0,
+		RX_RAM_SIZE	=> 2048,
+		TX_RAM_SIZE	=> 2048
+	)
+	PORT MAP
+	(
+		CLK_I		=> CLK,
+		RST_I		=> RST,
+		INT_O		=> INT_O,
+		CYC_I		=> CYC_I,
+		STB_I		=> STB_I,
+		SEL_I		=> SEL_I,
+		WE_I		=> WE_I,
+		ACK_O		=> ACK_O,
+		SRDY_O		=> SRDY_O,
+		MRDY_I		=> MRDY_I,
+		ADDR_I		=> ADDR_I,
+		DAT_I		=> DAT_I,
+		DAT_O		=> DAT_O,
+		mii_rx_clk	=> mii_rx_clk_board,
+		mii_rx_dv	=> mii_rx_dv,
+		mii_rx_er	=> mii_rx_er,
+		mii_rx		=> mii_rx,
+		mii_tx_clk	=> mii_tx_clk_board,
+		mii_tx_en	=> mii_tx_en,
+		mii_tx_er	=> mii_tx_er,
+		mii_tx		=> mii_tx,
+		mii_gtx_clk	=> mii_gtx_clk,
+		mii_crs		=> mii_crs,
+		mii_col		=> mii_col
+		
+	);
+
+inst_pkt_gen : entity work.pkt_gen
+	GENERIC MAP
+	(
+		f_sysclk		=> 100.0,
+		PKT_DLY_MIN		=> 1.0E-6,
+		PKT_DLY_MAX		=> 5.0E-6,
+		PKT_SIZE_MIN	=> 64,
+		PKT_SIZE_MAX	=> 1512
+		
+	)
+	PORT MAP
+	(
+		clk			=> CLK,
+		rst			=> pktgen_rst,
+		mii_tx_clk	=> mii_tx_clk_board,
+		mii_tx_en	=> pktgen_tx_en,
+		mii_tx_er	=> pktgen_tx_er,
+		mii_tx		=> pktgen_tx
+		
+	);
+
+
+CLK_GEN: process
+	begin
+		wait for CLK_PERIOD/2;
+		CLK <= not CLK;
+	end process;
+
+MII_CLK_GEN: process
+	begin
+		wait for MII_CLK_PERIOD/2;
+		mii_rx_clk <= not mii_rx_clk;
+		mii_tx_clk <= not mii_tx_clk;
+	end process;
+
+	mii_rx_clk_board <= mii_rx_clk;
+	mii_tx_clk_board <= mii_tx_clk;
+
+DAT_O_register:
+	process(CLK)
+	begin
+		if rising_edge(CLK) then
+			if ACK_O = '1' then
+				DAT_O_reg	<= DAT_O;
+			end if;
+		end if;
+	end process;
+	
+DAT_O_count_register:
+	process(CLK)
+	begin
+		if rising_edge(CLK) then
+			if dat_o_cnt_rst = '1' then
+				dat_o_cnt <= 0;
+			elsif ACK_O = '1' and dat_o_cnt_en = '1' then
+				dat_o_cnt	<= dat_o_cnt + 1;
+			end if;
+		end if;
+	end process;
+
+	mii_rx		<= mii_tx when loop_back_en = '1' else pktgen_tx;
+	mii_rx_dv	<= mii_tx_en when loop_back_en = '1' else pktgen_tx_en;
+	mii_rx_er	<= mii_tx_er when loop_back_en = '1' else pktgen_tx_er;
+	mii_crs		<= '0';
+	mii_col		<= '0';
+	
+-- Master
+STIMULUS: process
+
+	procedure emac_alloc (size : natural) is
+	begin
+	
+		-- TX-ALLOCATION
+		-- set TX-size
+		emac_action	<= emac_alloc;
+		CYC_I	<= '1';
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		DAT_I	<= to_unsigned(size, 16) & X"55AA";
+		STB_I	<= '1';
+		WE_I	<= '1';
+		ADDR_I	<= X"0000_0004";
+
+	check_alloc_ok:
+		while(true) loop
+
+			-- set alloc request
+			wait until rising_edge(CLK) and SRDY_O = '1';
+			DAT_I	<= X"0200_0000";
+			STB_I	<= '1';
+			WE_I	<= '1';
+			ADDR_I	<= X"0000_0000";
+
+		check_bsy:
+			while (true) loop
+				wait until rising_edge(CLK) and SRDY_O = '1';
+				WE_I	<= '0';
+				STB_I	<= '1';
+				ADDR_I	<= X"0000_0000";
+				wait until rising_edge(CLK) and SRDY_O = '1';
+				STB_I	<= '0';
+				wait until rising_edge(CLK) and ACK_O = '1';
+				wait until rising_edge(CLK);
+				if DAT_O_reg(25) = '0' then
+					exit check_bsy;
+				end if;
+			end loop;
+			if DAT_O_reg(24) = '1' then
+				exit check_alloc_ok;
+			end if;
+		end loop;
+		CYC_I	<= '0';
+		
+		emac_action	<= emac_idle;
+
+	end procedure emac_alloc;
+	
+	procedure emac_commit  is
+	begin
+	
+		-- RX- DEALLOCATION
+		emac_action	<= emac_commit;
+
+		-- set free request
+		CYC_I	<= '1';
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		DAT_I	<= X"0100_0000";
+		STB_I	<= '1';
+		WE_I	<= '1';
+		ADDR_I	<= X"0000_0000";
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		STB_I	<= '0';
+		WE_I	<= '0';
+
+		emac_action	<= emac_idle;
+
+	end procedure emac_commit;
+
+	procedure emac_write (size : natural) is
+	variable data : unsigned (7 downto 0);
+	variable num_words : natural;
+	begin
+
+		-- FILL TX data
+		emac_action	<= emac_write;
+		if (size mod 4) = 0 then
+			num_words	:= size/4;
+		else
+			num_words	:= size/4 + 1;
+		end if;
+		
+		CYC_I	<= '1';
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		data	:= X"00";
+		ADDR_I	<= X"0000_0008";
+		WE_I	<= '1';
+		for i in 1 to num_words loop
+			STB_I	<= '1';
+			DAT_I(7 downto 0)	<= data;
+			data				:= data + 1;
+			DAT_I(15 downto 8)	<= data;
+			data				:= data + 1;
+			DAT_I(23 downto 16)	<= data;
+			data				:= data + 1;
+			DAT_I(31 downto 24)	<= data;
+			data				:= data + 1;
+			wait until rising_edge(CLK) and SRDY_O = '1';
+		end loop;
+
+		STB_I	<= '0';
+		wait until rising_edge(CLK) and SRDY_O = '1';
+
+ 		emac_commit;
+
+		emac_action	<= emac_idle;
+
+	end procedure emac_write;
+
+	procedure emac_read (size_in : natural) is
+	variable data : unsigned (7 downto 0);
+	variable size, num_words : natural;
+	begin
+
+		emac_action	<= emac_wait_data;
+
+		-- check if data available
+	check_data_avail:
+		while (true) loop
+			CYC_I	<= '1';
+			wait until rising_edge(CLK) and SRDY_O = '1';
+			WE_I	<= '0';
+			STB_I	<= '1';
+			ADDR_I	<= X"0000_0000";
+			wait until rising_edge(CLK) and SRDY_O = '1';
+			STB_I	<= '0';
+			wait until rising_edge(CLK) and ACK_O = '1';
+			wait until rising_edge(CLK);
+			if DAT_O_reg(16) = '1' then
+				exit check_data_avail;
+			end if;
+		end loop;
+
+	read_size:
+		dat_o_cnt_rst <= '1';
+		CYC_I	<= '1';
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		WE_I	<= '0';
+		STB_I	<= '1';
+		ADDR_I	<= X"0000_0004";
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		STB_I	<= '0';
+		wait until rising_edge(CLK) and ACK_O = '1';
+		wait until rising_edge(CLK);
+
+		-- set packet request
+		CYC_I	<= '1';
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		DAT_I	<= X"0001_0000";
+		STB_I	<= '1';
+		WE_I	<= '1';
+		ADDR_I	<= X"0000_0000";
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		STB_I	<= '0';
+		WE_I	<= '0';
+
+		emac_action	<= emac_read;
+		-- Read RX data
+		size := size_in;
+		if (size_in = 0) then
+			size	:= to_integer(DAT_O_reg(15 downto 0));
+		end if;
+		
+		if (size mod 4) = 0 then
+			num_words	:= size/4;
+		else
+			num_words	:= size/4 + 1;
+		end if;
+		
+		dat_o_cnt_rst <= '0';
+		dat_o_cnt_en <= '1';
+		CYC_I	<= '1';
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		data	:= X"00";
+		ADDR_I	<= X"0000_0008";
+		WE_I	<= '0';
+		STB_I	<= '1';
+		for i in 1 to num_words loop
+			wait until rising_edge(CLK) and SRDY_O = '1';
+		end loop;
+		STB_I	<= '0';
+		wait until rising_edge(CLK) and dat_o_cnt = num_words;
+		dat_o_cnt_en <= '0';
+		emac_action	<= emac_idle;
+
+	end procedure emac_read;
+
+	procedure emac_free  is
+	begin
+	
+		-- RX- DEALLOCATION
+		emac_action	<= emac_free;
+
+		-- set free request
+		CYC_I	<= '1';
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		DAT_I	<= X"0002_0000";
+		STB_I	<= '1';
+		WE_I	<= '1';
+		ADDR_I	<= X"0000_0000";
+		wait until rising_edge(CLK) and SRDY_O = '1';
+		STB_I	<= '0';
+		WE_I	<= '0';
+
+		emac_action	<= emac_idle;
+
+	end procedure emac_free;
+
+	begin
+
+		wait for 6*MII_CLK_PERIOD;
+		RST <= '0';
+		wait for 60*CLK_PERIOD;
+
+ 		emac_alloc (1004);
+ 		emac_alloc (1004);
+ 		emac_alloc (1004);
+ 		emac_alloc (1004);
+ 		emac_alloc (1004);
+ 		emac_alloc (1004);
+ 		emac_alloc (1004);
+ 		emac_alloc (1004);
+ 		emac_alloc (1004);
+ 		emac_alloc (1004);
+ 		emac_alloc (1004);
+ 		emac_alloc (1004);
+
+		for i in 1 to 10 loop
+			for j in 1 to 100 loop
+		 		emac_alloc (72);
+		 		emac_write (72);
+			end loop;
+			wait for 1 ms;
+		end loop;
+		
+		wait until rising_edge(mii_tx_clk) and mii_tx_en = '0';
+		wait for 6000*CLK_PERIOD;
+		
+		loop_back_en	<= '1';
+		
+ 		emac_alloc (74);
+ 		emac_write (74);
+ 
+ 		emac_alloc (105);
+ 		emac_write (105);
+
+		emac_read (0);
+		emac_free;
+
+		emac_read (0);
+		emac_free;
+
+ 		emac_alloc (103);
+ 		emac_write (103);
+
+		emac_read (0);
+		emac_free;
+
+ 		emac_alloc (71);
+ 		emac_write (71);
+ 
+		emac_read (0);
+		emac_free;
+
+ 		emac_alloc (82);
+ 		emac_write (82);
+
+ 		emac_alloc (86);
+ 		emac_write (86);
+
+		emac_read (0);
+		emac_free;
+
+		emac_read (0);
+		emac_free;
+
+ 		emac_alloc (77);
+ 		emac_write (77);
+
+ 		emac_alloc (99);
+ 		emac_write (99);
+
+ 		emac_alloc (65);
+ 		emac_write (65);
+
+ 		emac_alloc (321);
+ 		emac_write (321);
+
+		emac_read (0);
+		emac_free;
+
+ 		emac_alloc (1111);
+ 		emac_write (1111);
+
+		emac_read (0);
+		emac_free;
+
+ 		emac_alloc (73);
+ 		emac_write (73);
+
+ 		emac_alloc (107);
+ 		emac_write (107);
+
+ 		emac_alloc (83);
+ 		emac_write (83);
+
+		emac_read (0);
+		emac_free;
+
+ 		emac_alloc (72);
+ 		emac_write (72);
+
+ 		emac_alloc (1003);
+ 		emac_write (1003);
+
+		emac_read (0);
+		emac_free;
+
+		emac_read (0);
+		emac_free;
+
+		emac_read (0);
+		emac_free;
+
+		emac_read (0);
+		emac_free;
+
+		emac_read (0);
+		emac_free;
+
+		emac_read (0);
+		emac_free;
+
+		emac_read (0);
+		emac_free;
+
+		wait for 6000*CLK_PERIOD;
+
+		loop_back_en	<= '0';
+		pktgen_rst		<= '0';
+		pkt_count		<= 0;
+		for i in 1 to 500 loop
+			wait for 10 us;
+			emac_read (0);
+			emac_free;
+			pkt_count	<= pkt_count + 1;
+		end loop;
+		pktgen_rst		<= '1';
+		emac_read (0);
+		emac_free;
+			
+
+		wait; 
+	
+	end process;
+	
+END;

lib/misc/pkg_template.vhd

@@ -1,19 +0,0 @@
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/pkg_template.vhd,v 1.1.4.1 2013-08-18 07:10:17 jens Exp $
------------------------------------------------------------------------
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-package template_pkg is
-
-	-- Constants
-	-- Types
-	-- Functions
-
-end template_pkg;
-
-package body template_pkg is
-
-end template_pkg;
-