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- changed register rudimentary register layout (new offsets!)

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- added new regsiter features: status/ctrl register cursor position, screen resolution


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git-svn-id: http://moon:8086/svn/vhdl/trunk@604 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-11-04 19:31:47 +00:00
parent 381e7cc659
commit 2ab1b93e51
2 changed files with 217 additions and 73 deletions
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lib/VGA_ctrl/src/vga_frontend.vhd
+110 -30
View File
@@ -113,10 +113,14 @@ architecture Behavioral of vga_frontend is
signal cg_draw : std_logic;
signal cg_clr_screen : std_logic;
signal cg_clr_line : std_logic;
signal cg_ascii_data : unsigned(7 downto 0);
signal cg_ascii_data_we : std_logic;
signal cg_ascii_posy_we : std_logic;
signal cg_ascii_posx_we : std_logic;
signal cg_din : unsigned(7 downto 0);
signal cg_dout : unsigned(7 downto 0);
signal cg_ascii_we : std_logic;
signal cg_posy_we : std_logic;
signal cg_posx_we : std_logic;
signal cg_color : color_t;
signal cg_csr_pos_x : natural range 0 to 80-1;
signal cg_csr_pos_y : natural range 0 to 32-1;
-- Bus master signals
constant MAX_REQUEST_CNT : natural := tsvga.ts_h.ncyc_scan*tsvga.ts_v.ncyc_scan;
@@ -183,7 +187,7 @@ inst_vga_backend : entity work.vga_backend
color_en(0) <= not fifo_empty;
color_en(1) <= cg_draw;
color_in(0) <= to_color_t(fifo_color_out);
color_in(1) <= (X"FF", X"FF", X"FF", X"FF"); -- white opaque
color_in(1) <= cg_color; --(X"FF", X"FF", X"FF", X"FF"); -- white opaque
color_op <= op_over;
vga_scan_rdy <= stat_hready and stat_vready;
@@ -360,52 +364,128 @@ inst_char_gen : entity work.char_gen
frame_pulse => scan_rdy,
clr_screen => cg_clr_screen,
clr_line => cg_clr_line,
ascii_data => cg_ascii_data,
ascii_data_we => cg_ascii_data_we,
ascii_posy_we => cg_ascii_posy_we,
ascii_posx_we => cg_ascii_posx_we,
din => cg_din,
dout => cg_dout,
ascii_we => cg_ascii_we,
posy_we => cg_posy_we,
posx_we => cg_posx_we,
ready => cg_rdy,
pos_x => stat_hpos,
pos_y => stat_vpos,
scan_pos_x_in => stat_hpos,
scan_pos_y_in => stat_vpos,
csr_pos_x_out => cg_csr_pos_x,
csr_pos_y_out => cg_csr_pos_y,
char_draw_en => cg_draw
);
SRDY_O <= CYC_I; -- and cg_rdy;
cg_ascii_data <= SDAT_I(7 downto 0);
cg_ascii_data_we <= ADDR_I(2) and CYC_I and STB_I and WE_I;
cg_ascii_posy_we <= ADDR_I(3) and CYC_I and STB_I and WE_I;
cg_ascii_posx_we <= ADDR_I(4) and CYC_I and STB_I and WE_I;
cg_clr_screen <= ADDR_I(5) and CYC_I and STB_I and WE_I;
cg_clr_line <= ADDR_I(6) and CYC_I and STB_I and WE_I;
SDAT_O <= X"0000000" & "000" & cg_rdy;
-- SDAT_O <= X"0000000" & "000" & cg_rdy;
MDAT_O <= (others => '-');
scan_rdy <= stat_hready and stat_vready;
cg_en <= stat_scan;
data_register:
registers_read:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
ACK_O <= '0';
else
ACK_O <= CYC_I and STB_I and not WE_I;
ACK_O <= '0';
if (STB_I and CYC_I) = '1' then
ACK_O <= not WE_I;
SDAT_O <= (others => '0');
case ADDR_I(5 downto 2) is
-- sys_vga_ctrl 0
when "0000" =>
SDAT_O(0) <= cg_rdy;
SDAT_O(1) <= vga_master_en;
-- sys_vga_ascii 4
when "0001" =>
SDAT_O(7 downto 0) <= cg_dout;
-- sys_vga_posx 8
when "0010" =>
SDAT_O(7 downto 0) <= to_unsigned(cg_csr_pos_x, 8);
-- sys_vga_posy 12
when "0011" =>
SDAT_O(7 downto 0) <= to_unsigned(cg_csr_pos_y, 8);
-- sys_vga_cgcol 16
when "0100" =>
SDAT_O <= to_unsigned(cg_color);
-- sys_vga_moffs 20
when "0101" =>
SDAT_O <= vga_mem_offset;
-- sys_vga_resx 24
when "0110" =>
SDAT_O(15 downto 0) <= to_unsigned(tsvga.ts_h.ncyc_scan, 16);
-- sys_vga_resy 28
when "0111" =>
SDAT_O(15 downto 0) <= to_unsigned(tsvga.ts_v.ncyc_scan, 16);
-- sys_vga_fps 32
when "1000" =>
SDAT_O(15 downto 0) <= to_unsigned(tsvga.nfps, 16);
when others => null;
end case;
end if;
end if;
end if;
end process;
data_valid_register:
registers_write:
process(CLK_I)
begin
if rising_edge(CLK_I) then
cg_ascii_we <= '0';
cg_posy_we <= '0';
cg_posx_we <= '0';
cg_clr_screen <= '0';
cg_clr_line <= '0';
if RST_I = '1' then
cg_din <= (others => '0');
vga_master_en <= '0';
vga_mem_offset <= X"40000000";
elsif (CYC_I and STB_I and WE_I) = '1' then
if ADDR_I(8) = '1' then
vga_master_en <= SDAT_I(0);
elsif ADDR_I(9) = '1' then
cg_color <= (X"FF", X"FF", X"FF", X"FF");
elsif (STB_I and CYC_I and WE_I) = '1' then
case ADDR_I(5 downto 2) is
-- sys_vga_ctrl 0
when "0000" =>
vga_master_en <= SDAT_I(1);
cg_clr_screen <= SDAT_I(4);
cg_clr_line <= SDAT_I(5);
-- sys_vga_ascii 4
when "0001" =>
cg_ascii_we <= '1';
cg_din <= SDAT_I(7 downto 0);
-- sys_vga_posx 8
when "0010" =>
cg_posx_we <= '1';
cg_din <= SDAT_I(7 downto 0);
-- sys_vga_posy 12
when "0011" =>
cg_posy_we <= '1';
cg_din <= SDAT_I(7 downto 0);
-- sys_vga_cgcol 16
when "0100" =>
cg_color <= to_color_t(SDAT_I(31 downto 0));
-- sys_vga_moffs 20
when "0101" =>
vga_mem_offset <= SDAT_I(31 downto 2) & "00";
end if;
when others => null;
end case;
end if;
end if;
end process;
lib/VGA_ctrl/src/vga_frontend64.vhd
+107 -43
View File
@@ -111,11 +111,14 @@ architecture Behavioral of vga_frontend64 is
signal cg_draw : std_logic;
signal cg_clr_screen : std_logic;
signal cg_clr_line : std_logic;
signal cg_ascii_data : unsigned(7 downto 0);
signal cg_ascii_data_we : std_logic;
signal cg_ascii_posy_we : std_logic;
signal cg_ascii_posx_we : std_logic;
signal cg_din : unsigned(7 downto 0);
signal cg_dout : unsigned(7 downto 0);
signal cg_ascii_we : std_logic;
signal cg_posy_we : std_logic;
signal cg_posx_we : std_logic;
signal cg_color : color_t;
signal cg_csr_pos_x : natural range 0 to 80-1;
signal cg_csr_pos_y : natural range 0 to 32-1;
-- Bus master signals
constant MAX_REQUEST_CNT : natural := tsvga.ts_h.ncyc_scan*tsvga.ts_v.ncyc_scan;
@@ -365,71 +368,132 @@ inst_char_gen : entity work.char_gen
frame_pulse => scan_rdy,
clr_screen => cg_clr_screen,
clr_line => cg_clr_line,
ascii_data => cg_ascii_data,
ascii_data_we => cg_ascii_data_we,
ascii_posy_we => cg_ascii_posy_we,
ascii_posx_we => cg_ascii_posx_we,
din => cg_din,
dout => cg_dout,
ascii_we => cg_ascii_we,
posy_we => cg_posy_we,
posx_we => cg_posx_we,
ready => cg_rdy,
pos_x => stat_hpos,
pos_y => stat_vpos,
scan_pos_x_in => stat_hpos,
scan_pos_y_in => stat_vpos,
csr_pos_x_out => cg_csr_pos_x,
csr_pos_y_out => cg_csr_pos_y,
char_draw_en => cg_draw
);
SRDY_O <= CYC_I; -- and cg_rdy;
SDAT_O <= X"0000000" & "000" & cg_rdy;
-- SDAT_O <= X"0000000" & "000" & cg_rdy;
MDAT_O <= (others => '-');
scan_rdy <= stat_hready and stat_vready;
cg_en <= stat_scan;
data_register:
registers_read:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
ACK_O <= '0';
else
ACK_O <= CYC_I and STB_I and not WE_I;
ACK_O <= '0';
if (STB_I and CYC_I) = '1' then
ACK_O <= not WE_I;
SDAT_O <= (others => '0');
case ADDR_I(5 downto 2) is
-- sys_vga_ctrl 0
when "0000" =>
SDAT_O(0) <= cg_rdy;
SDAT_O(1) <= vga_master_en;
-- sys_vga_ascii 4
when "0001" =>
SDAT_O(7 downto 0) <= cg_dout;
-- sys_vga_posx 8
when "0010" =>
SDAT_O(7 downto 0) <= to_unsigned(cg_csr_pos_x, 8);
-- sys_vga_posy 12
when "0011" =>
SDAT_O(7 downto 0) <= to_unsigned(cg_csr_pos_y, 8);
-- sys_vga_cgcol 16
when "0100" =>
SDAT_O <= to_unsigned(cg_color);
-- sys_vga_moffs 20
when "0101" =>
SDAT_O <= vga_mem_offset;
-- sys_vga_resx 24
when "0110" =>
SDAT_O(15 downto 0) <= to_unsigned(tsvga.ts_h.ncyc_scan, 16);
-- sys_vga_resy 28
when "0111" =>
SDAT_O(15 downto 0) <= to_unsigned(tsvga.ts_v.ncyc_scan, 16);
-- sys_vga_fps 32
when "1000" =>
SDAT_O(15 downto 0) <= to_unsigned(tsvga.nfps, 16);
when others => null;
end case;
end if;
end if;
end if;
end process;
data_valid_register:
registers_write:
process(CLK_I)
begin
if rising_edge(CLK_I) then
cg_ascii_data_we <= '0';
cg_ascii_posy_we <= '0';
cg_ascii_posx_we <= '0';
cg_clr_screen <= '0';
cg_clr_line <= '0';
cg_ascii_we <= '0';
cg_posy_we <= '0';
cg_posx_we <= '0';
cg_clr_screen <= '0';
cg_clr_line <= '0';
if RST_I = '1' then
cg_din <= (others => '0');
vga_master_en <= '0';
vga_mem_offset <= X"40000000";
cg_color <= (X"FF", X"FF", X"FF", X"FF");
elsif (CYC_I and STB_I and WE_I) = '1' then
if ADDR_I(2) = '1' then
cg_ascii_data_we <= '1';
cg_ascii_data <= SDAT_I(7 downto 0);
elsif ADDR_I(3) = '1' then
cg_ascii_posy_we <= '1';
cg_ascii_data <= SDAT_I(7 downto 0);
elsif ADDR_I(4) = '1' then
cg_ascii_posx_we <= '1';
cg_ascii_data <= SDAT_I(7 downto 0);
elsif ADDR_I(5) = '1' then
cg_clr_screen <= '1';
elsif ADDR_I(6) = '1' then
cg_clr_line <= '1';
elsif ADDR_I(7) = '1' then
elsif (STB_I and CYC_I and WE_I) = '1' then
case ADDR_I(5 downto 2) is
-- sys_vga_ctrl 0
when "0000" =>
vga_master_en <= SDAT_I(1);
cg_clr_screen <= SDAT_I(4);
cg_clr_line <= SDAT_I(5);
-- sys_vga_ascii 4
when "0001" =>
cg_ascii_we <= '1';
cg_din <= SDAT_I(7 downto 0);
-- sys_vga_posx 8
when "0010" =>
cg_posx_we <= '1';
cg_din <= SDAT_I(7 downto 0);
-- sys_vga_posy 12
when "0011" =>
cg_posy_we <= '1';
cg_din <= SDAT_I(7 downto 0);
-- sys_vga_cgcol 16
when "0100" =>
cg_color <= to_color_t(SDAT_I(31 downto 0));
elsif ADDR_I(8) = '1' then
vga_master_en <= SDAT_I(0);
elsif ADDR_I(9) = '1' then
-- sys_vga_moffs 20
when "0101" =>
vga_mem_offset <= SDAT_I(31 downto 2) & "00";
end if;
when others => null;
end case;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------
end Behavioral;