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- read-page cycle is minimum 2 cycles

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- change assertion check: Read page pulse length must be greater than one

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git-svn-id: http://moon:8086/svn/vhdl/trunk@563 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-10-30 10:49:15 +00:00
parent 9ad3c6cd4e
commit 989fe72ddb
1 changed files with 2 additions and 2 deletions
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lib/misc/async_port_wb.vhd
+2 -2
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@@ -1,5 +1,5 @@
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.8 2009-10-29 22:56:20 Jens Exp $
-- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.9 2009-10-30 10:49:15 Jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
@@ -74,7 +74,7 @@ architecture Behavioral of async_port_wb is
ASSERT async_timespec.ncyc_pulse_rd > 0 report "Read pulse length must be greater than zero!" severity failure;
ASSERT async_timespec.ncyc_pulse_wr > 0 report "Write pulse length must be greater than zero!" severity failure;
ASSERT (not async_timespec.can_page_rd OR (async_timespec.ncyc_pulse_page_rd > 0)) report "Read page pulse length must be greater than zero!" severity failure;
ASSERT (not async_timespec.can_page_rd OR (async_timespec.ncyc_pulse_page_rd > 1)) report "Read page pulse length must be greater than one!" severity failure;
SRDY_O <= CYC_I and rdyo;
en <= CYC_I and STB_I;