- added asynchronous BUS FIFOs

- added cpu_clk
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git-svn-id: http://moon:8086/svn/vhdl/trunk@726 cc03376c-175c-47c8-b038-4cd826a8556b

lib/CPUs/MIPS/src/tb_mips_top.vhd

@@ -37,6 +37,7 @@ END tb_mips_top;
 
 ARCHITECTURE behavior OF tb_mips_top IS 
 
+	constant SYS_FREQ	 			: natural := 100E6;
 	constant CLK_PERIOD 			: time := 10 ns;
 	constant SRAM_ADDR_WIDTH		: integer := 17;		-- bits
 	constant FLASH_ADDR_WIDTH		: integer := 17;		-- bits
@@ -207,6 +208,7 @@ uut: entity work.mips_top
 	(
 		debug			=> debug,
 		eb				=> eb,
+		cpu_clk			=> clk,
 		RST_I			=> rst,
 		CLK_I			=> clk,
 		ACK_I			=> ACK_I,
@@ -265,6 +267,7 @@ inst_gpio : entity work.gpio_wb
 inst_flash_port : entity work.async_port_wb
 	GENERIC MAP
 	(
+		f_sysclk_hz		=> SYS_FREQ,
 		addr_width		=> FLASH_ADDR_WIDTH,
 		data_width		=> 32,
 		byte_sel_width	=> 4,
@@ -297,6 +300,7 @@ inst_flash_port : entity work.async_port_wb
 inst_sram_port : entity work.async_port_wb
 	GENERIC MAP
 	(
+		f_sysclk_hz		=> SYS_FREQ,
 		addr_width		=> SRAM_ADDR_WIDTH,
 		data_width		=> 32,
 		byte_sel_width	=> 4,