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- use async_be

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git-svn-id: http://moon:8086/svn/vhdl/trunk@326 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-02-08 17:34:55 +00:00
parent 5226b0bb0a
commit 0e825a1df5
5 changed files with 72 additions and 40 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/CPUs/MIPS/sim/tb_mips_top.wdo
+9 -2
View File
@@ -31,9 +31,11 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_a
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_d
add wave -noupdate -format Logic /tb_mips_top/flash_cs_n
add wave -noupdate -format Logic /tb_mips_top/flash_oe_n
add wave -noupdate -format Literal /tb_mips_top/flash_be_n
add wave -noupdate -format Logic /tb_mips_top/sram_cs_n
add wave -noupdate -format Literal /tb_mips_top/sram_wr_n
add wave -noupdate -format Logic /tb_mips_top/sram_oe_n
add wave -noupdate -format Literal /tb_mips_top/sram_be_n
add wave -noupdate -divider ALU
add wave -noupdate -format Logic /tb_mips_top/clk
add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline/hdu
@@ -49,8 +51,13 @@ add wave -noupdate -format Logic /tb_mips_top/clk
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/mem_stage
add wave -noupdate -format Logic /tb_mips_top/clk
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/wb_stage
add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/rst
add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/cpu_rst
add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/cpu_run
add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/run_en
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/inst_reg_dual/reg_mem
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {1199854590 ps} 0}
WaveRestoreCursors {{Cursor 1} {1375665640 ps} 0}
configure wave -namecolwidth 188
configure wave -valuecolwidth 100
configure wave -justifyvalue left
@@ -64,4 +71,4 @@ configure wave -gridperiod 100
configure wave -griddelta 40
configure wave -timeline 1
update
WaveRestoreZoom {0 ps} {1260 us}
WaveRestoreZoom {0 ps} {1680 us}
lib/CPUs/MIPS/src/tb_mips_top.vhd
+51 -27
View File
@@ -86,8 +86,10 @@ ARCHITECTURE behavior OF tb_mips_top IS
signal flash_cs_n : std_logic;
signal flash_oe_n : std_logic;
signal flash_be_n : unsigned(3 downto 0);
signal sram_cs_n : std_logic;
signal sram_wr_n : unsigned(3 downto 0);
signal sram_be_n : unsigned(3 downto 0);
signal sram_wr_n : std_logic;
signal sram_oe_n : std_logic;
signal sram_a : unsigned(SRAM_ADDR_WIDTH-1 downto 0);
signal sram_d : unsigned(31 downto 0);
@@ -254,7 +256,7 @@ inst_flash_port : entity work.async_port_wb
(
addr_width => FLASH_ADDR_WIDTH,
data_width => 32,
byte_sel_width => 1,
byte_sel_width => 4,
async_timespec => ts_flash
)
PORT MAP
@@ -276,6 +278,7 @@ inst_flash_port : entity work.async_port_wb
async_cs => flash_cs_n,
async_wr => open,
async_rd => flash_oe_n,
async_be => flash_be_n,
async_rst => open
);
@@ -306,6 +309,7 @@ inst_sram_port : entity work.async_port_wb
async_cs => sram_cs_n,
async_wr => sram_wr_n,
async_rd => sram_oe_n,
async_be => sram_be_n,
async_rst => open
);
@@ -332,38 +336,45 @@ inst_uart : entity work.uart_wb
------------------------------------------------------------------
SRAM_READ:
process(sram_a, sram_cs_n, sram_oe_n)
process(sram_a, sram_cs_n, sram_oe_n, sram_be_n)
begin
sram_d <= (others => 'Z');
sram_d <= (others => 'Z') after 10 ns;
if sram_oe_n = '0' then
if sram_cs_n = '0' then
sram_d <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)));
if sram_be_n(0) = '0' then
sram_d(7 downto 0) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(7 downto 0) after 10 ns;
end if;
if sram_be_n(1) = '0' then
sram_d(15 downto 8) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(15 downto 8) after 10 ns;
end if;
if sram_be_n(2) = '0' then
sram_d(23 downto 16) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(23 downto 16) after 10 ns;
end if;
if sram_be_n(3) = '0' then
sram_d(31 downto 24) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(31 downto 24) after 10 ns;
end if;
end if;
end if;
end process;
SRAM_WRITE:
process(sram_a, sram_cs_n, sram_wr_n)
process(sram_wr_n)
begin
if rising_edge(sram_wr_n(0)) then
if rising_edge(sram_wr_n) then
if sram_cs_n = '0' then
sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(7 downto 0) <= sram_d(7 downto 0);
end if;
end if;
if rising_edge(sram_wr_n(1)) then
if sram_cs_n = '0' then
sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(15 downto 8) <= sram_d(15 downto 8);
end if;
end if;
if rising_edge(sram_wr_n(2)) then
if sram_cs_n = '0' then
sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(23 downto 16) <= sram_d(23 downto 16);
end if;
end if;
if rising_edge(sram_wr_n(3)) then
if sram_cs_n = '0' then
sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(31 downto 24) <= sram_d(31 downto 24);
end if;
if sram_be_n(0) = '0' then
sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(7 downto 0) <= sram_d(7 downto 0);
end if;
if sram_be_n(1) = '0' then
sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(15 downto 8) <= sram_d(15 downto 8);
end if;
if sram_be_n(2) = '0' then
sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(23 downto 16) <= sram_d(23 downto 16);
end if;
if sram_be_n(3) = '0' then
sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(31 downto 24) <= sram_d(31 downto 24);
end if;
end if;
end if;
end process;
@@ -386,9 +397,22 @@ FLASH_READ:
end loop;
else
flash_d <= (others => 'Z') after 10 ns;
if flash_oe_n = '0' and flash_cs_n = '0' then
index := to_integer(flash_a(FLASH_ADDR_WIDTH-1 downto 2));
flash_d <= flash_data(index) after 10 ns;
index := to_integer(flash_a(FLASH_ADDR_WIDTH-1 downto 2));
if flash_oe_n = '0' then
if flash_cs_n = '0' then
if flash_be_n(0) = '0' then
flash_d(7 downto 0) <= flash_data(index)(7 downto 0) after 10 ns;
end if;
if flash_be_n(1) = '0' then
flash_d(15 downto 8) <= flash_data(index)(15 downto 8) after 10 ns;
end if;
if flash_be_n(2) = '0' then
flash_d(23 downto 16) <= flash_data(index)(23 downto 16) after 10 ns;
end if;
if flash_be_n(3) = '0' then
flash_d(31 downto 24) <= flash_data(index)(31 downto 24) after 10 ns;
end if;
end if;
end if;
end if;
end process;
projects/mips_sys/src/mips_sys.vhd
+6 -7
View File
@@ -218,8 +218,9 @@ ARCHITECTURE behavior OF mips_sys IS
async_a : out unsigned(addr_width-1 downto 0);
async_d : inout unsigned(data_width-1 downto 0);
async_cs : out std_logic;
async_wr : out unsigned(byte_sel_width-1 downto 0);
async_wr : out std_logic;
async_rd : out std_logic;
async_be : out unsigned(byte_sel_width-1 downto 0);
async_rst : out std_logic
);
END COMPONENT;
@@ -331,8 +332,6 @@ ARCHITECTURE behavior OF mips_sys IS
signal flash_addr : unsigned(31 downto 0);
signal ac97_rstn : std_logic;
signal flash_rstn : std_logic;
signal usb_wrn : unsigned(0 downto 0);
signal flash_wrn : unsigned(0 downto 0);
-- Arbiter
constant ARB_MAX_MASTER : natural := 2;
@@ -461,8 +460,6 @@ BEGIN
SEL_I_sdram <= "0000" & SEL_O;
sys_flash_ac97_rstn <= ac97_rstn and flash_rstn;
sys_usb_wrn <= usb_wrn(0);
sys_flash_wrn <= flash_wrn(0);
---------------------------------------------------------------
-- Arbiter
@@ -717,8 +714,9 @@ inst_flash_port : async_port_wb
async_a => sys_flash_a,
async_d => sys_flash_d,
async_cs => sys_flash_ce,
async_wr => flash_wrn,
async_wr => sys_flash_wrn,
async_rd => sys_flash_rdn,
async_be => open,
async_rst => flash_rstn
);
@@ -747,8 +745,9 @@ inst_usb_port : async_port_wb
async_a => sys_usb_a,
async_d => sys_usb_d,
async_cs => sys_usb_csn,
async_wr => usb_wrn,
async_wr => sys_usb_wrn,
async_rd => sys_usb_rdn,
async_be => open,
async_rst => open
);
projects/mips_sys/src/mips_sys_sim.vhd
+4 -4
View File
@@ -228,8 +228,9 @@ ARCHITECTURE behavior OF mips_sys IS
async_a : out unsigned(addr_width-1 downto 0);
async_d : inout unsigned(data_width-1 downto 0);
async_cs : out std_logic;
async_wr : out unsigned(byte_sel_width-1 downto 0);
async_wr : out std_logic;
async_rd : out std_logic;
async_be : out unsigned(byte_sel_width-1 downto 0);
async_rst : out std_logic
);
END COMPONENT;
@@ -388,7 +389,6 @@ ARCHITECTURE behavior OF mips_sys IS
signal flash_we_n : std_logic;
signal flash_d_drv : std_logic;
signal flash_bsy : std_logic;
signal usb_wrn : unsigned(0 downto 0);
-- Arbiter
constant ARB_MAX_MASTER : natural := 2;
@@ -515,7 +515,6 @@ BEGIN
rst_in <= not sys_rst_n_in;
rst <= not locked;
sys_usb_rstn <= not gpo1(0);
sys_usb_wrn <= usb_wrn(0);
sys_flash_byten <= '1';
ADDR_I_usb <= X"0000000" & "00" & ADDR_O(3 downto 2);
ADDR_I_flash <= "0000000" & ADDR_O(25 downto 2) & '0';
@@ -844,8 +843,9 @@ inst_usb_port : async_port_wb
async_a => sys_usb_a,
async_d => sys_usb_d,
async_cs => sys_usb_csn,
async_wr => usb_wrn,
async_wr => sys_usb_wrn,
async_rd => sys_usb_rdn,
async_be => open,
async_rst => open
);
projects/mips_sys/src/sys_types.vhd
+2
View File
@@ -40,6 +40,7 @@ package async_defs is
pol_cs => '1',
pol_oe => '0',
pol_we => '0',
pol_be => '0',
pol_rst => '0'
);
@@ -54,6 +55,7 @@ package async_defs is
pol_cs => '0',
pol_oe => '0',
pol_we => '0',
pol_be => '0',
pol_rst => '0'
);