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git-svn-id: http://moon:8086/svn/vhdl/trunk@293 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-01-30 21:11:41 +00:00
parent f2faffb88f
commit aacedf75a9
5 changed files with 0 additions and 177 deletions
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lib/FIFO/sim/tb_async_fifo_ctrl.fdo
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## NOTE: Do not edit this file.
##
vlib work
vcom -explicit -93 "../src/fifo_ctrl_pkg.vhd"
vcom -explicit -93 "../src/gray_counter.vhd"
vcom -explicit -93 "../src/dpram.vhd"
vcom -explicit -93 "../src/async_fifo_ctrl.vhd"
vcom -explicit -93 "../src/tb_async_fifo_ctrl.vhd"
vsim -t 1ps -lib work tb_async_fifo_ctrl
view wave
do {tb_async_fifo_ctrl.wdo}
view structure
view signals
run 10us
lib/FIFO/sim/tb_async_fifo_ctrl.wdo
-36
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onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_async_fifo_ctrl/rst
add wave -noupdate -format Logic /tb_async_fifo_ctrl/clk_w
add wave -noupdate -format Logic /tb_async_fifo_ctrl/we
add wave -noupdate -format Literal -radix hexadecimal /tb_async_fifo_ctrl/ptr_w
add wave -noupdate -format Logic /tb_async_fifo_ctrl/clk_r
add wave -noupdate -format Logic /tb_async_fifo_ctrl/re
add wave -noupdate -format Literal -radix hexadecimal /tb_async_fifo_ctrl/ptr_r
add wave -noupdate -format Logic /tb_async_fifo_ctrl/fifo_almost_empty
add wave -noupdate -format Logic /tb_async_fifo_ctrl/fifo_empty
add wave -noupdate -format Logic /tb_async_fifo_ctrl/fifo_almost_full
add wave -noupdate -format Logic /tb_async_fifo_ctrl/fifo_full
add wave -noupdate -format Literal -radix hexadecimal /tb_async_fifo_ctrl/din
add wave -noupdate -format Literal -radix hexadecimal /tb_async_fifo_ctrl/dout
add wave -noupdate -format Logic /tb_async_fifo_ctrl/uut/inst_gray_counter_w/ce
add wave -noupdate -format Literal -radix hexadecimal /tb_async_fifo_ctrl/uut/bnxt_w
add wave -noupdate -format Literal /tb_async_fifo_ctrl/uut/bcnt_r
add wave -noupdate -format Literal -radix decimal /tb_async_fifo_ctrl/uut/diffw
add wave -noupdate -format Literal -radix decimal /tb_async_fifo_ctrl/uut/diffr
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {250000 ps} 0}
configure wave -namecolwidth 190
configure wave -valuecolwidth 80
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 100
configure wave -griddelta 40
configure wave -timeline 1
update
WaveRestoreZoom {115874 ps} {612358 ps}
lib/FIFO/sim/tb_sync_fifo_ctrl.fdo
-15
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@@ -1,15 +0,0 @@
## NOTE: Do not edit this file.
##
vlib work
vcom -explicit -93 "../src/fifo_ctrl_pkg.vhd"
vcom -explicit -93 "../src/gray_counter.vhd"
vcom -explicit -93 "../src/dpram.vhd"
vcom -explicit -93 "../src/sync_fifo_ctrl.vhd"
vcom -explicit -93 "../src/tb_sync_fifo_ctrl.vhd"
vsim -t 1ps -lib work tb_sync_fifo_ctrl
view wave
do {tb_sync_fifo_ctrl.wdo}
view structure
view signals
run 10us
lib/FIFO/sim/tb_sync_fifo_ctrl.wdo
-32
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@@ -1,32 +0,0 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_sync_fifo_ctrl/rst
add wave -noupdate -format Logic /tb_sync_fifo_ctrl/we
add wave -noupdate -format Literal -radix hexadecimal /tb_sync_fifo_ctrl/ptr_w
add wave -noupdate -format Logic /tb_sync_fifo_ctrl/re
add wave -noupdate -format Literal -radix hexadecimal /tb_sync_fifo_ctrl/ptr_r
add wave -noupdate -format Logic /tb_sync_fifo_ctrl/fifo_almost_empty
add wave -noupdate -format Logic /tb_sync_fifo_ctrl/fifo_empty
add wave -noupdate -format Logic /tb_sync_fifo_ctrl/fifo_almost_full
add wave -noupdate -format Logic /tb_sync_fifo_ctrl/fifo_full
add wave -noupdate -format Literal -radix hexadecimal /tb_sync_fifo_ctrl/din
add wave -noupdate -format Literal -radix hexadecimal /tb_sync_fifo_ctrl/dout
add wave -noupdate -format Literal -radix unsigned /tb_sync_fifo_ctrl/uut/pw_next
add wave -noupdate -format Literal -radix unsigned /tb_sync_fifo_ctrl/uut/pr_next
add wave -noupdate -format Literal -radix unsigned /tb_sync_fifo_ctrl/uut/diff
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {290000 ps} 0}
configure wave -namecolwidth 190
configure wave -valuecolwidth 80
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 100
configure wave -griddelta 40
configure wave -timeline 1
update
WaveRestoreZoom {0 ps} {2166667 ps}
lib/FIFO/src/dpram.vhd
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-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: Dual-ported register file with asynchrous read
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/dpram.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
entity dpram is
Generic (
addr_width : integer := 3;
data_width : integer := 8
);
Port (
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
en_a : in STD_LOGIC;
en_b : in STD_LOGIC;
we_a : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
addr_b : in unsigned (addr_width-1 downto 0);
din_a : in unsigned (data_width-1 downto 0);
dout_b : out unsigned (data_width-1 downto 0)
);
end dpram;
architecture Behavioral of dpram is
constant depth : integer := 2**addr_width;
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
signal RAM : RAMtype;
begin
process (clka)
begin
if clka'event and clka = '1' then
if en_a = '1' then
if we_a = '1' then
RAM(to_integer(addr_a)) <= din_a;
end if;
end if;
end if;
end process;
process (clkb)
begin
if clkb'event and clkb = '1' then
if en_b = '1' then
dout_b <= RAM(to_integer(addr_b));
end if;
end if;
end process;
end Behavioral;