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- re-added state 'rd_cache'

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git-svn-id: http://moon:8086/svn/vhdl/trunk@341 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-02-11 10:55:42 +00:00
parent 44ef835b7a
commit 1597bc6240
2 changed files with 9 additions and 8 deletions
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lib/CPUs/MIPS/src/core/dcache.vhd
+4 -3
View File
@@ -127,7 +127,7 @@ END COMPONENT;
return result;
end to_tram_data;
type cache_state_t is (init, ready, flush, mem_request, mem_access, mem_wait, mem_data, upd_cache);
type cache_state_t is (init, ready, flush, mem_request, mem_access, mem_wait, mem_data, upd_cache, rd_cache);
signal s, sn : cache_state_t;
signal cache_busy : std_logic;
@@ -332,7 +332,6 @@ cache_state:
cache_entry_in.tv_p <= (others => '0');
cache_entry_in.tag <= tag_index_reg;
cache_entry_in.valid <= '0';
sn <= s;
case s is
@@ -390,8 +389,10 @@ cache_state:
tram_addr_wr <= cache_index_reg;
tram_we <= '1';
cache_entry_in.valid <= '1';
sn <= rd_cache;
when rd_cache =>
was_miss <= '1';
sn <= ready;
sn <= ready;
when others =>
sn <= ready;
lib/CPUs/MIPS/src/core/icache.vhd
+5 -5
View File
@@ -101,7 +101,7 @@ END COMPONENT;
return result;
end to_tag_ram_data;
type cache_state_t is (init, ready, flush, mem_request, mem_access, mem_wait, mem_data, upd_cache);
type cache_state_t is (init, ready, flush, mem_request, mem_access, mem_wait, mem_data, upd_cache, rd_cache);
signal s, sn : cache_state_t;
signal cache_busy : std_logic;
@@ -124,7 +124,6 @@ END COMPONENT;
signal tag_ram_data_rd : tag_ram_data_t;
signal tag_ram_addr_wr : unsigned(cache_index_width-1 downto 0);
signal tag_ram_data_wr : tag_ram_data_t;
signal tag_ram_re : std_logic;
signal tag_ram_we : std_logic;
signal ram_index_count : natural range 0 to 2**word_index_width-1;
@@ -236,7 +235,6 @@ cache_state:
cache_entry_in.tv_p <= (others => '0');
cache_entry_in.tag <= tag_index_reg;
cache_entry_in.valid <= '0';
sn <= s;
case s is
@@ -297,10 +295,12 @@ cache_state:
tag_ram_addr_wr <= cache_index_reg;
tag_ram_we <= '1';
cache_entry_in.valid <= '1';
sn <= rd_cache;
when rd_cache =>
data_ram_re <= '1';
was_miss <= '1';
sn <= ready;
sn <= ready;
when others =>
sn <= ready;
end case;