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git-svn-id: http://moon:8086/svn/vhdl/trunk@800 cc03376c-175c-47c8-b038-4cd826a8556b

lib/emac/src/piso.vhd

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+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+use std.textio.all; --  Imports the standard textio package.
+
+use work.utils_pkg.all; --  Imports the standard textio package.
+
+ENTITY piso IS
+	Generic
+	(
+		data_width_in	: natural := 32;
+		data_width_out	: natural := 8;
+		msb_first		: boolean := false
+	);
+	Port
+	(
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		din_rdy		: out STD_LOGIC;
+		din_vld		: in  STD_LOGIC;
+		din			: in  unsigned(data_width_in-1 downto 0);
+		dout_vld	: out STD_LOGIC;
+		dout		: out unsigned(data_width_out-1 downto 0)
+		
+	);
+END piso;
+
+ARCHITECTURE behavior OF piso IS
+
+	constant num_shifts		: natural := data_width_in/data_width_out;
+	signal pre_fin			: STD_LOGIC;
+	signal rdy				: STD_LOGIC;
+	signal shift_cnt_pipe	: unsigned(num_shifts-2 downto 0);
+	signal shift_pipe		: unsigned(data_width_in-1 downto 0);
+	
+--------------------------------------------------------------------------
+begin
+
+	pre_fin		<= shift_cnt_pipe(shift_cnt_pipe'left-1);
+
+	din_rdy		<= rdy;
+	dout		<= 		shift_pipe(shift_pipe'left downto shift_pipe'left-data_width_out+1) when msb_first
+				else	shift_pipe(data_width_out-1 downto 0);
+	
+--------------------------------------------------------------------------
+process(clk)
+begin
+	if rising_edge(clk) then
+		if rst = '1' then
+			shift_cnt_pipe	<= (others => '1');
+		elsif rdy = '1' then
+			if din_vld = '1' then
+				shift_cnt_pipe	<= (others => '0');
+				shift_pipe		<= din;
+			end if;
+		else
+			shift_cnt_pipe	<= shift_cnt_pipe(shift_cnt_pipe'left-1 downto 0)  & '1';
+			if (msb_first) then
+				shift_pipe		<= shift_pipe(shift_pipe'left-data_width_out downto 0) & (data_width_out-1 downto 0 => '0');
+			else
+				shift_pipe		<= (data_width_out-1 downto 0 => '0') & shift_pipe(shift_pipe'left downto data_width_out);
+			end if;
+			
+		end if;
+	end if;
+end process;
+
+--------------------------------------------------------------------------
+process(clk)
+begin
+	if rising_edge(clk) then
+		if rst = '1' then
+			rdy	<= '0';
+			dout_vld	<= '0';
+		elsif rdy = '1' then
+			if pre_fin = '1' then
+				dout_vld	<= '0';
+				if din_vld = '1' then
+					rdy	<= '0';
+					dout_vld	<= '1';
+				end if;
+			end if;
+		elsif pre_fin = '1' then
+			rdy	<= '1';
+		end if;
+	end if;
+end process;
+
+--------------------------------------------------------------------------
+end behavior;