jens 584ac47a8a - Bugfix: register bypass with same target register, used for unaligned loads (LWL, LWR), was incorrect. ...

Newlib's memcpy() (MIPS-optimized) uses this for unaligned copy.
  Consectutive load instructions without nops using same target register (which is legal) like
   lw $1, 0(mem)
   lwl $1, 1(mem)
  or
   lwl $1, 0(mem)
   lwr $1, 1(mem)
  or similar, lead to incorrect result. Now it's fixed.


git-svn-id: http://moon:8086/svn/vhdl/trunk@519 cc03376c-175c-47c8-b038-4cd826a8556b

2009-10-17 12:58:28 +00:00

Common

- Intital revision

2008-10-26 23:52:49 +00:00

lib

- Bugfix: register bypass with same target register, used for unaligned loads (LWL, LWR), was incorrect.

2009-10-17 12:58:28 +00:00

projects/mips_sys

- added addtional UART (4 UARTS in total)

2009-10-14 21:33:41 +00:00

S

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