- Removed linefifo and clockgen (=> frontend and top)
git-svn-id: http://moon:8086/svn/vhdl/trunk@80 cc03376c-175c-47c8-b038-4cd826a8556b
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@@ -27,9 +27,6 @@ entity vga_backend is
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Generic
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(
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sys_freq : integer := 100E6;
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fifo_depth : integer := 2048;
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fifo_almost_full_thresh : natural := 2000;
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fifo_almost_empty_thresh : natural := 48;
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tsvga : vga_timespec_t := ts_vga_800_600_72
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);
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Port
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@@ -37,19 +34,18 @@ entity vga_backend is
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-- System signals
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sys_rst : in std_logic;
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sys_clk : in std_logic;
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vga_ready : out std_logic;
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-- Buffered channel (Graphics plane)
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color_in : in color_t;
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color_fifo_we : in std_logic;
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color_fifo_full : out std_logic;
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color_fifo_afull : out std_logic;
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-- Color channels
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color_in : in color_array_t;
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color_op : in color_op_t;
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color_en : unsigned (VGA_NUM_CH-1 downto 0);
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-- Control signals
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ctrl_scan_en : in std_logic;
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-- Direct channel (Character plane)
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direct_color_in : in color_t;
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direct_draw_en : in std_logic;
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-- Status signals
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stat_vga_rdy : out std_logic;
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stat_scan : out std_logic;
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stat_hsync : out std_logic;
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stat_vsync : out std_logic;
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stat_hready : out std_logic;
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@@ -61,7 +57,9 @@ entity vga_backend is
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-- VGA domain signals
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vga_clk_out : out std_logic;
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vga_color_out : out color_t;
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vga_red : out unsigned(7 downto 0);
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vga_green : out unsigned(7 downto 0);
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vga_blue : out unsigned(7 downto 0);
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vga_blank_n : out std_logic;
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vga_sync_n : out std_logic;
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vga_hsync : out std_logic;
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@@ -72,10 +70,6 @@ end vga_backend;
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architecture Behavioral of vga_backend is
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signal scan_enable : std_logic;
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signal fifo_full : std_logic;
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signal fifo_empty : std_logic;
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signal fifo_almost_empty : std_logic;
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signal fifo_almost_full : std_logic;
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signal is_scan : std_logic;
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signal is_hscan : std_logic;
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signal is_vscan : std_logic;
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@@ -83,7 +77,6 @@ architecture Behavioral of vga_backend is
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signal vsync : std_logic;
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signal hready : std_logic;
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signal vready : std_logic;
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signal color : color_t;
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signal vga_clk : std_logic;
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signal dcm_locked : std_logic;
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signal rst : std_logic;
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@@ -91,9 +84,8 @@ architecture Behavioral of vga_backend is
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begin
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vga_clk_out <= vga_clk;
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vga_ready <= dcm_locked;
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inst_clkgen: entity work.clkgen
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inst_clkgen: entity work.clkgen
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GENERIC MAP
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(
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sys_freq => sys_freq,
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@@ -107,7 +99,7 @@ begin
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dcm_locked => dcm_locked
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);
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inst_vga_timing: entity work.vga_timing
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inst_vga_timing: entity work.vga_timing
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GENERIC MAP
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(
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tsvga => tsvga
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@@ -127,44 +119,21 @@ begin
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scan_rdy_v => vready
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);
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inst_linefifo: entity work.linefifo
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GENERIC MAP
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(
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depth => fifo_depth,
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almost_full_thresh => fifo_almost_full_thresh,
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almost_empty_thresh => fifo_almost_empty_thresh
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)
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PORT MAP(
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rst => sys_rst,
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clk_w => sys_clk,
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clk_r => vga_clk,
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we_w => color_fifo_we,
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re_r => is_scan,
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color_w => color_in,
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color_r => color,
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fifo_full => fifo_full,
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fifo_empty => fifo_empty,
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fifo_afull => fifo_almost_full,
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fifo_aempty => fifo_almost_empty
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);
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---------------------------------------------------------------------------------------------
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rst <= not dcm_locked;
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stat_vga_rdy <= dcm_locked;
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stat_hsync <= hsync;
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stat_vsync <= vsync;
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stat_hscan <= is_hscan;
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stat_vscan <= is_vscan;
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stat_hready <= hready;
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stat_vready <= vready;
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stat_scan <= is_scan;
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vga_blank_n <= '1';
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vga_sync_n <= '0';
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is_scan <= is_hscan and is_vscan and scan_enable;
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color_fifo_full <= fifo_full;
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color_fifo_afull <= fifo_almost_full;
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---------------------------------------------------------------------------------------------
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proc_vga_start:
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process (rst, vga_clk)
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@@ -173,7 +142,7 @@ begin
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scan_enable <= '0';
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elsif rising_edge(vga_clk) then
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if vsync = '1' then
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if fifo_empty = '0' then
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if ctrl_scan_en = '1' then
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scan_enable <= '1';
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else
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scan_enable <= '0';
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@@ -185,17 +154,23 @@ begin
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proc_vga_color_out:
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process (rst, vga_clk)
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variable do_scan : std_logic;
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variable color : color_t;
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begin
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if rst = '1' then
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do_scan := '0';
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elsif rising_edge(vga_clk) then
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vga_color_out <= (X"00", X"00", X"00");
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vga_red <= X"00";
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vga_green <= X"00";
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vga_blue <= X"00";
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if do_scan = '1' then
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if direct_draw_en = '1' then
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vga_color_out <= direct_color_in;
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else
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vga_color_out <= color;
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end if;
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for i in 0 to VGA_NUM_CH-1 loop
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color := color_in(i);
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if color_en(i) = '1' then
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vga_red <= color(r); -- ToDo: color_op over channels
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vga_green <= color(g); -- ToDo: color_op over channels
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vga_blue <= color(b); -- ToDo: color_op over channels
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end if;
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end loop;
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end if;
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do_scan := is_scan;
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end if;
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