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- minor bugfix (width mismatch)

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git-svn-id: http://moon:8086/svn/vhdl/trunk@600 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-11-04 19:26:53 +00:00
parent 3065e22f8f
commit c33943f991
1 changed files with 2 additions and 2 deletions
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lib/misc/async_port_wb.vhd
+2 -2
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@@ -1,5 +1,5 @@
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.12 2009-11-02 10:29:23 Jens Exp $
-- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.13 2009-11-04 19:26:53 Jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
@@ -251,7 +251,7 @@ architecture Behavioral of async_port_wb is
SEL_I_r <= (others => '0');
elsif en = '1' and rdy = '1' then
async_a <= ADDR_I(addr_width-1 downto 0);
async_be <= (byte_sel_width-1 downto 0 => not async_timespec.pol_be) xor ((byte_sel_width-1 downto 0 => as.cs) and SEL_I);
async_be <= (byte_sel_width-1 downto 0 => not async_timespec.pol_be) xor ((byte_sel_width-1 downto 0 => as.cs) and SEL_I(byte_sel_width-1 downto 0));
SEL_I_r <= SEL_I(byte_sel_width-1 downto 0);
if is_idle = '1' then
ADDR_I_r <= ADDR_I(addr_width-1 downto 0);