- removed ram_wb
Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@329 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -18,12 +18,10 @@ vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd"
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vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
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vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd"
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vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
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vhdl work "../../../../lib/misc/dpram_2w2r_virtex4.vhd"
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vhdl work "../../../../lib/FIFO/src/fifo_sync.vhd"
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vhdl work "../../../../lib/FIFO/src/fifo_async_ctrl.vhd"
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vhdl work "../../../../lib/ac97_ctrl/src/core/ac_out.vhd"
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vhdl work "../../../../lib/ac97_ctrl/src/core/ac_in.vhd"
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vhdl work "../../src/ram_ld.vhd"
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vhdl work "../../src/bootloader.ROM_ld.vhd"
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vhdl work "../../../../lib/VGA_ctrl/src/vga_backend.vhd"
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vhdl work "../../../../lib/VGA_ctrl/src/char_gen.vhd"
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@@ -38,7 +36,6 @@ vhdl work "../../../../lib/VGA_ctrl/src/vga_frontend64.vhd"
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vhdl work "../../../../lib/uart/uart_wb.vhd"
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vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd"
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vhdl work "../../../../lib/misc/rom_wb.vhd"
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vhdl work "../../../../lib/misc/ram_wb.vhd"
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vhdl work "../../../../lib/misc/lcd_port.vhd"
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vhdl work "../../../../lib/misc/gpio_wb.vhd"
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vhdl work "../../../../lib/misc/clockgen_virtex4.vhd"
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@@ -18,12 +18,10 @@ vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl.vhd"
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vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_cmd.vhd"
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vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\reset_virtex4.vhd"
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vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\ddr_phy_virtex4.vhd"
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vhdl work "W:\vhdl\lib\misc\dpram_2w2r_virtex4.vhd"
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vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync.vhd"
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vhdl work "W:\vhdl\lib\FIFO\src\fifo_async_ctrl.vhd"
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vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac_out.vhd"
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vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac_in.vhd"
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vhdl work "W:\vhdl\projects\mips_sys\src\ram_ld.vhd"
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vhdl work "W:\vhdl\projects\mips_sys\src\bootloader.ROM_ld.vhd"
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vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_backend.vhd"
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vhdl work "W:\vhdl\lib\VGA_ctrl\src\char_gen.vhd"
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@@ -38,7 +36,6 @@ vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_frontend64.vhd"
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vhdl work "W:\vhdl\lib\uart\uart_wb.vhd"
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vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_frontend64_wb.vhd"
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vhdl work "W:\vhdl\lib\misc\rom_wb.vhd"
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vhdl work "W:\vhdl\lib\misc\ram_wb.vhd"
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vhdl work "W:\vhdl\lib\misc\lcd_port.vhd"
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vhdl work "W:\vhdl\lib\misc\gpio_wb.vhd"
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vhdl work "W:\vhdl\lib\misc\clockgen_virtex4.vhd"
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@@ -38,9 +38,7 @@ vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_dcache.vhd"
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vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_icache.vhd"
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vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_biu.vhd"
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vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_top.vhd"
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vcom -explicit -93 "../src/ram_sim.vhd"
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vcom -explicit -93 "../src/bootloader.ROM.vhd"
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vcom -explicit -93 "../../../lib/misc/ram_wb.vhd"
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vcom -explicit -93 "../../../lib/misc/rom_wb.vhd"
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# VGA
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@@ -59,19 +59,10 @@ add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/sync_tx
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/sync_status
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add wave -noupdate -format Literal /tb_mips_sys/uut/inst_ac97_wb/request
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_data_start
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/rx_data_start
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_ac97_wb/ac97_stat
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/int_en_frame_sync
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/int_en_rx
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/int_en_tx
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/rx_fifo_re
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/rx_fifo_we
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/rx_fifo_full
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/rx_fifo_empty
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/rx_fifo_almost_full
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/rx_fifo_almost_empty
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_ac97_wb/rx_fifo_din
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_ac97_wb/rx_fifo_dout
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_re
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_we
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_full
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@@ -96,7 +87,6 @@ add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o_cpu
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add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o_cpu
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add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i_cpu
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add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i_cpu
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add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/s
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add wave -noupdate -divider {VGA Master}
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add wave -noupdate -format Logic /tb_mips_sys/uut/clk
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_i
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@@ -111,47 +101,6 @@ add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i_vga
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add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i_vga
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add wave -noupdate -divider BUI
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add wave -noupdate -format Logic /tb_mips_sys/uut/clk
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cyc_o_icache
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cyc_o_dcache
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cyc_o_dmem_rd
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cyc_o_dmem_wr
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/stb_o_icache
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/stb_o_dcache
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/stb_o_dmem_rd
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/stb_o_dmem_wr
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add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/s
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/dcached
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/uncached_access
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_rdy
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_we
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_en
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_addr
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add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/bus_timeout_cnt
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/bus_timeout
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_re
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_we
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_full
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_empty
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_we_out
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add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_sel_out
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_data_out
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_addr_out
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_we_in
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add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_sel_in
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_data_in
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_addr_in
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/write_fifo_din
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/write_fifo_dout
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/write_fifo_re
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/write_fifo_we
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/write_fifo_full
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/write_fifo_empty
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/write_busy
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_rdy
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_we
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_en
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_addr
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add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/s
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add wave -noupdate -format Literal -label .op -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage.op
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add wave -noupdate -divider USB
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add wave -noupdate -format Logic /tb_mips_sys/uut/clk
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@@ -239,7 +188,6 @@ add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ru
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/cpu_rst
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add wave -noupdate -format Logic /tb_mips_sys/uut/clk
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add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_busy
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add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
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add wave -noupdate -format Logic /tb_mips_sys/uut/clk
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add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/mem_stage
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@@ -254,20 +202,8 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/epc
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add wave -noupdate -divider {CPU DMEM}
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add wave -noupdate -format Logic /tb_mips_sys/uut/clk
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_busy
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_rdy
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_en
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_we
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add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_be
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_dout
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_din
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_addr
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add wave -noupdate -divider {CPU IMEM}
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add wave -noupdate -format Logic /tb_mips_sys/uut/clk
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_imem_en
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_imem_addr
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_imem_din
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_imem_rdy
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add wave -noupdate -divider {User ROM}
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add wave -noupdate -divider UUT
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add wave -noupdate -format Logic /tb_mips_sys/uut/clk
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@@ -292,56 +228,8 @@ add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/cp
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/run_en
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add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/pc
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add wave -noupdate -format Logic -label .branch -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage.ctrl.branch
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add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/s
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add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/s
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/cpu_en
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/cpu_addr
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/cpu_dout
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/cache_busy
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/cache_miss
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add wave -noupdate -format Literal -label tag_ram -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/inst_tag_ram/ram
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add wave -noupdate -format Literal -label data_ram -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/inst_data_ram/ram
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/data_ram_addr_rd
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/data_ram_addr_wr
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/data_ram_we
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/ram_index_count
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/mem_index_count
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/data_write
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add wave -noupdate -divider D-Cache
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add wave -noupdate -format Logic /tb_mips_sys/uut/clk
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_en
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_we
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add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_we
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_addr
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_din
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_dout
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_busy
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_we_reg
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add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/s
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add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cache_busy
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cache_hit
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_reg_en
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/was_miss
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/data_write
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/dcached
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/mem_index_count
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/word_index_reg
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_word_index
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/instant_raw
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_dram_addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_dram_dout
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_hit_we
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_dram_we
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/ctrl_dram_en
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/ctrl_dram_addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/ctrl_dram_din
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/ctrl_dram_we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/tram_addr_rd
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/tram_dout
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/tram_addr_wr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/tram_din
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/tram_re
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/tram_we
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 2} {23579127600 ps} 0} {{Cursor 100} {5544988254 ps} 0}
|
||||
configure wave -namecolwidth 187
|
||||
@@ -357,4 +245,4 @@ configure wave -gridperiod 100
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 1
|
||||
update
|
||||
WaveRestoreZoom {0 ps} {37535226330 ps}
|
||||
WaveRestoreZoom {381220785 ps} {2601775328 ps}
|
||||
|
||||
@@ -32,7 +32,6 @@ use UNISIM.vcomponents.all;
|
||||
|
||||
library work;
|
||||
use work.mips_types.all;
|
||||
--use work.fifo_ctrl_pkg.all;
|
||||
use work.sdram_config.all;
|
||||
use work.sdram_types.all;
|
||||
use work.vga_types.all;
|
||||
@@ -160,24 +159,6 @@ ARCHITECTURE behavior OF mips_sys IS
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT ram_wb
|
||||
PORT
|
||||
(
|
||||
CLK_I : in STD_LOGIC;
|
||||
RST_I : in STD_LOGIC;
|
||||
CYC_I : in STD_LOGIC;
|
||||
STB_I : in STD_LOGIC;
|
||||
SEL_I : in unsigned(3 downto 0);
|
||||
WE_I : in STD_LOGIC;
|
||||
ACK_O : out STD_LOGIC;
|
||||
SRDY_O : out STD_LOGIC;
|
||||
MRDY_I : in STD_LOGIC;
|
||||
ADDR_I : in unsigned(31 downto 0);
|
||||
DAT_I : in unsigned(31 downto 0);
|
||||
DAT_O : out unsigned(31 downto 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT lcd_port
|
||||
PORT
|
||||
(
|
||||
@@ -393,11 +374,6 @@ ARCHITECTURE behavior OF mips_sys IS
|
||||
signal SDAT_I_sdram : unsigned(63 downto 0);
|
||||
signal SEL_I_sdram : unsigned(7 downto 0);
|
||||
|
||||
signal CYC_I_ram : std_logic;
|
||||
signal ACK_O_ram : std_logic;
|
||||
signal SRDY_O_ram : std_logic;
|
||||
signal SDAT_O_ram : unsigned(31 downto 0);
|
||||
|
||||
signal CYC_I_rom : std_logic;
|
||||
signal ACK_O_rom : std_logic;
|
||||
signal SRDY_O_rom : std_logic;
|
||||
@@ -440,7 +416,7 @@ ARCHITECTURE behavior OF mips_sys IS
|
||||
-- attribute rom_style of cpu_cpu_write_fifo_dout: signal is "DISTRIBUTED";
|
||||
-- attribute rom_style of cpu_read_fifo_dout: signal is "DISTRIBUTED";
|
||||
|
||||
type mem_area_t is (mem_dead, mem_flash, mem_usb, mem_rom, mem_ram, mem_gpio, mem_uart, mem_sdram, mem_vga, mem_ac97);
|
||||
type mem_area_t is (mem_dead, mem_flash, mem_usb, mem_rom, mem_gpio, mem_uart, mem_sdram, mem_vga, mem_ac97);
|
||||
signal mem_area : mem_area_t;
|
||||
|
||||
BEGIN
|
||||
@@ -532,8 +508,7 @@ mem_mux:
|
||||
end if;
|
||||
elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then
|
||||
mem_area <= mem_rom;
|
||||
elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '1') then
|
||||
mem_area <= mem_ram;
|
||||
-- elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '1') then
|
||||
elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then
|
||||
mem_area <= mem_sdram;
|
||||
end if;
|
||||
@@ -548,7 +523,6 @@ signal_mux:
|
||||
CYC_I_flash <= '0';
|
||||
CYC_I_usb <= '0';
|
||||
CYC_I_rom <= '0';
|
||||
CYC_I_ram <= '0';
|
||||
CYC_I_sdram <= '0';
|
||||
CYC_I_vga <= '0';
|
||||
CYC_I_ac97 <= '0';
|
||||
@@ -570,9 +544,6 @@ signal_mux:
|
||||
when mem_rom =>
|
||||
CYC_I_rom <= CYC_O;
|
||||
|
||||
when mem_ram =>
|
||||
CYC_I_ram <= CYC_O;
|
||||
|
||||
when mem_sdram =>
|
||||
CYC_I_sdram <= CYC_O;
|
||||
|
||||
@@ -589,10 +560,9 @@ signal_mux:
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
SRDY_I <= SRDY_O_flash or SRDY_O_usb or SRDY_O_sdram or SRDY_O_ram or SRDY_O_rom or SRDY_O_uart or SRDY_O_gpio or SRDY_O_vga or SRDY_O_ac97;
|
||||
ACK_I <= ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_ram or ACK_O_rom or ACK_O_uart or ACK_O_gpio or ACK_O_vga or ACK_O_ac97;
|
||||
SRDY_I <= SRDY_O_flash or SRDY_O_usb or SRDY_O_sdram or SRDY_O_rom or SRDY_O_uart or SRDY_O_gpio or SRDY_O_vga or SRDY_O_ac97;
|
||||
ACK_I <= ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_rom or ACK_O_uart or ACK_O_gpio or ACK_O_vga or ACK_O_ac97;
|
||||
MDAT_I <= SDAT_O_sdram(31 downto 0) when CYC_I_sdram = '1' else
|
||||
SDAT_O_ram when CYC_I_ram = '1' else
|
||||
SDAT_O_rom when CYC_I_rom = '1' else
|
||||
SDAT_O_flash when CYC_I_flash = '1' else
|
||||
SDAT_O_usb when CYC_I_usb = '1' else
|
||||
@@ -621,23 +591,6 @@ inst_mips_top: mips_top
|
||||
INT => INT
|
||||
);
|
||||
|
||||
inst_ram_wb : ram_wb
|
||||
PORT MAP
|
||||
(
|
||||
CLK_I => clk,
|
||||
RST_I => rst,
|
||||
CYC_I => CYC_I_ram,
|
||||
STB_I => STB_O,
|
||||
SEL_I => SEL_O,
|
||||
WE_I => WE_O,
|
||||
ACK_O => ACK_O_ram,
|
||||
SRDY_O => SRDY_O_ram,
|
||||
MRDY_I => MRDY_O,
|
||||
ADDR_I => ADDR_O,
|
||||
DAT_I => MDAT_O,
|
||||
DAT_O => SDAT_O_ram
|
||||
);
|
||||
|
||||
inst_rom_wb : rom_wb
|
||||
PORT MAP
|
||||
(
|
||||
|
||||
@@ -170,24 +170,6 @@ ARCHITECTURE behavior OF mips_sys IS
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT ram_wb
|
||||
PORT
|
||||
(
|
||||
CLK_I : in STD_LOGIC;
|
||||
RST_I : in STD_LOGIC;
|
||||
CYC_I : in STD_LOGIC;
|
||||
STB_I : in STD_LOGIC;
|
||||
SEL_I : in unsigned(3 downto 0);
|
||||
WE_I : in STD_LOGIC;
|
||||
ACK_O : out STD_LOGIC;
|
||||
SRDY_O : out STD_LOGIC;
|
||||
MRDY_I : in STD_LOGIC;
|
||||
ADDR_I : in unsigned(31 downto 0);
|
||||
DAT_I : in unsigned(31 downto 0);
|
||||
DAT_O : out unsigned(31 downto 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT lcd_port
|
||||
PORT
|
||||
(
|
||||
@@ -450,11 +432,6 @@ ARCHITECTURE behavior OF mips_sys IS
|
||||
signal SDAT_I_sdram : unsigned(63 downto 0);
|
||||
signal SEL_I_sdram : unsigned(7 downto 0);
|
||||
|
||||
signal CYC_I_ram : std_logic;
|
||||
signal ACK_O_ram : std_logic;
|
||||
signal SRDY_O_ram : std_logic;
|
||||
signal SDAT_O_ram : unsigned(31 downto 0);
|
||||
|
||||
signal CYC_I_rom : std_logic;
|
||||
signal ACK_O_rom : std_logic;
|
||||
signal SRDY_O_rom : std_logic;
|
||||
@@ -503,7 +480,7 @@ ARCHITECTURE behavior OF mips_sys IS
|
||||
-- attribute rom_style of cpu_cpu_write_fifo_dout: signal is "DISTRIBUTED";
|
||||
-- attribute rom_style of cpu_read_fifo_dout: signal is "DISTRIBUTED";
|
||||
|
||||
type mem_area_t is (mem_dead, mem_flash, mem_ssram, mem_usb, mem_rom, mem_ram, mem_gpio, mem_uart, mem_sdram, mem_vga, mem_ac97);
|
||||
type mem_area_t is (mem_dead, mem_flash, mem_ssram, mem_usb, mem_rom, mem_gpio, mem_uart, mem_sdram, mem_vga, mem_ac97);
|
||||
signal mem_area : mem_area_t;
|
||||
|
||||
BEGIN
|
||||
@@ -623,9 +600,8 @@ mem_mux:
|
||||
end if;
|
||||
elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then
|
||||
mem_area <= mem_rom;
|
||||
elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '1') then
|
||||
mem_area <= mem_ram;
|
||||
-- mem_area <= mem_ssram;
|
||||
-- elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '1') then
|
||||
-- kernel sram
|
||||
elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then
|
||||
mem_area <= mem_sdram;
|
||||
end if;
|
||||
@@ -640,7 +616,6 @@ signal_mux:
|
||||
CYC_I_flash <= '0';
|
||||
CYC_I_usb <= '0';
|
||||
CYC_I_rom <= '0';
|
||||
CYC_I_ram <= '0';
|
||||
CYC_I_sdram <= '0';
|
||||
CYC_I_vga <= '0';
|
||||
CYC_I_ssram <= '0';
|
||||
@@ -663,9 +638,6 @@ signal_mux:
|
||||
when mem_rom =>
|
||||
CYC_I_rom <= CYC_O;
|
||||
|
||||
when mem_ram =>
|
||||
CYC_I_ram <= CYC_O;
|
||||
|
||||
when mem_sdram =>
|
||||
CYC_I_sdram <= CYC_O;
|
||||
|
||||
@@ -685,11 +657,10 @@ signal_mux:
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
SRDY_I <= SRDY_O_flash or SRDY_O_ssram or SRDY_O_usb or SRDY_O_sdram or SRDY_O_ram or SRDY_O_rom or SRDY_O_uart or SRDY_O_gpio or SRDY_O_vga or SRDY_O_ac97;
|
||||
ACK_I <= ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_ssram or ACK_O_ram or ACK_O_rom or ACK_O_uart or ACK_O_gpio or ACK_O_vga or ACK_O_ac97;
|
||||
SRDY_I <= SRDY_O_flash or SRDY_O_ssram or SRDY_O_usb or SRDY_O_sdram or SRDY_O_rom or SRDY_O_uart or SRDY_O_gpio or SRDY_O_vga or SRDY_O_ac97;
|
||||
ACK_I <= ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_ssram or ACK_O_rom or ACK_O_uart or ACK_O_gpio or ACK_O_vga or ACK_O_ac97;
|
||||
MDAT_I <= SDAT_O_ssram when CYC_I_ssram = '1' else
|
||||
SDAT_O_sdram(31 downto 0) when CYC_I_sdram = '1' else
|
||||
SDAT_O_ram when CYC_I_ram = '1' else
|
||||
SDAT_O_rom when CYC_I_rom = '1' else
|
||||
SDAT_O_flash when CYC_I_flash = '1' else
|
||||
SDAT_O_usb when CYC_I_usb = '1' else
|
||||
@@ -718,23 +689,6 @@ inst_mips_top: mips_top
|
||||
INT => INT
|
||||
);
|
||||
|
||||
inst_ram_wb : ram_wb
|
||||
PORT MAP
|
||||
(
|
||||
CLK_I => clk,
|
||||
RST_I => rst,
|
||||
CYC_I => CYC_I_ram,
|
||||
STB_I => STB_O,
|
||||
SEL_I => SEL_O,
|
||||
WE_I => WE_O,
|
||||
ACK_O => ACK_O_ram,
|
||||
SRDY_O => SRDY_O_ram,
|
||||
MRDY_I => MRDY_O,
|
||||
ADDR_I => ADDR_O,
|
||||
DAT_I => MDAT_O,
|
||||
DAT_O => SDAT_O_ram
|
||||
);
|
||||
|
||||
inst_rom_wb : rom_wb
|
||||
PORT MAP
|
||||
(
|
||||
|
||||
Reference in New Issue
Block a user