- removed ram_wb

Committed on the Free edition of March Hare Software CVSNT Server.
Upgrade to CVS Suite for more features and support:
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git-svn-id: http://moon:8086/svn/vhdl/trunk@329 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
2009-02-08 18:20:42 +00:00
parent fed261182c
commit 6ff7294c1e
6 changed files with 10 additions and 223 deletions
@@ -18,12 +18,10 @@ vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
vhdl work "../../../../lib/misc/dpram_2w2r_virtex4.vhd"
vhdl work "../../../../lib/FIFO/src/fifo_sync.vhd"
vhdl work "../../../../lib/FIFO/src/fifo_async_ctrl.vhd"
vhdl work "../../../../lib/ac97_ctrl/src/core/ac_out.vhd"
vhdl work "../../../../lib/ac97_ctrl/src/core/ac_in.vhd"
vhdl work "../../src/ram_ld.vhd"
vhdl work "../../src/bootloader.ROM_ld.vhd"
vhdl work "../../../../lib/VGA_ctrl/src/vga_backend.vhd"
vhdl work "../../../../lib/VGA_ctrl/src/char_gen.vhd"
@@ -38,7 +36,6 @@ vhdl work "../../../../lib/VGA_ctrl/src/vga_frontend64.vhd"
vhdl work "../../../../lib/uart/uart_wb.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd"
vhdl work "../../../../lib/misc/rom_wb.vhd"
vhdl work "../../../../lib/misc/ram_wb.vhd"
vhdl work "../../../../lib/misc/lcd_port.vhd"
vhdl work "../../../../lib/misc/gpio_wb.vhd"
vhdl work "../../../../lib/misc/clockgen_virtex4.vhd"
@@ -18,12 +18,10 @@ vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_cmd.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\reset_virtex4.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\ddr_phy_virtex4.vhd"
vhdl work "W:\vhdl\lib\misc\dpram_2w2r_virtex4.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\fifo_async_ctrl.vhd"
vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac_out.vhd"
vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac_in.vhd"
vhdl work "W:\vhdl\projects\mips_sys\src\ram_ld.vhd"
vhdl work "W:\vhdl\projects\mips_sys\src\bootloader.ROM_ld.vhd"
vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_backend.vhd"
vhdl work "W:\vhdl\lib\VGA_ctrl\src\char_gen.vhd"
@@ -38,7 +36,6 @@ vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_frontend64.vhd"
vhdl work "W:\vhdl\lib\uart\uart_wb.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_frontend64_wb.vhd"
vhdl work "W:\vhdl\lib\misc\rom_wb.vhd"
vhdl work "W:\vhdl\lib\misc\ram_wb.vhd"
vhdl work "W:\vhdl\lib\misc\lcd_port.vhd"
vhdl work "W:\vhdl\lib\misc\gpio_wb.vhd"
vhdl work "W:\vhdl\lib\misc\clockgen_virtex4.vhd"
-2
View File
@@ -38,9 +38,7 @@ vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_dcache.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_icache.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_biu.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_top.vhd"
vcom -explicit -93 "../src/ram_sim.vhd"
vcom -explicit -93 "../src/bootloader.ROM.vhd"
vcom -explicit -93 "../../../lib/misc/ram_wb.vhd"
vcom -explicit -93 "../../../lib/misc/rom_wb.vhd"
# VGA
+1 -113
View File
@@ -59,19 +59,10 @@ add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/sync_tx
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/sync_status
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_ac97_wb/request
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_data_start
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/rx_data_start
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_ac97_wb/ac97_stat
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/int_en_frame_sync
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/int_en_rx
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/int_en_tx
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/rx_fifo_re
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/rx_fifo_we
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/rx_fifo_full
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/rx_fifo_empty
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/rx_fifo_almost_full
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/rx_fifo_almost_empty
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_ac97_wb/rx_fifo_din
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_ac97_wb/rx_fifo_dout
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_re
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_we
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_full
@@ -96,7 +87,6 @@ add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o_cpu
add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o_cpu
add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i_cpu
add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i_cpu
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/s
add wave -noupdate -divider {VGA Master}
add wave -noupdate -format Logic /tb_mips_sys/uut/clk
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_i
@@ -111,47 +101,6 @@ add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i_vga
add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i_vga
add wave -noupdate -divider BUI
add wave -noupdate -format Logic /tb_mips_sys/uut/clk
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cyc_o_icache
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cyc_o_dcache
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cyc_o_dmem_rd
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cyc_o_dmem_wr
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/stb_o_icache
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/stb_o_dcache
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/stb_o_dmem_rd
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/stb_o_dmem_wr
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/s
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/dcached
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/uncached_access
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_rdy
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_we
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_en
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_addr
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/bus_timeout_cnt
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/bus_timeout
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_re
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_we
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_full
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_empty
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_we_out
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_sel_out
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_data_out
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_addr_out
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_we_in
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_sel_in
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_data_in
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_addr_in
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/write_fifo_din
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/write_fifo_dout
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/write_fifo_re
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/write_fifo_we
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/write_fifo_full
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/write_fifo_empty
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/write_busy
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_rdy
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_we
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_en
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_addr
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/s
add wave -noupdate -format Literal -label .op -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage.op
add wave -noupdate -divider USB
add wave -noupdate -format Logic /tb_mips_sys/uut/clk
@@ -239,7 +188,6 @@ add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ru
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/cpu_rst
add wave -noupdate -format Logic /tb_mips_sys/uut/clk
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_busy
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
add wave -noupdate -format Logic /tb_mips_sys/uut/clk
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/mem_stage
@@ -254,20 +202,8 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/epc
add wave -noupdate -divider {CPU DMEM}
add wave -noupdate -format Logic /tb_mips_sys/uut/clk
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_busy
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_rdy
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_we
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_be
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_dout
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_din
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_addr
add wave -noupdate -divider {CPU IMEM}
add wave -noupdate -format Logic /tb_mips_sys/uut/clk
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_imem_en
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_imem_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_imem_din
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_imem_rdy
add wave -noupdate -divider {User ROM}
add wave -noupdate -divider UUT
add wave -noupdate -format Logic /tb_mips_sys/uut/clk
@@ -292,56 +228,8 @@ add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/cp
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/run_en
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/pc
add wave -noupdate -format Logic -label .branch -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage.ctrl.branch
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/s
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/s
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/cpu_en
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/cpu_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/cpu_dout
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/cache_busy
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/cache_miss
add wave -noupdate -format Literal -label tag_ram -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/inst_tag_ram/ram
add wave -noupdate -format Literal -label data_ram -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/inst_data_ram/ram
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/data_ram_addr_rd
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/data_ram_addr_wr
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/data_ram_we
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/ram_index_count
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/mem_index_count
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/data_write
add wave -noupdate -divider D-Cache
add wave -noupdate -format Logic /tb_mips_sys/uut/clk
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_we
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_we
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_din
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_dout
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_busy
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_we_reg
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/s
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cache_busy
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cache_hit
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_reg_en
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/was_miss
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/data_write
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/dcached
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/mem_index_count
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/word_index_reg
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_word_index
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/instant_raw
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_dram_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_dram_dout
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_hit_we
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_dram_we
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/ctrl_dram_en
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/ctrl_dram_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/ctrl_dram_din
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/ctrl_dram_we
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/tram_addr_rd
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/tram_dout
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/tram_addr_wr
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/tram_din
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/tram_re
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/tram_we
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 2} {23579127600 ps} 0} {{Cursor 100} {5544988254 ps} 0}
configure wave -namecolwidth 187
@@ -357,4 +245,4 @@ configure wave -gridperiod 100
configure wave -griddelta 40
configure wave -timeline 1
update
WaveRestoreZoom {0 ps} {37535226330 ps}
WaveRestoreZoom {381220785 ps} {2601775328 ps}
+4 -51
View File
@@ -32,7 +32,6 @@ use UNISIM.vcomponents.all;
library work;
use work.mips_types.all;
--use work.fifo_ctrl_pkg.all;
use work.sdram_config.all;
use work.sdram_types.all;
use work.vga_types.all;
@@ -160,24 +159,6 @@ ARCHITECTURE behavior OF mips_sys IS
);
END COMPONENT;
COMPONENT ram_wb
PORT
(
CLK_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
SEL_I : in unsigned(3 downto 0);
WE_I : in STD_LOGIC;
ACK_O : out STD_LOGIC;
SRDY_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
ADDR_I : in unsigned(31 downto 0);
DAT_I : in unsigned(31 downto 0);
DAT_O : out unsigned(31 downto 0)
);
END COMPONENT;
COMPONENT lcd_port
PORT
(
@@ -393,11 +374,6 @@ ARCHITECTURE behavior OF mips_sys IS
signal SDAT_I_sdram : unsigned(63 downto 0);
signal SEL_I_sdram : unsigned(7 downto 0);
signal CYC_I_ram : std_logic;
signal ACK_O_ram : std_logic;
signal SRDY_O_ram : std_logic;
signal SDAT_O_ram : unsigned(31 downto 0);
signal CYC_I_rom : std_logic;
signal ACK_O_rom : std_logic;
signal SRDY_O_rom : std_logic;
@@ -440,7 +416,7 @@ ARCHITECTURE behavior OF mips_sys IS
-- attribute rom_style of cpu_cpu_write_fifo_dout: signal is "DISTRIBUTED";
-- attribute rom_style of cpu_read_fifo_dout: signal is "DISTRIBUTED";
type mem_area_t is (mem_dead, mem_flash, mem_usb, mem_rom, mem_ram, mem_gpio, mem_uart, mem_sdram, mem_vga, mem_ac97);
type mem_area_t is (mem_dead, mem_flash, mem_usb, mem_rom, mem_gpio, mem_uart, mem_sdram, mem_vga, mem_ac97);
signal mem_area : mem_area_t;
BEGIN
@@ -532,8 +508,7 @@ mem_mux:
end if;
elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then
mem_area <= mem_rom;
elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '1') then
mem_area <= mem_ram;
-- elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '1') then
elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then
mem_area <= mem_sdram;
end if;
@@ -548,7 +523,6 @@ signal_mux:
CYC_I_flash <= '0';
CYC_I_usb <= '0';
CYC_I_rom <= '0';
CYC_I_ram <= '0';
CYC_I_sdram <= '0';
CYC_I_vga <= '0';
CYC_I_ac97 <= '0';
@@ -570,9 +544,6 @@ signal_mux:
when mem_rom =>
CYC_I_rom <= CYC_O;
when mem_ram =>
CYC_I_ram <= CYC_O;
when mem_sdram =>
CYC_I_sdram <= CYC_O;
@@ -589,10 +560,9 @@ signal_mux:
end process;
------------------------------------------------------------------
SRDY_I <= SRDY_O_flash or SRDY_O_usb or SRDY_O_sdram or SRDY_O_ram or SRDY_O_rom or SRDY_O_uart or SRDY_O_gpio or SRDY_O_vga or SRDY_O_ac97;
ACK_I <= ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_ram or ACK_O_rom or ACK_O_uart or ACK_O_gpio or ACK_O_vga or ACK_O_ac97;
SRDY_I <= SRDY_O_flash or SRDY_O_usb or SRDY_O_sdram or SRDY_O_rom or SRDY_O_uart or SRDY_O_gpio or SRDY_O_vga or SRDY_O_ac97;
ACK_I <= ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_rom or ACK_O_uart or ACK_O_gpio or ACK_O_vga or ACK_O_ac97;
MDAT_I <= SDAT_O_sdram(31 downto 0) when CYC_I_sdram = '1' else
SDAT_O_ram when CYC_I_ram = '1' else
SDAT_O_rom when CYC_I_rom = '1' else
SDAT_O_flash when CYC_I_flash = '1' else
SDAT_O_usb when CYC_I_usb = '1' else
@@ -621,23 +591,6 @@ inst_mips_top: mips_top
INT => INT
);
inst_ram_wb : ram_wb
PORT MAP
(
CLK_I => clk,
RST_I => rst,
CYC_I => CYC_I_ram,
STB_I => STB_O,
SEL_I => SEL_O,
WE_I => WE_O,
ACK_O => ACK_O_ram,
SRDY_O => SRDY_O_ram,
MRDY_I => MRDY_O,
ADDR_I => ADDR_O,
DAT_I => MDAT_O,
DAT_O => SDAT_O_ram
);
inst_rom_wb : rom_wb
PORT MAP
(
+5 -51
View File
@@ -170,24 +170,6 @@ ARCHITECTURE behavior OF mips_sys IS
);
END COMPONENT;
COMPONENT ram_wb
PORT
(
CLK_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
SEL_I : in unsigned(3 downto 0);
WE_I : in STD_LOGIC;
ACK_O : out STD_LOGIC;
SRDY_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC;
ADDR_I : in unsigned(31 downto 0);
DAT_I : in unsigned(31 downto 0);
DAT_O : out unsigned(31 downto 0)
);
END COMPONENT;
COMPONENT lcd_port
PORT
(
@@ -450,11 +432,6 @@ ARCHITECTURE behavior OF mips_sys IS
signal SDAT_I_sdram : unsigned(63 downto 0);
signal SEL_I_sdram : unsigned(7 downto 0);
signal CYC_I_ram : std_logic;
signal ACK_O_ram : std_logic;
signal SRDY_O_ram : std_logic;
signal SDAT_O_ram : unsigned(31 downto 0);
signal CYC_I_rom : std_logic;
signal ACK_O_rom : std_logic;
signal SRDY_O_rom : std_logic;
@@ -503,7 +480,7 @@ ARCHITECTURE behavior OF mips_sys IS
-- attribute rom_style of cpu_cpu_write_fifo_dout: signal is "DISTRIBUTED";
-- attribute rom_style of cpu_read_fifo_dout: signal is "DISTRIBUTED";
type mem_area_t is (mem_dead, mem_flash, mem_ssram, mem_usb, mem_rom, mem_ram, mem_gpio, mem_uart, mem_sdram, mem_vga, mem_ac97);
type mem_area_t is (mem_dead, mem_flash, mem_ssram, mem_usb, mem_rom, mem_gpio, mem_uart, mem_sdram, mem_vga, mem_ac97);
signal mem_area : mem_area_t;
BEGIN
@@ -623,9 +600,8 @@ mem_mux:
end if;
elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then
mem_area <= mem_rom;
elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '1') then
mem_area <= mem_ram;
-- mem_area <= mem_ssram;
-- elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '1') then
-- kernel sram
elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then
mem_area <= mem_sdram;
end if;
@@ -640,7 +616,6 @@ signal_mux:
CYC_I_flash <= '0';
CYC_I_usb <= '0';
CYC_I_rom <= '0';
CYC_I_ram <= '0';
CYC_I_sdram <= '0';
CYC_I_vga <= '0';
CYC_I_ssram <= '0';
@@ -663,9 +638,6 @@ signal_mux:
when mem_rom =>
CYC_I_rom <= CYC_O;
when mem_ram =>
CYC_I_ram <= CYC_O;
when mem_sdram =>
CYC_I_sdram <= CYC_O;
@@ -685,11 +657,10 @@ signal_mux:
end process;
------------------------------------------------------------------
SRDY_I <= SRDY_O_flash or SRDY_O_ssram or SRDY_O_usb or SRDY_O_sdram or SRDY_O_ram or SRDY_O_rom or SRDY_O_uart or SRDY_O_gpio or SRDY_O_vga or SRDY_O_ac97;
ACK_I <= ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_ssram or ACK_O_ram or ACK_O_rom or ACK_O_uart or ACK_O_gpio or ACK_O_vga or ACK_O_ac97;
SRDY_I <= SRDY_O_flash or SRDY_O_ssram or SRDY_O_usb or SRDY_O_sdram or SRDY_O_rom or SRDY_O_uart or SRDY_O_gpio or SRDY_O_vga or SRDY_O_ac97;
ACK_I <= ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_ssram or ACK_O_rom or ACK_O_uart or ACK_O_gpio or ACK_O_vga or ACK_O_ac97;
MDAT_I <= SDAT_O_ssram when CYC_I_ssram = '1' else
SDAT_O_sdram(31 downto 0) when CYC_I_sdram = '1' else
SDAT_O_ram when CYC_I_ram = '1' else
SDAT_O_rom when CYC_I_rom = '1' else
SDAT_O_flash when CYC_I_flash = '1' else
SDAT_O_usb when CYC_I_usb = '1' else
@@ -718,23 +689,6 @@ inst_mips_top: mips_top
INT => INT
);
inst_ram_wb : ram_wb
PORT MAP
(
CLK_I => clk,
RST_I => rst,
CYC_I => CYC_I_ram,
STB_I => STB_O,
SEL_I => SEL_O,
WE_I => WE_O,
ACK_O => ACK_O_ram,
SRDY_O => SRDY_O_ram,
MRDY_I => MRDY_O,
ADDR_I => ADDR_O,
DAT_I => MDAT_O,
DAT_O => SDAT_O_ram
);
inst_rom_wb : rom_wb
PORT MAP
(