This commit was manufactured by cvs2svn to create tag 'MIPS_R10'.

git-svn-id: http://moon:8086/svn/vhdl/tags/MIPS_R10@321 cc03376c-175c-47c8-b038-4cd826a8556b

Common/sim/compile_simprim.do

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+vlib simprim
+
+set XILINX C:/Programme/Xilinx101/ISE
+
+vcom -93 -work simprim  $XILINX/vhdl/src/simprims/simprim_Vcomponents_mti.vhd
+vcom -93 -work simprim  $XILINX/vhdl/src/simprims/simprim_Vpackage_mti.vhd
+vcom -93 -work simprim  $XILINX/vhdl/src/simprims/simprim_SMODEL_mti.vhd
+vcom -93 -work simprim  $XILINX/vhdl/src/simprims/simprim_VITAL_mti.vhd

Common/sim/compile_unisim.do

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+vlib unisim
+
+set XILINX C:/Programme/Xilinx101/ISE
+
+vcom -93 -work unisim  $XILINX/vhdl/src/unisims/unisim_vpkg.vhd
+vcom -93 -work unisim  $XILINX/vhdl/src/unisims/unisim_vcomp.vhd
+vcom -93 -work unisim  $XILINX/vhdl/src/unisims/unisim_smodel.vhd
+vcom -93 -work unisim  $XILINX/vhdl/src/unisims/unisim_vital.vhd

Common/ucf/ml402.ucf

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+#
+#     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
+#     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
+#     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
+#     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
+#     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
+#     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
+#     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
+#     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
+#     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
+#     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+#     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
+#     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+#     FOR A PARTICULAR PURPOSE.
+#     
+#     (c) Copyright 2005 Xilinx, Inc.
+#     All rights reserved.
+#
+
+# Bus clock nets
+NET "sys_clk"  TNM_NET = "sys_clk";
+NET "tft_clk"  TNM_NET = "tft_clk";
+NET sys_clk_in TNM_NET = "sys_clk_in";
+TIMESPEC "TSSYSCLK" = PERIOD "sys_clk_in" 9.9 ns HIGH 50 %;
+
+NET sys_clk_in LOC = AE14;
+NET sys_clk_in IOSTANDARD = LVCMOS33;
+NET sys_rst_in LOC = D6;
+NET sys_rst_in PULLUP;
+NET sys_rst_in TIG;
+
+NET uart_RX LOC = W2;
+NET uart_RX IOSTANDARD = LVCMOS33;
+NET uart_RX TIG;
+NET uart_TX LOC = W1;
+NET uart_TX IOSTANDARD = LVCMOS33;
+NET uart_TX TIG;
+
+NET ext_irq TIG;
+
+# Reset timing ignore - treat as async paths
+NET sys_rst TIG;
+NET opb_v20_0_OPB_Rst TIG;
+NET lmb_v10_1_OPB_Rst TIG;
+NET lmb_v10_0_OPB_Rst TIG;
+NET opb_v20_0_Debug_SYS_Rst TIG;
+NET Debug_Rst TIG;
+NET plb_v34_0_PLB_Rst TIG;
+NET dcm_locked TIG;
+
+# Locate DCM/BUFG - Tools can probably figure them out automatically
+#                   but just LOC them down to be safe
+INST dcm_0/dcm_0/DCM_ADV_INST LOC = DCM_ADV_X0Y2;
+INST dcm_1/dcm_1/DCM_ADV_INST LOC = DCM_ADV_X0Y4;
+INST dcm_2/dcm_2/DCM_ADV_INST LOC = DCM_ADV_X0Y1;
+
+INST dcm_0/dcm_0/CLK0_BUFG_INST  LOC = BUFGCTRL_X0Y0;
+INST dcm_0/dcm_0/CLK90_BUFG_INST LOC = BUFGCTRL_X0Y1;
+INST dcm_0/dcm_0/CLKDV_BUFG_INST LOC = BUFGCTRL_X0Y2;
+
+INST dcm_1/dcm_1/CLK0_BUFG_INST  LOC = BUFGCTRL_X0Y31;
+INST dcm_1/dcm_1/CLK90_BUFG_INST LOC = BUFGCTRL_X0Y30;
+
+////////////////////////////////////////////////////////////////////////////
+// Buttons, LEDs, and DIP Switches 
+////////////////////////////////////////////////////////////////////////////
+
+# GPLED 0-3
+NET gpio<0>  LOC = G5;  #GPLED0
+NET gpio<1>  LOC = G6;  #GPLED1
+NET gpio<2>  LOC = A11; #GPLED2
+NET gpio<3>  LOC = A12; #GPLED3
+# North-East-South-West-Center LEDs
+NET gpio<4>  LOC = C6;  # C LED
+NET gpio<5>  LOC = F9;  # W LED
+NET gpio<6>  LOC = A5;  # S LED
+NET gpio<7>  LOC = E10; # E LED
+NET gpio<8>  LOC = E2;  # N LED
+# North-East-South-West-Center Buttons
+NET gpio<9>  LOC = B6;  # C Button
+NET gpio<10> LOC = E9;  # W Button
+NET gpio<11> LOC = A6;  # S Button
+NET gpio<12> LOC = F10; # E Button
+NET gpio<13> LOC = E7;  # N Button
+# Dip Switches 1-8
+NET gpio<14> LOC = U24; # DIP SW 8
+NET gpio<15> LOC = U25; # DIP SW 7
+NET gpio<16> LOC = V23; # DIP SW 6
+NET gpio<17> LOC = U23; # DIP SW 5
+NET gpio<18> LOC = U26; # DIP SW 4
+NET gpio<19> LOC = T26; # DIP SW 3
+NET gpio<20> LOC = R19; # DIP SW 2
+NET gpio<21> LOC = R20; # DIP SW 1
+NET gpio<14> IOSTANDARD = LVCMOS33;
+NET gpio<15> IOSTANDARD = LVCMOS33;
+NET gpio<16> IOSTANDARD = LVCMOS33;
+NET gpio<17> IOSTANDARD = LVCMOS33;
+NET gpio<18> IOSTANDARD = LVCMOS33;
+NET gpio<19> IOSTANDARD = LVCMOS33;
+NET gpio<20> IOSTANDARD = LVCMOS33;
+NET gpio<21> IOSTANDARD = LVCMOS33;
+#SMA Connectors
+NET gpio<22> LOC = C12; # SMA_IN_N
+NET gpio<23> LOC = C13; # SMA_IN_P
+NET gpio<24> LOC = D7;  # SMA_OUT_N
+NET gpio<25> LOC = D8;  # SMA_OUT_P
+NET gpio<26> LOC = AD12;# USERCLK
+NET gpio<26> IOSTANDARD = LVCMOS33;
+
+NET "gpio<*>" PULLDOWN;
+NET "gpio<*>" TIG;
+NET "gpio<*>" SLEW = SLOW;
+NET "gpio<*>" DRIVE = 2;
+
+NET "gpio<22>" SLEW = FAST;
+NET "gpio<22>" DRIVE = 12;
+NET "gpio<23>" SLEW = FAST;
+NET "gpio<23>" DRIVE = 12;
+NET "gpio<24>" SLEW = FAST;
+NET "gpio<24>" DRIVE = 12;
+NET "gpio<25>" SLEW = FAST;
+NET "gpio<25>" DRIVE = 12;
+
+NET  "gpio2_d_out<*>" TIG;
+NET  "gpio2_t_out<*>" TIG;
+NET  "gpio2_in<*>" TIG;
+
+#------------------------------------------------------------------------------
+# IO Pad Location Constraints / Properties for PS/2 Ports
+#------------------------------------------------------------------------------
+
+#Keyboard
+NET ps2_keyb_clk  LOC = D2;
+NET ps2_keyb_clk  SLEW = SLOW;
+NET ps2_keyb_clk  DRIVE = 2;
+NET ps2_keyb_clk  TIG;
+NET ps2_keyb_data LOC = G9;
+NET ps2_keyb_data SLEW = SLOW;
+NET ps2_keyb_data DRIVE = 2;
+NET ps2_keyb_data TIG;
+
+#Mouse
+NET ps2_mouse_clk  LOC = B14;
+NET ps2_mouse_clk  SLEW = SLOW;
+NET ps2_mouse_clk  DRIVE = 2;
+NET ps2_mouse_clk  TIG;
+NET ps2_mouse_data LOC = C14;
+NET ps2_mouse_data SLEW = SLOW;
+NET ps2_mouse_data DRIVE = 2;
+NET ps2_mouse_data TIG;
+
+#------------------------------------------------------------------------------
+# IO Pad Location Constraints / Properties for IIC Controller
+#------------------------------------------------------------------------------
+
+NET iic_scl    LOC = A17;
+NET iic_sda    LOC = B17;
+NET iic_scl    SLEW = SLOW;
+NET iic_scl    DRIVE = 6;
+NET iic_scl    TIG;
+NET iic_sda    SLEW = SLOW;
+NET iic_sda    DRIVE = 6;
+NET iic_sda    TIG;
+
+#------------------------------------------------------------------------------
+# IO Pad Location Constraints / Properties for AC97 Sound Controller
+#------------------------------------------------------------------------------
+
+NET ac97_bit_clk   LOC = AE10;
+NET ac97_bit_clk   IOSTANDARD = LVCMOS33;
+NET ac97_bit_clk   PERIOD = 80;
+NET ac97_sdata_in  LOC = AD16;
+NET ac97_sdata_in  IOSTANDARD = LVCMOS33;
+NET ac97_reset_n   LOC = AD10;
+NET ac97_reset_n   IOSTANDARD = LVCMOS33;
+NET ac97_reset_n   TIG;
+NET ac97_sdata_out LOC = C8;
+NET ac97_sync      LOC = D9;
+
+#------------------------------------------------------------------------------
+# IO Pad Location Constraints / Properties for System ACE MPU / USB
+#------------------------------------------------------------------------------
+
+NET sysace_clk_in   LOC        = AF11;
+NET sysace_clk_in   IOSTANDARD = LVCMOS33;
+NET sysace_clk_in   TNM_NET    = "sysace_clk_in";
+# Leave 1 ns margin
+TIMESPEC "TSSYSACE" = PERIOD "sysace_clk_in" 29 ns;
+
+NET sace_usb_a<0>   LOC        = U22;
+NET sace_usb_a<1>   LOC        = Y10;
+NET sace_usb_a<2>   LOC        = AA10;
+NET sace_usb_a<3>   LOC        = AC7;
+NET sace_usb_a<4>   LOC        = Y7;
+NET sace_usb_a<5>   LOC        = AA9;
+NET sace_usb_a<6>   LOC        = Y9;
+NET sace_usb_a<*>   IOSTANDARD = LVCMOS33;
+NET sace_usb_a<*>   SLEW       = FAST;
+NET sace_usb_a<*>   DRIVE      = 8;
+NET sace_mpce       LOC        = AD5;
+NET sace_mpce       IOSTANDARD = LVCMOS33;
+NET sace_mpce       SLEW       = FAST;
+NET sace_mpce       DRIVE      = 8;
+NET sace_usb_d<0>   LOC        = AB7;
+NET sace_usb_d<1>   LOC        = AC9;
+NET sace_usb_d<2>   LOC        = AB9;
+NET sace_usb_d<3>   LOC        = AE6;
+NET sace_usb_d<4>   LOC        = AD6;
+NET sace_usb_d<5>   LOC        = AF9;
+NET sace_usb_d<6>   LOC        = AE9;
+NET sace_usb_d<7>   LOC        = AD8;
+NET sace_usb_d<8>   LOC        = AC8;
+NET sace_usb_d<9>   LOC        = AF4;
+NET sace_usb_d<10>  LOC        = AE4;
+NET sace_usb_d<11>  LOC        = AD3;
+NET sace_usb_d<12>  LOC        = AC3;
+NET sace_usb_d<13>  LOC        = AF6;
+NET sace_usb_d<14>  LOC        = AF5;
+NET sace_usb_d<15>  LOC        = AA7;
+NET sace_usb_d<*>   IOSTANDARD = LVCMOS33;
+NET sace_usb_d<*>   SLEW       = FAST;
+NET sace_usb_d<*>   DRIVE      = 8;
+NET sace_usb_d<*>   PULLDOWN;
+NET sace_usb_oen    LOC        = AA8;
+NET sace_usb_oen    IOSTANDARD = LVCMOS33;
+NET sace_usb_oen    SLEW       = FAST;
+NET sace_usb_oen    DRIVE      = 8;
+NET sace_usb_wen    LOC        = Y8;
+NET sace_usb_wen    IOSTANDARD = LVCMOS33;
+NET sace_usb_wen    SLEW       = FAST;
+NET sace_usb_wen    DRIVE      = 8;
+NET sysace_mpirq    LOC        = AD4;
+NET sysace_mpirq    IOSTANDARD = LVCMOS33;
+NET sysace_mpirq    TIG;
+NET sysace_mpirq    PULLDOWN;
+
+NET usb_csn         LOC        = AF10;
+NET usb_csn         IOSTANDARD = LVCMOS33;
+NET usb_csn         SLEW       = FAST;
+NET usb_csn         DRIVE      = 8;
+NET usb_hpi_reset_n LOC        = A7;
+NET usb_hpi_reset_n IOSTANDARD = LVCMOS25;
+NET usb_hpi_reset_n TIG;
+NET usb_hpi_int     LOC        = V5;
+NET usb_hpi_int     IOSTANDARD = LVCMOS33;
+NET usb_hpi_int     TIG;
+NET usb_hpi_int     PULLDOWN;
+
+#------------------------------------------------------------------------------
+# IO Pad Location Constraints / Properties for DDR Controllers
+#------------------------------------------------------------------------------
+
+NET ddr_ad<0>  LOC = C26; # DDR_A0
+NET ddr_ad<1>  LOC = E17; # DDR_A1
+NET ddr_ad<2>  LOC = D18; # DDR_A2
+NET ddr_ad<3>  LOC = C19; # DDR_A3
+NET ddr_ad<4>  LOC = F17; # DDR_A4
+NET ddr_ad<5>  LOC = B18; # DDR_A5
+NET ddr_ad<6>  LOC = B20; # DDR_A6
+NET ddr_ad<7>  LOC = C20; # DDR_A7
+NET ddr_ad<8>  LOC = D20; # DDR_A8
+NET ddr_ad<9>  LOC = C21; # DDR_A9
+NET ddr_ad<10> LOC = A18; # DDR_A10
+NET ddr_ad<11> LOC = B21; # DDR_A11
+NET ddr_ad<12> LOC = A24; # DDR_A12
+NET ddr_ba<0>  LOC = B12; # DDR_BA0
+NET ddr_ba<1>  LOC = A16; # DDR_BA1
+NET ddr_casb   LOC = F23; # DDR_CAS_N
+NET ddr_cke    LOC = G22; # DDR_CKE
+NET ddr_csb    LOC = G21; # DDR_CS_N
+NET ddr_rasb   LOC = F24; # DDR_RAS_N
+NET ddr_web    LOC = A23; # DDR_WE_N
+
+NET ddr_clk    LOC = A10; # DDR_CK1_P
+NET ddr_clk_fb LOC = B13; # DDR_CK1_P (FEEDBACK)
+NET ddr_clkb   LOC = B10; # DDR_CK1_N
+
+NET ddr_dm<0>  LOC = G19; # DDR_DM0
+NET ddr_dm<1>  LOC = G24; # DDR_DM1
+NET ddr_dm<2>  LOC = G20; # DDR_DM2
+NET ddr_dm<3>  LOC = C22; # DDR_DM3
+
+NET ddr_dqs<0> LOC = D25; # DDR_DQS0
+NET ddr_dqs<1> LOC = G18; # DDR_DQS1
+NET ddr_dqs<2> LOC = G17; # DDR_DQS2
+NET ddr_dqs<3> LOC = D26; # DDR_DQS3
+
+NET ddr_dq<0> LOC = H20; # DDR_D0
+NET ddr_dq<1> LOC = E23; # DDR_D1
+NET ddr_dq<2> LOC = H26; # DDR_D2
+NET ddr_dq<3> LOC = H22; # DDR_D3
+NET ddr_dq<4> LOC = E25; # DDR_D4
+NET ddr_dq<5> LOC = E26; # DDR_D5
+NET ddr_dq<6> LOC = F26; # DDR_D6
+NET ddr_dq<7> LOC = E24; # DDR_D7
+NET ddr_dq<8> LOC = E20; # DDR_D8
+NET ddr_dq<9> LOC = A22; # DDR_D9
+NET ddr_dq<10> LOC = C23; # DDR_D10
+NET ddr_dq<11> LOC = C24; # DDR_D11
+NET ddr_dq<12> LOC = A20; # DDR_D12
+NET ddr_dq<13> LOC = A21; # DDR_D13
+NET ddr_dq<14> LOC = D24; # DDR_D14
+NET ddr_dq<15> LOC = E18; # DDR_D15
+NET ddr_dq<16> LOC = F18; # DDR_D16
+NET ddr_dq<17> LOC = A19; # DDR_D17
+NET ddr_dq<18> LOC = F19; # DDR_D18
+NET ddr_dq<19> LOC = B23; # DDR_D19
+NET ddr_dq<20> LOC = E21; # DDR_D20
+NET ddr_dq<21> LOC = D22; # DDR_D21
+NET ddr_dq<22> LOC = D23; # DDR_D22
+NET ddr_dq<23> LOC = B24; # DDR_D23
+NET ddr_dq<24> LOC = E22; # DDR_D24
+NET ddr_dq<25> LOC = F20; # DDR_D25
+NET ddr_dq<26> LOC = H23; # DDR_D26
+NET ddr_dq<27> LOC = G25; # DDR_D27
+NET ddr_dq<28> LOC = G26; # DDR_D28
+NET ddr_dq<29> LOC = H25; # DDR_D29
+NET ddr_dq<30> LOC = H24; # DDR_D30
+NET ddr_dq<31> LOC = H21; # DDR_D31
+
+NET ddr_ad<*>  IOSTANDARD = SSTL2_I;
+NET ddr_ba<*>  IOSTANDARD = SSTL2_I;
+NET ddr_casb   IOSTANDARD = SSTL2_I;
+NET ddr_cke    IOSTANDARD = SSTL2_I;
+NET ddr_clk    IOSTANDARD = SSTL2_I;
+NET ddr_clk_fb IOSTANDARD = LVCMOS25;
+NET ddr_clkb   IOSTANDARD = SSTL2_I;
+NET ddr_casb   IOSTANDARD = SSTL2_I;
+NET ddr_csb    IOSTANDARD = SSTL2_I;
+NET ddr_rasb   IOSTANDARD = SSTL2_I;
+NET ddr_web    IOSTANDARD = SSTL2_I;
+
+NET ddr_dqs<*> IOSTANDARD = SSTL2_II;
+NET ddr_dm<*>  IOSTANDARD = SSTL2_II;
+NET ddr_dq<*>  IOSTANDARD = SSTL2_II;
+
+// Timing Constraint for DDR Feedback Clock
+NET "ddr_clk_fb" TNM_NET = "ddr_clk_fb";
+TIMESPEC "TSDDR_FB" = PERIOD "ddr_clk_fb" 9.9 ns;
+
+#------------------------------------------------------------------------------
+# IO Pad Location Constraints / Properties for TFT VGA LCD Controller
+#------------------------------------------------------------------------------
+
+NET tft_lcd_b<0> LOC = L26; # VGA_B2
+NET tft_lcd_b<0> IOSTANDARD = LVCMOS33;
+NET tft_lcd_b<1> LOC = C5;  # VGA_B3
+NET tft_lcd_b<2> LOC = C7;  # VGA_B4
+NET tft_lcd_b<3> LOC = B7;  # VGA_B5
+NET tft_lcd_b<4> LOC = G8;  # VGA_B6
+NET tft_lcd_b<5> LOC = F8;  # VGA_B7
+NET tft_lcd_b<*> SLEW = FAST;
+NET tft_lcd_b<*> DRIVE = 8;
+
+NET tft_lcd_clk  LOC = AF8;
+NET tft_lcd_clk  IOSTANDARD = LVDCI_33;
+NET tft_lcd_clk  SLEW = FAST;
+NET tft_lcd_clk  DRIVE = 8;
+
+NET tft_lcd_g<0> LOC = M20; # VGA_G2
+NET tft_lcd_g<0> IOSTANDARD = LVCMOS33;
+NET tft_lcd_g<1> LOC = E4;  # VGA_G3
+NET tft_lcd_g<2> LOC = D3;  # VGA_G4
+NET tft_lcd_g<3> LOC = H7;  # VGA_G5
+NET tft_lcd_g<4> LOC = H8;  # VGA_G6
+NET tft_lcd_g<5> LOC = C1;  # VGA_G7
+NET tft_lcd_g<*> SLEW = FAST;
+NET tft_lcd_g<*> DRIVE = 8;
+
+NET tft_lcd_hsync LOC = C10;
+NET tft_lcd_hsync SLEW = FAST;
+NET tft_lcd_hsync DRIVE = 8;
+
+NET tft_lcd_r<0> LOC = N25; #VGA_R2
+NET tft_lcd_r<0> IOSTANDARD = LVCMOS33;
+NET tft_lcd_r<1> LOC = C2; #VGA_R3
+NET tft_lcd_r<2> LOC = G7; #VGA_R4
+NET tft_lcd_r<3> LOC = F7; #VGA_R5
+NET tft_lcd_r<4> LOC = E5; #VGA_R6
+NET tft_lcd_r<5> LOC = E6; #VGA_R7
+NET tft_lcd_r<*> SLEW = FAST;
+NET tft_lcd_r<*> DRIVE = 8;
+
+NET tft_lcd_vsync LOC = A8;
+NET tft_lcd_vsync SLEW = FAST;
+NET tft_lcd_vsync DRIVE = 8;
+
+TIMESPEC "TSPLB_TFT" = FROM "sys_clk" TO "tft_clk" TIG;
+TIMESPEC "TSTFT_PLB" = FROM "tft_clk" TO "sys_clk" TIG;
+
+////////////////////////////////////////////////////////////////////////////
+// Misc Board Signals
+////////////////////////////////////////////////////////////////////////////
+
+NET plb_error LOC = L24;
+NET plb_error IOSTANDARD = LVCMOS33;
+NET plb_error TIG;
+NET opb_error LOC = V6;
+NET opb_error IOSTANDARD = LVCMOS33;
+NET opb_error TIG;
+
+#------------------------------------------------------------------------------
+# IO Pad Location Constraints / Properties for Ethernet
+#------------------------------------------------------------------------------
+
+NET phy_col        LOC = E3;
+NET phy_crs        LOC = D5;
+NET phy_dv         LOC = A9;
+NET phy_rx_clk     LOC = B15;
+NET phy_rx_data<3> LOC = C4;
+NET phy_rx_data<2> LOC = D4;
+NET phy_rx_data<1> LOC = E1;
+NET phy_rx_data<0> LOC = F1;
+
+NET phy_rx_er      LOC = B9;
+NET phy_tx_clk     LOC = C15;
+NET phy_mii_clk    LOC = D1;
+NET phy_mii_int_n  LOC = H4;
+NET phy_rst_n      LOC = D10;
+NET phy_tx_data<3> LOC = G1;
+NET phy_tx_data<2> LOC = H3;
+NET phy_tx_data<1> LOC = H2;
+NET phy_tx_data<0> LOC = H1;
+NET phy_tx_en      LOC = F4;
+NET phy_tx_er      LOC = F3;
+NET phy_mii_data   LOC = G4;
+
+NET phy_mii_int_n  PULLUP;
+
+NET phy_mii_int_n  TIG;
+NET phy_rst_n      TIG;
+
+# Timing Constraints (these are recommended in documentation and
+# are unaltered except for the TIG)
+NET "phy_rx_clk" TNM_NET = "RXCLK_GRP";
+NET "phy_tx_clk" TNM_NET = "TXCLK_GRP";
+TIMESPEC "TSTXOUT" = FROM "TXCLK_GRP" TO "PADS" 10 ns;
+TIMESPEC "TSRXIN" = FROM "PADS" TO "RXCLK_GRP" 6 ns;
+
+NET "phy_tx_clk" MAXSKEW= 1.0 ns;
+NET "phy_rx_clk" MAXSKEW= 1.0 ns;
+NET "phy_rx_clk" PERIOD = 40 ns HIGH 14 ns;
+NET "phy_tx_clk" PERIOD = 40 ns HIGH 14 ns;
+
+NET "phy_rx_data<3>" IOBDELAY=NONE;
+NET "phy_rx_data<2>" IOBDELAY=NONE;
+NET "phy_rx_data<1>" IOBDELAY=NONE;
+NET "phy_rx_data<0>" IOBDELAY=NONE;
+NET "phy_dv" IOBDELAY=NONE;
+NET "phy_rx_er" IOBDELAY=NONE;
+NET "phy_crs" IOBDELAY=NONE;
+NET "phy_col" IOBDELAY=NONE;
+
+# Workaround to help meet "phy_rx_clk MAXSKEW= 1.0 ns" constraint
+INST "opb_ethernet_0/opb_ethernet_0/RX_FF_I0" IOB=FALSE;
+INST "opb_ethernet_0/opb_ethernet_0/RX_FF_I1" IOB=FALSE;
+INST "opb_ethernet_0/opb_ethernet_0/RX_FF_I2" IOB=FALSE;
+INST "opb_ethernet_0/opb_ethernet_0/RX_FF_I3" IOB=FALSE;
+INST "opb_ethernet_0/opb_ethernet_0/DVD_FF"   IOB=FALSE;
+INST "opb_ethernet_0/opb_ethernet_0/RER_FF"   IOB=FALSE;
+
+# Timing ignores (to specify unconstrained paths)
+TIMESPEC "TS_PHYTX_OPB" = FROM "TXCLK_GRP" TO "sys_clk" TIG;
+TIMESPEC "TS_OPB_PHYTX" = FROM "sys_clk" TO "TXCLK_GRP" TIG;
+TIMESPEC "TS_PHYRX_OPB" = FROM "RXCLK_GRP" TO "sys_clk" TIG;
+TIMESPEC "TS_OPB_PHYRX" = FROM "sys_clk" TO "RXCLK_GRP" TIG;
+
+#------------------------------------------------------------------------------
+# IO Pad Location Constraints / Properties for SRAM/FLASH
+#------------------------------------------------------------------------------
+
+NET sram_clk            LOC = AF7;
+NET sram_clk_fb         LOC = AD17;
+NET flash_a23           LOC = T21;
+NET sram_flash_addr<22> LOC = U20;
+NET sram_flash_addr<21> LOC = T19;
+NET sram_flash_addr<20> LOC = AC5;
+NET sram_flash_addr<19> LOC = AB5;
+NET sram_flash_addr<18> LOC = AC4;
+NET sram_flash_addr<17> LOC = AB4;
+
+NET sram_flash_addr<16> LOC = AB3;
+NET sram_flash_addr<15> LOC = AA4;
+NET sram_flash_addr<14> LOC = AA3;
+NET sram_flash_addr<13> LOC = W5;
+NET sram_flash_addr<12> LOC = W6;
+NET sram_flash_addr<11> LOC = W3;
+NET sram_flash_addr<10> LOC = AF3;
+NET sram_flash_addr<9>  LOC = AE3;
+NET sram_flash_addr<8>  LOC = AD2;
+NET sram_flash_addr<7>  LOC = AD1;
+NET sram_flash_addr<6>  LOC = AC2;
+NET sram_flash_addr<5>  LOC = AC1;
+NET sram_flash_addr<4>  LOC = AB2;
+NET sram_flash_addr<3>  LOC = AB1;
+NET sram_flash_addr<2>  LOC = AA1;
+NET sram_flash_addr<1>  LOC = Y2;
+NET sram_flash_addr<0>  LOC = Y1;
+NET sram_flash_data<31> LOC = F14;
+NET sram_flash_data<30> LOC = F13;
+NET sram_flash_data<29> LOC = F12;
+NET sram_flash_data<28> LOC = F11;
+NET sram_flash_data<27> LOC = F16;
+NET sram_flash_data<26> LOC = F15;
+NET sram_flash_data<25> LOC = D14;
+NET sram_flash_data<24> LOC = D13;
+NET sram_flash_data<23> LOC = D15;
+NET sram_flash_data<22> LOC = E14;
+NET sram_flash_data<21> LOC = C11;
+NET sram_flash_data<20> LOC = D11;
+NET sram_flash_data<19> LOC = D16;
+NET sram_flash_data<18> LOC = C16;
+NET sram_flash_data<17> LOC = E13;
+NET sram_flash_data<16> LOC = D12;
+NET sram_flash_data<15> LOC = AA14;
+NET sram_flash_data<14> LOC = AB14;
+NET sram_flash_data<13> LOC = AC12;
+NET sram_flash_data<12> LOC = AC11;
+NET sram_flash_data<11> LOC = AA16;
+NET sram_flash_data<10> LOC = AA15;
+NET sram_flash_data<9>  LOC = AB13;
+NET sram_flash_data<8>  LOC = AA13;
+NET sram_flash_data<7>  LOC = AC14;
+NET sram_flash_data<6>  LOC = AD14;
+NET sram_flash_data<5>  LOC = AA12;
+NET sram_flash_data<4>  LOC = AA11;
+NET sram_flash_data<3>  LOC = AC16;
+NET sram_flash_data<2>  LOC = AC15;
+NET sram_flash_data<1>  LOC = AC13;
+NET sram_flash_data<0>  LOC = AD13;
+NET sram_cen            LOC = V7;
+NET sram_flash_oe_n     LOC = AC6;
+NET sram_flash_we_n     LOC = AB6;
+NET sram_bw<3>          LOC = Y3; #Y4; 
+NET sram_bw<2>          LOC = Y4; #Y3;
+NET sram_bw<1>          LOC = Y5; #Y6;
+NET sram_bw<0>          LOC = Y6; #Y5;
+NET flash_ce            LOC = W7;
+NET sram_adv_ld_n       LOC = W4;
+NET sram_mode           LOC = V26;
+
+NET sram_clk           IOSTANDARD = LVCMOS33;
+NET sram_clk           DRIVE = 16;
+NET sram_clk           SLEW = FAST;
+NET sram_clk_fb        IOSTANDARD = LVCMOS33;
+
+NET flash_a23          IOSTANDARD = LVDCI_33;
+NET flash_a23  SLEW = FAST;
+NET flash_a23  DRIVE = 8;
+
+NET sram_mode          IOSTANDARD = LVDCI_33;
+NET sram_mode SLEW = FAST;
+NET sram_mode DRIVE = 8;
+
+NET sram_flash_addr<*> IOSTANDARD = LVDCI_33;
+NET sram_flash_addr<*>  SLEW = FAST;
+NET sram_flash_addr<*>  DRIVE = 8;
+
+NET sram_flash_data<*> IOSTANDARD = LVCMOS33;
+NET sram_flash_data<*> DRIVE = 12;
+NET sram_flash_data<*> SLEW = FAST;
+NET sram_flash_data<*> PULLDOWN;
+
+NET sram_flash_oe_n    IOSTANDARD = LVDCI_33;
+NET sram_flash_oe_n SLEW = FAST;
+NET sram_flash_oe_n DRIVE = 8;
+
+NET sram_flash_we_n    IOSTANDARD = LVDCI_33;
+NET sram_flash_we_n SLEW = FAST;
+NET sram_flash_we_n DRIVE = 8;
+
+NET sram_bw<*>         IOSTANDARD = LVDCI_33;
+NET sram_bw<*> SLEW = FAST;
+NET sram_bw<*> DRIVE = 8;
+
+NET flash_ce           IOSTANDARD = LVDCI_33;
+NET flash_ce SLEW = FAST;
+NET flash_ce DRIVE = 8;
+
+NET sram_cen           IOSTANDARD = LVDCI_33;
+NET sram_cen SLEW = FAST;
+NET sram_cen DRIVE = 8;
+
+NET sram_adv_ld_n      IOSTANDARD = LVDCI_33;
+NET sram_adv_ld_n SLEW = FAST;
+NET sram_adv_ld_n DRIVE = 8;
+
+#------------------------------------------------------------------------------
+# IO Pad Location Constraints / Properties for Expansion Header GPIO
+#------------------------------------------------------------------------------
+
+NET gpio_exp_hdr1<31> LOC = AF24; # HDR1_64
+NET gpio_exp_hdr1<30> LOC = AE24; # HDR1_62
+NET gpio_exp_hdr1<29> LOC = AD22; # HDR1_8
+NET gpio_exp_hdr1<28> LOC = AB21; # HDR1_58
+NET gpio_exp_hdr1<27> LOC = W20;  # HDR1_44
+NET gpio_exp_hdr1<26> LOC = W21;  # HDR1_48
+NET gpio_exp_hdr1<25> LOC = AB22; # HDR1_14
+NET gpio_exp_hdr1<24> LOC = AD25; # HDR1_20
+NET gpio_exp_hdr1<23> LOC = W22;  # HDR1_46
+NET gpio_exp_hdr1<22> LOC = V21;  # HDR1_56
+NET gpio_exp_hdr1<21> LOC = V22;  # HDR1_54
+NET gpio_exp_hdr1<20> LOC = AC22; # HDR1_16
+NET gpio_exp_hdr1<19> LOC = AD26; # HDR1_18
+NET gpio_exp_hdr1<18> LOC = AC26; # HDR1_34
+NET gpio_exp_hdr1<17> LOC = AD23; # HDR1_6
+NET gpio_exp_hdr1<16> LOC = AB25; # HDR1_30
+NET gpio_exp_hdr1<15> LOC = AC23; # HDR1_4
+NET gpio_exp_hdr1<14> LOC = AB26; # HDR1_24
+NET gpio_exp_hdr1<13> LOC = AC21; # HDR1_60
+NET gpio_exp_hdr1<12> LOC = AA23; # HDR1_10
+NET gpio_exp_hdr1<11> LOC = AA26; # HDR1_22
+NET gpio_exp_hdr1<10> LOC = Y25;  # HDR1_40
+NET gpio_exp_hdr1<9>  LOC = Y26;  # HDR1_38
+NET gpio_exp_hdr1<8>  LOC = W26;  # HDR1_50
+NET gpio_exp_hdr1<7>  LOC = AB23; # HDR1_12
+NET gpio_exp_hdr1<6>  LOC = Y24;  # HDR1_26
+NET gpio_exp_hdr1<5>  LOC = AB24; # HDR1_32
+NET gpio_exp_hdr1<4>  LOC = W25;  # HDR1_52
+NET gpio_exp_hdr1<3>  LOC = AC24; # HDR1_2
+NET gpio_exp_hdr1<2>  LOC = AC25; # HDR1_36
+NET gpio_exp_hdr1<1>  LOC = V20;  # HDR1_42
+NET gpio_exp_hdr1<0>  LOC = AA24; # HDR1_28
+NET gpio_exp_hdr1<*> TIG;
+NET gpio_exp_hdr1<*> PULLDOWN;
+
+NET gpio_exp_hdr2<31> LOC = AF18; # HDR2_40
+NET gpio_exp_hdr2<30> LOC = AE18; # HDR2_38
+NET gpio_exp_hdr2<29> LOC = AF19; # HDR2_32
+NET gpio_exp_hdr2<28> LOC = AF20; # HDR2_30
+NET gpio_exp_hdr2<27> LOC = AF21; # HDR2_44
+NET gpio_exp_hdr2<26> LOC = AF22; # HDR2_42
+NET gpio_exp_hdr2<25> LOC = AF23; # HDR2_24
+NET gpio_exp_hdr2<24> LOC = AE23; # HDR2_22
+NET gpio_exp_hdr2<23> LOC = AC18; # HDR2_48
+NET gpio_exp_hdr2<22> LOC = AB18; # HDR2_46
+NET gpio_exp_hdr2<21> LOC = AD19; # HDR2_64
+NET gpio_exp_hdr2<20> LOC = AC19; # HDR2_62
+NET gpio_exp_hdr2<19> LOC = AE20; # HDR2_16
+NET gpio_exp_hdr2<18> LOC = AD20; # HDR2_14
+NET gpio_exp_hdr2<17> LOC = AE21; # HDR2_36
+NET gpio_exp_hdr2<16> LOC = AD21; # HDR2_34
+NET gpio_exp_hdr2<15> LOC = AB20; # HDR2_52
+NET gpio_exp_hdr2<14> LOC = AC20; # HDR2_50
+NET gpio_exp_hdr2<13> LOC = Y17;  # HDR2_56
+NET gpio_exp_hdr2<12> LOC = AA17; # HDR2_54
+NET gpio_exp_hdr2<11> LOC = AA19; # HDR2_60
+NET gpio_exp_hdr2<10> LOC = AA20; # HDR2_58
+NET gpio_exp_hdr2<9>  LOC = Y22;  # HDR2_8
+NET gpio_exp_hdr2<8>  LOC = Y23;  # HDR2_6
+NET gpio_exp_hdr2<7>  LOC = W23;  # HDR2_12
+NET gpio_exp_hdr2<6>  LOC = W24;  # HDR2_10
+NET gpio_exp_hdr2<5>  LOC = Y20;  # HDR2_20
+NET gpio_exp_hdr2<4>  LOC = Y21;  # HDR2_18
+NET gpio_exp_hdr2<3>  LOC = Y19;  # HDR2_28
+NET gpio_exp_hdr2<2>  LOC = W19;  # HDR2_26
+NET gpio_exp_hdr2<1>  LOC = AA18; # HDR2_4
+NET gpio_exp_hdr2<0>  LOC = Y18;  # HDR2_2
+NET gpio_exp_hdr2<*> TIG;
+NET gpio_exp_hdr2<*> PULLDOWN;
+
+#------------------------------------------------------------------------------
+# IO Pad Location Constraints / Properties for Character LCD GPIO
+#------------------------------------------------------------------------------
+
+NET gpio_char_lcd<6> LOC = AE13; # LCD_E
+NET gpio_char_lcd<5> LOC = AC17; # LCD_RS
+NET gpio_char_lcd<4> LOC = AB17; # LCD_RW
+NET gpio_char_lcd<3> LOC = AF12; # LCD_DB7
+NET gpio_char_lcd<2> LOC = AE12; # LCD_DB6
+NET gpio_char_lcd<1> LOC = AC10; # LCD_DB5
+NET gpio_char_lcd<0> LOC = AB10; # LCD_DB4
+NET gpio_char_lcd<*> IOSTANDARD = LVCMOS33;
+NET gpio_char_lcd<*> TIG;
+NET gpio_char_lcd<*> PULLDOWN;

lib/CPUs/JCpu/asm/dctest.jsm

@@ -0,0 +1,56 @@
+; -------------------------------------------------	
+;			PROJECT	"dctest"
+; -------------------------------------------------	
+
+include "../../../jasm/cregs.inc.jsm"
+
+; -------------------------------------------------	
+				xmem
+				org		4
+konst:			dc		0x01, 0x12,"A"
+gap1:			db		16
+mesg:			dc		"Hallo", 13,0x0A, 0
+name:			dc		"Jens",0
+msg1:			dc		"Welcome to JASM CPU",0
+msg2:			dc		"Ready",0
+msg3:			dc		"Testing",0
+msg4:			dc		"Passed",0
+msg5:			dc		"Error",0
+crlf:			dc		0x0D, 0x0A
+
+				org		0x00
+shit:			db		4	
+
+				cmem	0
+				org		8
+cram1:			db		16
+cram2:			db		6
+cram3:			db		4
+
+				cmem	1
+cram4:			db		8
+cram5:			db		8
+				org		0x20
+cram6:			db		8
+cram7:			db		4
+
+reg_revision:	equ		0x00			
+reg_testid:		equ		0x01			
+
+; -------------------------------------------------	
+				code
+				org		0x000
+reset:			jmp		start
+
+; -------------------------------------------------	
+				org		0x001
+int_vec:		jmp		isr
+
+; -------------------------------------------------	
+				org		0x010
+			
+start:			jmp		start
+
+; -------------------------------------------------	
+isr:			reti
+

lib/CPUs/JCpu/asm/dctest.tcl

@@ -0,0 +1,212 @@
+# ----------------------------------------------------------------------
+# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+# This file: The ROM file for upload to target over JTAG 
+#
+# Copyright (C) 2007 J. Ahrensfeld
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+# 
+# For questions and ideas, please contact the author at jens@jayfield.org
+#
+# ---------------------------------------------------------------------
+
+# ---------------------------------------------------------------------
+# For Chipscope 9.1
+# ---------------------------------------------------------------------
+# Source JTAG/TCL frame work
+cd $env(CHIPSCOPE)\\bin\\nt
+source csejtag.tcl
+
+namespace import ::chipscope::*
+
+# Platform USB Cable
+set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"]
+# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
+
+# Create session
+set handle [::chipscope::csejtag_session create 0]
+
+# Open JTAG and lock
+set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
+set lock_result [::chipscope::csejtag_target lock $handle 1000]
+
+set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
+
+# Get Device ID
+set devtype "Virtex-4SX"
+set devid 2
+set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
+set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
+
+set CSE_OP $CSEJTAG_SHIFT_READWRITE
+set CSE_ES $CSEJTAG_RUN_TEST_IDLE
+
+# Write Program
+# JASM_ROM_INSERT_HERE
+# Assembled from dctest.jsm
+# ---------------------------------------------------------------
+# Shift the USER2 Instruction (b1111000010) into the Instruction Register of FPGA
+# User 1
+set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C2"]
+
+# 0x000: JMP 0x010
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00030010"
+
+# 0x001: JMP 0x011
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00130011"
+
+# 0x002:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00200000"
+
+# 0x003:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00300000"
+
+# 0x004:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00400000"
+
+# 0x005:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00500000"
+
+# 0x006:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00600000"
+
+# 0x007:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00700000"
+
+# 0x008:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00800000"
+
+# 0x009:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00900000"
+
+# 0x00A:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00A00000"
+
+# 0x00B:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00B00000"
+
+# 0x00C:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00C00000"
+
+# 0x00D:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00D00000"
+
+# 0x00E:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00E00000"
+
+# 0x00F:
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00F00000"
+
+# 0x010: JMP 0x010
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01030010"
+
+# 0x011: RETI
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0113F000"
+
+# Assembled from dctest.jsm
+# ---------------------------------------------------------------
+# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA
+# User 2
+set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C3"]
+
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0000"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0100"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0200"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0300"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0401"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0512"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0641"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0700"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0800"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0900"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0A00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0B00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0C00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0D00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0E00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0F00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1000"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1100"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1200"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1300"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1400"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1500"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1600"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1748"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1861"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "196C"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1A6C"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1B6F"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1C0D"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1D0A"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1E00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1F4A"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2065"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "216E"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2273"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2300"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2457"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2565"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "266C"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2763"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "286F"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "296D"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2A65"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2B20"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2C74"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2D6F"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2E20"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2F4A"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3041"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3153"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "324D"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3320"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3443"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3550"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3655"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3700"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3852"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3965"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3A61"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3B64"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3C79"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3D00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3E54"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3F65"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4073"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4174"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4269"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "436E"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4467"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4500"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4650"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4761"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4873"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4973"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4A65"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4B64"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4C00"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4D45"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4E72"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4F72"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "506F"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5172"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5200"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "530D"
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "540A"
+
+::chipscope::csejtag_target unlock $handle
+::chipscope::csejtag_target close $handle
+::chipscope::csejtag_session destroy $handle
+exit

lib/CPUs/JCpu/asm/itest.jsm

@@ -0,0 +1,858 @@
+; -------------------------------------------------	
+;			PROJECT	"itest"
+; -------------------------------------------------	
+
+include "../../../jasm/cregs.inc.jsm"
+
+; -------------------------------------------------	
+				xmem
+msg:			dc		"Hallo", 0
+xram:			db		256
+
+				cmem	0
+cram:			db		256
+
+reg_revision:	equ		0x00			
+reg_testid:		equ		0x01			
+
+; -------------------------------------------------	
+			code
+			org		0x000
+reset:		jmp		start
+
+; -------------------------------------------------	
+			org		0x001
+int_vec:	jmp		isr
+
+; -------------------------------------------------	
+			org		0x010
+			
+start:		call	init
+			cin		R0, (cpu_revision)
+			xout	(reg_revision), R0
+			
+			; Test 0
+			call	test0
+			
+			; Test 1
+			mov		R0, 1
+			xout	(reg_testid), R0
+			call	test1
+			
+			; Test 2
+			mov		R0, 2
+			xout	(reg_testid), R0
+			call	test2
+
+			; Test 3
+			mov		R0, 3
+			xout	(reg_testid), R0
+			call	test3
+
+			; Test 4
+			mov		R0, 4
+			xout	(reg_testid), R0
+			call	test4
+
+			; Test 5
+			mov		R0, 5
+			xout	(reg_testid), R0
+			call	test5
+
+			; Test 6
+			mov		R0, 6
+			xout	(reg_testid), R0
+			call	test6
+
+			; Test 7
+			mov		R0, 7
+			xout	(reg_testid), R0
+			call	test7
+
+			; Test 8
+			mov		R0, 8
+			xout	(reg_testid), R0
+			call	test8
+
+			; Test 9
+			mov		R0, 9
+			xout	(reg_testid), R0
+			call	test9
+			
+			; Test 10
+			mov		R0, 10
+			xout	(reg_testid), R0
+			call	test10
+
+			; Test 11
+			mov		R0, 11
+			xout	(reg_testid), R0
+			call	test11
+
+			; Test 12
+			mov		R0, 12
+			xout	(reg_testid), R0
+			call	test12
+
+			; End of test
+			mov		R0, 0xFF
+			xout	(reg_testid), R0
+			
+			jmp		ok
+
+; -------------------------------------------------	
+init:		mov		R0, 0
+			mov		R1, 0
+			mov		R2, 0
+			mov		R3, 0
+			mov		R4, 0
+			mov		R5, 0
+			mov		R6, 0
+			mov		R7, 0
+			mov		R8, 0
+			mov		R9, 0
+			mov		R10, 0
+			mov		R11, 0
+			mov		R12, 0
+			mov		R13, 0
+			mov		R14, 0
+			mov		R15, 0
+			ret
+
+; -------------------------------------------------	
+; MOV|R|K
+; MOV|R|R
+test0:		mov		R0, 0x10
+			cmp		R0, 0x10
+			jne		error
+			add		R0, 1
+
+			mov		R1, R0
+			cmp		R1, 0x11
+			jne		error
+			add		R1, 1
+
+			mov		R2, R1
+			cmp		R2, 0x12
+			jne		error
+			add		R2, 1
+
+			mov		R3, R2
+			cmp		R3, 0x13
+			jne		error
+			add		R3, 1
+
+			mov		R4, R3
+			cmp		R4, 0x14
+			jne		error
+			add		R4, 1
+
+			mov		R5, R4
+			cmp		R5, 0x15
+			jne		error
+			add		R5, 1
+
+			mov		R6, R5
+			cmp		R6, 0x16
+			jne		error
+			add		R6, 1
+
+			mov		R7, R6
+			cmp		R7, 0x17
+			jne		error
+			add		R7, 1
+
+			mov		R8, R7
+			cmp		R8, 0x18
+			jne		error
+			add		R8, 1
+
+			mov		R9, R8
+			cmp		R9, 0x19
+			jne		error
+			add		R9, 1
+
+			mov		R10, R9
+			cmp		R10, 0x1A
+			jne		error
+			add		R10, 1
+
+			mov		R11, R10
+			cmp		R11, 0x1B
+			jne		error
+			add		R11, 1
+
+			mov		R12, R11
+			cmp		R12, 0x1C
+			jne		error
+			add		R12, 1
+
+			mov		R13, R12
+			cmp		R13, 0x1D
+			jne		error
+			add		R13, 1
+
+			mov		R14, R13
+			cmp		R14, 0x1E
+			jne		error
+			add		R14, 1
+
+			mov		R15, R14
+			cmp		R15, 0x1F
+			jne		error
+			add		R15, 1
+			
+			ret
+
+; -------------------------------------------------	
+; Instruction test
+; TST|R
+; CMP|R|K
+; JNZ|K
+; JC|K
+; JNE|K
+; JLT|K
+; JGT|K
+; JLE|K
+; JGE|K
+; JMP|K
+test1:		mov		R0, 0			; R0 <= 0
+			tst		R0
+			jnz		error	
+			jc		error	
+			cmp		R0, 0	
+			jne		error	
+			jlt		error	
+			jgt		error
+			jle		t1_ok10
+			jmp		error
+
+t1_ok10:	jeq		t1_ok20
+			jmp		error
+			
+t1_ok20:	jge		t1_ok30
+			jmp		error
+			
+t1_ok30:	cmp		R0, 0x55
+			jeq		error	
+			jlt		t1_ok40
+			jmp		error
+			
+t1_ok40:	jle		t1_ok50
+			jmp		error
+			
+t1_ok50:	jge		error
+			jgt		error
+			
+			mov		R0, 0x55		; R0 <= 0xAA
+			tst		R0
+			jz		error	
+			jc		error	
+			
+			cmp		R0, 0xAA
+			jeq		error	
+			jne		t1_ok60
+			jmp		error
+
+t1_ok60:	jlt		t1_ok70	
+			jmp		error
+
+t1_ok70:	jle		t1_ok80
+			jmp		error
+
+t1_ok80:	jgt		error
+
+			cmp		R0, 0x55
+			jeq		t1_ok90
+			jmp		error
+			
+t1_ok90:	jne		error
+			jlt		error
+			
+			jle		t1_ok100
+			jmp		error
+
+t1_ok100:	jgt		error
+			jge		t1_ok110
+			jmp		error
+			
+t1_ok110:	mov		R0, 0xAA		; R0 <= 0x55
+			tst		R0
+			jz		error	
+			jc		error	
+			
+			cmp		R0, 0x55
+			jeq		error	
+			jne		t1_ok120
+			jmp		error
+
+t1_ok120:	jgt		t1_ok130	
+			jmp		error
+
+t1_ok130:	jge		t1_ok140
+			jmp		error
+
+t1_ok140:	jlt		error
+			jle		error
+
+			ret
+			
+; -------------------------------------------------	
+; ADD|R|K
+; ADDC|R|K
+; ToDo: ADD|R|R
+; ToDo: ADDC|R|R
+; CMP|R|R
+test2:		mov		R0, 0
+			mov		R1, 0
+			mov		R2, R0
+			mov		R3, R1
+
+t2_loop:	add		R0, 0x01
+			addc	R1, 0x00
+			add		R2, 1
+			cmp		R2, 0
+			jne		t2_L1
+			add		R3, 1
+			cmp		R3, 0x02
+t2_L1:		jne		t2_loop
+			cmp		R0, R2
+			jne		error
+			cmp		R1, R3
+			jne		error
+			mov		R0, 0
+
+			ret
+
+; -------------------------------------------------	
+; SUB|R|K
+; SUBC|R|K
+; ToDo: SUB|R|R
+; ToDo: SUBC|R|R
+; CMP|R|R
+test3:		mov		R0, 0x00
+			mov		R1, 0x03
+			mov		R2, R0
+			mov		R3, R1
+
+t3_loop:	sub		R0, 0x01
+			subc	R1, 0x00
+			sub		R2, 1
+			cmp		R2, 0xFF
+			jne		t3_L1
+			sub		R3, 1
+			cmp		R3, 0x00
+t3_L1:		jne		t3_loop
+			cmp		R0, R2
+			jne		error
+			cmp		R1, R3
+			jne		error
+			mov		R0, 0
+
+			ret
+; -------------------------------------------------	
+; SUB|K|R
+; SUB|R|R
+; SUBC|R|R
+; SUBC|K|R
+; CMP|R|R
+test4:		mov		R0, 0x03
+			mov		R1, 0x05
+			sub		0x05, R0
+			sub		R1, 0x03
+			cmp		R0, R1
+			jne		error
+			mov		R0, 0x03
+			mov		R1, 0x05
+			sub		R0, R1
+			subc	0, R0
+			cmp		R0, 0x01
+			jne		error
+			add		R0, 0	
+			subc	R1, R0
+			cmp		R1, 0x04
+			jne		error
+			mov		R0, 0
+
+			ret
+						
+; -------------------------------------------------	
+; MOVC|R|Ri
+; MOVC|R|Ki
+; MOVC|Ri|R
+; MOVC|Ri|K
+; MOVC|Ki|R
+test5:		mov		R0, 1
+			movc	(cram+0x5A), R0
+			dec		R0			
+			movc	(cram+0), R0
+			movc	R1, (cram+0x5A)
+			movc	(R1), 0xA5
+			movc	R0, (R1)
+			movc	R1, (R1)
+			add		R1, 0xFF-0xA5
+			movc	R0, (R1)
+t5_loop1:	movc	(R0), R0
+			movc	R2, (R0)
+			cmp		R2, R0
+			jne		error
+			movc	(R2), R1
+			movc	R2, (R2)
+			cmp		R2, R1
+			jne		error
+			dec		R1
+			inc		R0
+			jnz		t5_loop1
+			
+			ret
+
+; -------------------------------------------------	
+; MOVX|R|Ri
+; MOVX|R|Ki
+; MOVX|Ri|R
+; MOVX|Ri|K
+; MOVX|Ki|R
+test6:		mov		R0, 1
+			movx	(xram+0x5A), R0
+			dec		R0			
+			movx	(xram+0), R0
+			movx	R1, (xram+0x5A)
+			movx	(R1), 0xA5
+			movx	R0, (R1)
+			movx	R1, (R1)
+			add		R1, 0xFF-0xA5
+			movx	R0, (R1)
+t6_loop1:	movx	(R0), R0
+			movx	R2, (R0)
+			cmp		R2, R0
+			jne		error
+			movx	(R2), R1
+			movx	R2, (R2)
+			cmp		R2, R1
+			jne		error
+			dec		R1
+			inc		R0
+			jnz		t6_loop1
+			
+			ret
+
+; -------------------------------------------------	
+; PUSH|R
+; POP|R
+test7:		mov		R0, 0xAA
+			mov		R1, 0
+t7_loop1:	push	R0
+			inc		R0
+			dec		R1
+			jnz		t7_loop1
+t7_loop2:	pop		R0
+			dec		R1
+			jnz		t7_loop2
+			cmp		R0, 0xAA
+			jne		error
+			
+			ret
+
+; -------------------------------------------------	
+; JMP|K
+; CALL|K
+; RET
+test8:		mov		R0, 0x55
+			push	R0
+			mov		R0, 0
+			mov		R1, 0xFF
+			call	t8_rec
+			pop		R0
+			cmp		R0, 0x55
+			jne		error
+
+			; Stack manipulations 1
+			mov		R0, return1'high
+			mov		R1, return1'low
+			cout	(cpu_stack_high), R0
+			push	R1
+
+			mov		R0, init'high
+			mov		R1, init'low
+			cout	(cpu_stack_high), R0
+			push	R1
+			ret
+			
+			; Stack manipulations 2
+return1:	mov		R0, return2'high
+			mov		R1, return2'low
+			cout	(cpu_stack_high), R0
+			push	R1
+
+			mov		R0, init'high
+			mov		R1, init'low
+			cout	(cpu_stack_high), R0
+			push	R1
+return2:	ret
+
+t8_rec:		cmp		R0, R1
+			jeq		ex_t8_rec
+			inc		R0
+			jmp		t8_rstub
+ex_t8_rec:	dec		R0
+			dec		R1
+			ret
+
+t8_rstub:	call	t8_rec
+			jmp		ex_t8_rec
+
+; -------------------------------------------------	
+; SWAP|R
+; SHL|R  
+; SHR|R  
+; ROL|R  
+; ROR|R  
+; ROLC|R 
+; RORC|R 
+test9:		mov		R0, 0xA5	; SWAP test
+			mov		R1, 0x5A
+			swap	R0
+			cmp		R0, 0x5A
+			jne		error
+			swap	R0
+			cmp		R0, 0xA5
+			jne		error
+			mov		R0, 0xD2
+			swap	R0
+			cmp		R0, 0x2D
+			jne		error
+			swap	R1
+			cmp		R0, 0x2D
+			jne		error
+			cmp		R1, 0xA5
+			jne		error
+			
+			mov		R0, 0x2D
+			shl		R0			; SHL test
+			cmp		R0, 0x5A
+			jne		error
+			shl		R0
+			cmp		R0, 0xB4
+			jne		error
+			shl		R0
+			cmp		R0, 0x68
+			jne		error
+			shl		R0
+			cmp		R0, 0xD0
+			jne		error
+			shl		R0
+			cmp		R0, 0xA0
+			jne		error
+			shl		R0
+			cmp		R0, 0x40
+			jne		error
+			shl		R0
+			cmp		R0, 0x80
+			jne		error
+			shl		R0
+			cmp		R0, 0x00
+			jne		error
+
+			mov		R1, 0x84
+			shr		R1			; SHR test
+			cmp		R1, 0x42
+			jne		error
+			shr		R1
+			cmp		R1, 0x21
+			jne		error
+			shr		R1
+			cmp		R1, 0x10
+			jne		error
+			shr		R1
+			cmp		R1, 0x08
+			jne		error
+			shr		R1
+			cmp		R1, 0x04
+			jne		error
+			shr		R1
+			cmp		R1, 0x02
+			jne		error
+			shr		R1
+			cmp		R1, 0x01
+			jne		error
+			shr		R1
+			cmp		R1, 0x00
+			jne		error
+
+			mov		R0, 0xC5	; ROL test
+			rol		R0			
+			cmp		R0, 0x8B
+			jne		error
+			rol		R0			
+			cmp		R0, 0x17
+			jne		error
+			rol		R0			
+			cmp		R0, 0x2E
+			jne		error
+			rol		R0			
+			cmp		R0, 0x5C
+			jne		error
+			rol		R0			
+			cmp		R0, 0xB8
+			jne		error
+			rol		R0			
+			cmp		R0, 0x71
+			jne		error
+			rol		R0			
+			cmp		R0, 0xE2
+			jne		error
+			rol		R0			
+			cmp		R0, 0xC5
+			jne		error
+
+			mov		R1, 0x63	; ROR test
+			ror		R1
+			cmp		R1, 0xB1
+			jne		error
+			ror		R1
+			cmp		R1, 0xD8
+			jne		error
+			ror		R1
+			cmp		R1, 0x6C
+			jne		error
+			ror		R1
+			cmp		R1, 0x36
+			jne		error
+			ror		R1
+			cmp		R1, 0x1B
+			jne		error
+			ror		R1
+			cmp		R1, 0x8D
+			jne		error
+			ror		R1
+			cmp		R1, 0xC6
+			jne		error
+			ror		R1
+			cmp		R1, 0x63
+			jne		error
+
+
+			xor		R0, R0		; ROLC generate
+			mov		R0, 0xC5	
+			rolc	R0		
+			push	R0
+			rolc	R0			
+			push	R0
+			rolc	R0			
+			push	R0
+			rolc	R0			
+			push	R0
+			rolc	R0			
+			push	R0
+			rolc	R0			
+			push	R0
+			rolc	R0			
+			push	R0
+			rolc	R0			
+			push	R0
+			rolc	R0			
+
+			cmp		R0, 0xC5	; ROLC verify
+			jne		error
+			pop		R0
+			cmp		R0, 0x62
+			jne		error
+			pop		R0
+			cmp		R0, 0xB1
+			jne		error
+			pop		R0
+			cmp		R0, 0x58
+			jne		error
+			pop		R0
+			cmp		R0, 0xAC
+			jne		error
+			pop		R0
+			cmp		R0, 0x56
+			jne		error
+			pop		R0
+			cmp		R0, 0x2B
+			jne		error
+			pop		R0
+			cmp		R0, 0x15
+			jne		error
+			pop		R0
+			cmp		R0, 0x8A
+			jne		error
+
+			xor		R1, R1		; RORC generate
+			mov		R1, 0x63
+			rorc	R1
+			push	R1
+			rorc	R1
+			push	R1
+			rorc	R1
+			push	R1
+			rorc	R1
+			push	R1
+			rorc	R1
+			push	R1
+			rorc	R1
+			push	R1
+			rorc	R1
+			push	R1
+			rorc	R1
+			push	R1
+			rorc	R1
+
+			cmp		R1, 0x63	; RORC verify
+			jne		error
+			pop		R1
+			cmp		R1, 0xC6
+			jne		error
+			pop		R1
+			cmp		R1, 0x8C
+			jne		error
+			pop		R1
+			cmp		R1, 0x19
+			jne		error
+			pop		R1
+			cmp		R1, 0x33
+			jne		error
+			pop		R1
+			cmp		R1, 0x66
+			jne		error
+			pop		R1
+			cmp		R1, 0xCC
+			jne		error
+			pop		R1
+			cmp		R1, 0x98
+			jne		error
+			pop		R1
+			cmp		R1, 0x31
+			jne		error
+
+			ret
+			
+; -------------------------------------------------
+; AND|R|R
+; AND|R|K
+; OR|R|R 
+; OR|R|K 
+; XOR|R|R
+; XOR|R|K
+test10:		mov		R0, 0xA5	; AND
+			swap	R0
+			push	R0
+			and		R0, 0x0F
+			cmp		R0, 0x0A
+			jne		error
+			pop		R0
+			push	R0
+			and		R0, 0x0F
+			cmp		R0, 0x0A
+			pop		R1
+			jne		error
+			swap	R1
+			mov		R2, 0x0F
+			and		R1, R2
+			cmp		R1, 0x05
+			jne		error
+			
+			mov		R0, 0x05	; OR
+			mov		R2, 0xA0
+			swap	R0
+			or		R2, R0
+			cmp		R2, 0xF0
+			jne		error
+			swap	R0
+			or		R0, 0x50
+			cmp		R0, 0x55
+			jne		error
+			
+			mov		R1, 0x01
+			mov		R0, 0x01
+			xor		R0, 0x01
+			jnz		error
+			xor		R0, R1
+			cmp		R0, 0x01
+			jne		error
+			
+			ret
+			
+; -------------------------------------------------	
+test11:
+			mov		R0, 0x03
+			cout	(cpu_int_ctrl), R0
+			
+			xin		R0, (2)
+			or		R0, 1
+			xout	(2), R0
+			nop
+			nop
+			nop
+			nop
+			nop
+			nop
+			xin		R0, (2)
+			and		R0, 0xFE
+			xout	(2), R0
+			nop
+			nop
+			nop
+			nop
+			
+			cin		R0, (cpu_int_ctrl)
+			or		R0, 0x80
+			cout	(cpu_int_ctrl), R0
+			nop
+			cin		R0, (cpu_int_ctrl)
+			or		R0, 0x80
+			cout	(cpu_int_ctrl), R0
+			nop
+			cin		R0, (cpu_int_ctrl)
+			or		R0, 0x80
+			cout	(cpu_int_ctrl), R0
+			nop
+			cin		R0, (cpu_int_ctrl)
+			or		R0, 0x80
+			cout	(cpu_int_ctrl), R0
+			nop
+			nop
+			nop
+			nop
+			nop
+			nop
+			nop
+			nop
+			nop
+			ret
+
+; -------------------------------------------------	
+; Tests clrc, setc
+test12:		sub		R0, 0
+			jc		error
+			setc
+			jnc		error
+			nop
+			sub		R0, 0
+			jc		error
+			
+			mov		R0, 0
+			clrc
+			jc		error
+			setc
+			jnc		error
+			nop
+			clrc
+			jc		error
+			ret
+
+; -------------------------------------------------	
+isr:		inc		R14
+			reti
+
+; -------------------------------------------------	
+			org		0x3FF
+error:		jmp		error
+
+; -------------------------------------------------	
+			org		0x2FF
+ok:			jmp		ok
+
+; -------------------------------------------------	
+			

lib/CPUs/JCpu/asm/make

@@ -0,0 +1,50 @@
+#!/bin/sh
+
+# ----------------------------------------------------------------------
+# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+# This file: rom-file generation for cpu_core
+#
+# Copyright (C) 2007 J. Ahrensfeld
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+# 
+# For questions and ideas, please contact the author at jens@jayfield.org
+#
+# ---------------------------------------------------------------------
+
+TARGET=$2
+DSTDIR=$1
+
+JASM_HOME=/cygdrive/w/vhdl/lib/CPUs/JCpu/tools
+
+$JASM_HOME/jasm.rb $TARGET.jsm
+
+irom_tcl_snippet="$TARGET.irom.tcl.snip"
+irom_vhdl_snippet="$TARGET.irom.vhdl.snip"
+irom_ld_vhdl_snippet="$TARGET.irom_ld.vhdl.snip"
+xrom_tcl_snippet="$TARGET.xrom.tcl.snip"
+xrom_vhdl_snippet="$TARGET.xrom.vhdl.snip"
+xrom_ld_vhdl_snippet="$TARGET.xrom_ld.vhdl.snip"
+
+$JASM_HOME/insrom.rb $irom_vhdl_snippet $JASM_HOME/irom.vhd.tpl >$DSTDIR/$TARGET\_irom.vhdl
+$JASM_HOME/insrom.rb $irom_ld_vhdl_snippet $JASM_HOME/irom_ld.vhd.tpl >$DSTDIR/$TARGET\_irom_ld.vhdl
+
+$JASM_HOME/insrom.rb $xrom_vhdl_snippet $JASM_HOME/xrom.vhd.tpl >$DSTDIR/$TARGET\_xrom.vhdl
+$JASM_HOME/insrom.rb $xrom_ld_vhdl_snippet $JASM_HOME/xrom_ld.vhd.tpl >$DSTDIR/$TARGET\_xrom_ld.vhdl
+
+cat $irom_tcl_snippet > $TARGET.tcl.snip.snip
+cat $xrom_tcl_snippet >> $TARGET.tcl.snip.snip
+$JASM_HOME/insrom.rb $TARGET.tcl.snip.snip $JASM_HOME/rom.tcl.tpl >$TARGET.tcl
+
+rm -f *.snip

lib/CPUs/JCpu/asm/mul8x8.jsm

@@ -0,0 +1,29 @@
+; -------------------------------------------------
+; Constants
+; -------------------------------------------------
+
+; Chip register
+include "../../../jasm/cregs.inc.jsm"
+
+; -------------------------------------------------
+; Program
+; -------------------------------------------------
+				code
+				org		0x000
+reset:			jmp		init
+						
+; -------------------------------------------------
+; Main
+; -------------------------------------------------
+init:			mov		R0, 0x45
+				mov		R1, 0xF5
+				
+				call	mul8x8
+stop:			jmp		stop
+
+
+; -------------------------------------------------
+include "../../../jasm/mul8x8.inc.jsm"
+				
+				
+				

lib/CPUs/JCpu/asm/mul8x8.tcl

@@ -0,0 +1,154 @@
+# ----------------------------------------------------------------------
+# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+# This file: The ROM file for upload to target over JTAG 
+#
+# Copyright (C) 2007 J. Ahrensfeld
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+# 
+# For questions and ideas, please contact the author at jens@jayfield.org
+#
+# ---------------------------------------------------------------------
+
+# ---------------------------------------------------------------------
+# For Chipscope 9.1
+# ---------------------------------------------------------------------
+# Source JTAG/TCL frame work
+cd $env(CHIPSCOPE)\\bin\\nt
+source csejtag.tcl
+
+namespace import ::chipscope::*
+
+# Platform USB Cable
+set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"]
+# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
+
+# Create session
+set handle [::chipscope::csejtag_session create 0]
+
+# Open JTAG and lock
+set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
+set lock_result [::chipscope::csejtag_target lock $handle 1000]
+
+set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
+
+# Get Device ID
+set devtype "Virtex-4SX"
+set devid 2
+set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
+set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
+
+set CSE_OP $CSEJTAG_SHIFT_READWRITE
+set CSE_ES $CSEJTAG_RUN_TEST_IDLE
+
+# Write Program
+# JASM_ROM_INSERT_HERE
+# Assembled from mul8x8.jsm
+# ---------------------------------------------------------------
+# Shift the USER2 Instruction (b1111000010) into the Instruction Register of FPGA
+# User 1
+set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C2"]
+
+# 0x000: JMP 0x001
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00030001"
+
+# 0x001: MOV R00, 0x45
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00103450"
+
+# 0x002: MOV R01, 0xF5
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00203F51"
+
+# 0x003: CALL 0x005
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0033B005"
+
+# 0x004: JMP 0x004
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00430004"
+
+# 0x005: PUSH R02
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0053C002"
+
+# 0x006: PUSH R03
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0063C003"
+
+# 0x007: PUSH R04
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0073C004"
+
+# 0x008: MOV R04, R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00802014"
+
+# 0x009: MOV R01, 0x00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00903001"
+
+# 0x00A: MOV R02, 0x00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00A03002"
+
+# 0x00B: MOV R03, 0x00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00B03003"
+
+# 0x00C: CMP R04, 0x01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00C0F014"
+
+# 0x00D: JEQ 0x015
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00D39015"
+
+# 0x00E: SHR R04
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00E1F004"
+
+# 0x00F: JNC 0x012
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00F34012"
+
+# 0x010: ADD R02, R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01010002"
+
+# 0x011: ADDC R03, R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01112013"
+
+# 0x012: SHL R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0121E000"
+
+# 0x013: ROLC R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01322001"
+
+# 0x014: JMP 0x00C
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0143000C"
+
+# 0x015: ADD R00, R02
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01510020"
+
+# 0x016: ADDC R01, R03
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01612031"
+
+# 0x017: POP R04
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0173D004"
+
+# 0x018: POP R03
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0183D003"
+
+# 0x019: POP R02
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0193D002"
+
+# 0x01A: RET
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01A3E000"
+
+# Assembled from mul8x8.jsm
+# ---------------------------------------------------------------
+# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA
+# User 2
+set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C3"]
+
+
+::chipscope::csejtag_target unlock $handle
+::chipscope::csejtag_target close $handle
+::chipscope::csejtag_session destroy $handle
+exit

lib/CPUs/JCpu/asm/reti_issue.jsm

@@ -0,0 +1,50 @@
+; -------------------------------------------------
+; Constants
+; -------------------------------------------------
+
+; Chip register
+cpu_revision:	equ		0x00	; RO
+cpu_control:	equ		0x01	; R/W
+cpu_status:		equ		0x02	; RO
+cpu_int_ctrl:	equ		0x03	; R/W
+
+; -------------------------------------------------
+; Program
+; -------------------------------------------------
+				code
+reset:			jmp		init
+		
+				org		0x001
+;				nop
+				reti
+				
+; -------------------------------------------------
+; Main
+; -------------------------------------------------
+init:			mov		R0, 0x05
+				cout	(cpu_int_ctrl), R0
+				mov		R0, 0x00
+loop:			nop
+				inc		R0
+				nop
+				call	subr
+				nop
+				push	R3
+				nop
+				push	R2
+				nop
+				push	R1
+				nop
+				push	R0
+				nop
+				pop		R0
+				nop
+				pop		R1
+				nop
+				pop		R2
+				nop
+				pop		R3
+				nop
+				jmp		loop
+
+subr:			ret				

lib/CPUs/JCpu/asm/reti_issue.tcl

@@ -0,0 +1,157 @@
+# ----------------------------------------------------------------------
+# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+# This file: The ROM file for upload to target over JTAG 
+#
+# Copyright (C) 2007 J. Ahrensfeld
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+# 
+# For questions and ideas, please contact the author at jens@jayfield.org
+#
+# ---------------------------------------------------------------------
+
+# ---------------------------------------------------------------------
+# For Chipscope 9.1
+# ---------------------------------------------------------------------
+# Source JTAG/TCL frame work
+cd $env(CHIPSCOPE)\\bin\\nt
+source csejtag.tcl
+
+namespace import ::chipscope::*
+
+# Platform USB Cable
+set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"]
+# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
+
+# Create session
+set handle [::chipscope::csejtag_session create 0]
+
+# Open JTAG and lock
+set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
+set lock_result [::chipscope::csejtag_target lock $handle 1000]
+
+set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
+
+# Get Device ID
+set devtype "Virtex-4SX"
+set devid 2
+set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
+set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
+
+set CSE_OP $CSEJTAG_SHIFT_READWRITE
+set CSE_ES $CSEJTAG_RUN_TEST_IDLE
+
+# Write Program
+# JASM_ROM_INSERT_HERE
+# Assembled from reti_issue.jsm
+# ---------------------------------------------------------------
+# Shift the USER2 Instruction (b1111000010) into the Instruction Register of FPGA
+# User 1
+set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C2"]
+
+# 0x000: JMP 0x002
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00030002"
+
+# 0x001: RETI
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0013F000"
+
+# 0x002: MOV R00, 0x05
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00203050"
+
+# 0x003: COUT (0x03), R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00326030"
+
+# 0x004: MOV R00, 0x00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00403000"
+
+# 0x005: NOP
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00500000"
+
+# 0x006: INC R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00611010"
+
+# 0x007: NOP
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00700000"
+
+# 0x008: CALL 0x01B
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0083B01B"
+
+# 0x009: NOP
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00900000"
+
+# 0x00A: PUSH R03
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00A3C003"
+
+# 0x00B: NOP
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00B00000"
+
+# 0x00C: PUSH R02
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00C3C002"
+
+# 0x00D: NOP
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00D00000"
+
+# 0x00E: PUSH R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00E3C001"
+
+# 0x00F: NOP
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00F00000"
+
+# 0x010: PUSH R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0103C000"
+
+# 0x011: NOP
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01100000"
+
+# 0x012: POP R00
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0123D000"
+
+# 0x013: NOP
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01300000"
+
+# 0x014: POP R01
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0143D001"
+
+# 0x015: NOP
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01500000"
+
+# 0x016: POP R02
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0163D002"
+
+# 0x017: NOP
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01700000"
+
+# 0x018: POP R03
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0183D003"
+
+# 0x019: NOP
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01900000"
+
+# 0x01A: JMP 0x005
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01A30005"
+
+# 0x01B: RET
+::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01B3E000"
+
+# Assembled from reti_issue.jsm
+# ---------------------------------------------------------------
+# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA
+# User 2
+set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C3"]
+
+
+::chipscope::csejtag_target unlock $handle
+::chipscope::csejtag_target close $handle
+::chipscope::csejtag_session destroy $handle
+exit

lib/CPUs/JCpu/gpl-3.0.txt

@@ -0,0 +1,674 @@
+                    GNU GENERAL PUBLIC LICENSE
+                       Version 3, 29 June 2007
+
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+patent license for this particular work, or (3) arrange, in a manner
+consistent with the requirements of this License, to extend the patent
+license to downstream recipients.  "Knowingly relying" means you have
+actual knowledge that, but for the patent license, your conveying the
+covered work in a country, or your recipient's use of the covered work
+in a country, would infringe one or more identifiable patents in that
+country that you have reason to believe are valid.
+
+  If, pursuant to or in connection with a single transaction or
+arrangement, you convey, or propagate by procuring conveyance of, a
+covered work, and grant a patent license to some of the parties
+receiving the covered work authorizing them to use, propagate, modify
+or convey a specific copy of the covered work, then the patent license
+you grant is automatically extended to all recipients of the covered
+work and works based on it.
+
+  A patent license is "discriminatory" if it does not include within
+the scope of its coverage, prohibits the exercise of, or is
+conditioned on the non-exercise of one or more of the rights that are
+specifically granted under this License.  You may not convey a covered
+work if you are a party to an arrangement with a third party that is
+in the business of distributing software, under which you make payment
+to the third party based on the extent of your activity of conveying
+the work, and under which the third party grants, to any of the
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+conveyed by you (or copies made from those copies), or (b) primarily
+for and in connection with specific products or compilations that
+contain the covered work, unless you entered into that arrangement,
+or that patent license was granted, prior to 28 March 2007.
+
+  Nothing in this License shall be construed as excluding or limiting
+any implied license or other defenses to infringement that may
+otherwise be available to you under applicable patent law.
+
+  12. No Surrender of Others' Freedom.
+
+  If conditions are imposed on you (whether by court order, agreement or
+otherwise) that contradict the conditions of this License, they do not
+excuse you from the conditions of this License.  If you cannot convey a
+covered work so as to satisfy simultaneously your obligations under this
+License and any other pertinent obligations, then as a consequence you may
+not convey it at all.  For example, if you agree to terms that obligate you
+to collect a royalty for further conveying from those to whom you convey
+the Program, the only way you could satisfy both those terms and this
+License would be to refrain entirely from conveying the Program.
+
+  13. Use with the GNU Affero General Public License.
+
+  Notwithstanding any other provision of this License, you have
+permission to link or combine any covered work with a work licensed
+under version 3 of the GNU Affero General Public License into a single
+combined work, and to convey the resulting work.  The terms of this
+License will continue to apply to the part which is the covered work,
+but the special requirements of the GNU Affero General Public License,
+section 13, concerning interaction through a network will apply to the
+combination as such.
+
+  14. Revised Versions of this License.
+
+  The Free Software Foundation may publish revised and/or new versions of
+the GNU General Public License from time to time.  Such new versions will
+be similar in spirit to the present version, but may differ in detail to
+address new problems or concerns.
+
+  Each version is given a distinguishing version number.  If the
+Program specifies that a certain numbered version of the GNU General
+Public License "or any later version" applies to it, you have the
+option of following the terms and conditions either of that numbered
+version or of any later version published by the Free Software
+Foundation.  If the Program does not specify a version number of the
+GNU General Public License, you may choose any version ever published
+by the Free Software Foundation.
+
+  If the Program specifies that a proxy can decide which future
+versions of the GNU General Public License can be used, that proxy's
+public statement of acceptance of a version permanently authorizes you
+to choose that version for the Program.
+
+  Later license versions may give you additional or different
+permissions.  However, no additional obligations are imposed on any
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+  15. Disclaimer of Warranty.
+
+  THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY
+APPLICABLE LAW.  EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT
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+  16. Limitation of Liability.
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+EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF
+SUCH DAMAGES.
+
+  17. Interpretation of Sections 15 and 16.
+
+  If the disclaimer of warranty and limitation of liability provided
+above cannot be given local legal effect according to their terms,
+reviewing courts shall apply local law that most closely approximates
+an absolute waiver of all civil liability in connection with the
+Program, unless a warranty or assumption of liability accompanies a
+copy of the Program in return for a fee.
+
+                     END OF TERMS AND CONDITIONS
+
+            How to Apply These Terms to Your New Programs
+
+  If you develop a new program, and you want it to be of the greatest
+possible use to the public, the best way to achieve this is to make it
+free software which everyone can redistribute and change under these terms.
+
+  To do so, attach the following notices to the program.  It is safest
+to attach them to the start of each source file to most effectively
+state the exclusion of warranty; and each file should have at least
+the "copyright" line and a pointer to where the full notice is found.
+
+    <one line to give the program's name and a brief idea of what it does.>
+    Copyright (C) <year>  <name of author>
+
+    This program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+Also add information on how to contact you by electronic and paper mail.
+
+  If the program does terminal interaction, make it output a short
+notice like this when it starts in an interactive mode:
+
+    <program>  Copyright (C) <year>  <name of author>
+    This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+    This is free software, and you are welcome to redistribute it
+    under certain conditions; type `show c' for details.
+
+The hypothetical commands `show w' and `show c' should show the appropriate
+parts of the General Public License.  Of course, your program's commands
+might be different; for a GUI interface, you would use an "about box".
+
+  You should also get your employer (if you work as a programmer) or school,
+if any, to sign a "copyright disclaimer" for the program, if necessary.
+For more information on this, and how to apply and follow the GNU GPL, see
+<http://www.gnu.org/licenses/>.
+
+  The GNU General Public License does not permit incorporating your program
+into proprietary programs.  If your program is a subroutine library, you
+may consider it more useful to permit linking proprietary applications with
+the library.  If this is what you want to do, use the GNU Lesser General
+Public License instead of this License.  But first, please read
+<http://www.gnu.org/philosophy/why-not-lgpl.html>.

lib/CPUs/JCpu/sim/tb_cpu.fdo

@@ -0,0 +1,22 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+vcom -explicit  -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
+vcom -explicit  -93 "../src/core/cpu_pkg.vhd"
+vcom -explicit  -93 "../src/core/stack_ctrl.vhd"
+vcom -explicit  -93 "../src/core/reg_dual.vhd"
+vcom -explicit  -93 "../src/core/chipram.vhd"
+vcom -explicit  -93 "../src/core/chipreg.vhd"
+vcom -explicit  -93 "../src/core/pc.vhd"
+vcom -explicit  -93 "../src/core/dpath_ctrl.vhd"
+vcom -explicit  -93 "../src/core/int_ctrl.vhd"
+vcom -explicit  -93 "../src/core/alu.vhd"
+vcom -explicit  -93 "../src/core/cpu.vhd"
+vcom -explicit  -93 "../src/test_irom.vhdl"
+vcom -explicit  -93 "../src/core/tb_cpu.vhd"
+vsim -t 1ps   -lib work tb_cpu
+do {tb_cpu.wdo}
+view wave
+view structure
+view signals
+run 50us

lib/CPUs/JCpu/sim/tb_cpu.wdo

@@ -0,0 +1,107 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_cpu/rst
+add wave -noupdate -format Logic /tb_cpu/clk
+add wave -noupdate -format Logic /tb_cpu/ce
+add wave -noupdate -format Logic /tb_cpu/uut/cpu_active
+add wave -noupdate -format Logic /tb_cpu/int_in
+add wave -noupdate -format Logic /tb_cpu/int_ack
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/irom_data
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/irom_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_dout
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_addr
+add wave -noupdate -format Logic /tb_cpu/xmem_we
+add wave -noupdate -format Logic /tb_cpu/xmem_re
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/sram
+add wave -noupdate -format Logic /tb_cpu/uut/io_sel
+add wave -noupdate -format Literal /tb_cpu/uut/iphase
+add wave -noupdate -divider CPU
+add wave -noupdate -format Literal /tb_cpu/reg
+add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
+add wave -noupdate -format Literal /tb_cpu/uut/cpu_status
+add wave -noupdate -format Literal /tb_cpu/uut/status_reg
+add wave -noupdate -format Literal /tb_cpu/uut/ctrl
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_out
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_reg
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/pc_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/pc_next
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/idata
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/int_pc_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/iphase
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/const_data
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_a_dout
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_b_dout
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_op1
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_op2
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_result
+add wave -noupdate -format Literal /tb_cpu/uut/alu_status
+add wave -noupdate -format Logic /tb_cpu/uut/pc_inc
+add wave -noupdate -format Logic /tb_cpu/uut/pc_load
+add wave -noupdate -format Logic /tb_cpu/uut/stk_we
+add wave -noupdate -format Logic /tb_cpu/uut/cmem_we
+add wave -noupdate -format Literal /tb_cpu/uut/ctrl_iphase
+add wave -noupdate -format Logic /tb_cpu/uut/was_pcld
+add wave -noupdate -format Logic /tb_cpu/uut/was_pop2pc
+add wave -noupdate -format Logic /tb_cpu/uut/int_pc_load
+add wave -noupdate -format Logic /tb_cpu/uut/int_stk_push
+add wave -noupdate -format Logic /tb_cpu/uut/stk_push
+add wave -noupdate -format Logic /tb_cpu/uut/stk_pop
+add wave -noupdate -format Logic /tb_cpu/uut/status_save
+add wave -noupdate -format Logic /tb_cpu/uut/status_restore
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_ptr
+add wave -noupdate -divider Stack
+add wave -noupdate -format Logic /tb_cpu/clk
+add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
+add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/push
+add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/pop
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/din
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/dout
+add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/mem_we
+add wave -noupdate -divider Chipram
+add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_a
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_a
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_a
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_a
+add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_b
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_b
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_b
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_b
+add wave -noupdate -divider Sequencer
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/inst_in
+add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/iphase_in
+add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/status_in
+add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/ctrl_out
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/idout
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/ddout
+add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/opcode
+add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/ctrl_lines
+add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_cpu/uut/inst_reg_ab/mem
+add wave -noupdate -divider {Chip register}
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/creg_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/creg_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/creg_dout
+add wave -noupdate -format Literal /tb_cpu/uut/creg_ctrl_out
+add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
+add wave -noupdate -format Logic /tb_cpu/clk
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_exit
+add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/int_state
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {136355 ps} 0}
+configure wave -namecolwidth 166
+configure wave -valuecolwidth 101
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+update
+WaveRestoreZoom {93532 ps} {206468 ps}

lib/CPUs/JCpu/sim/tb_cpu_embedded.fdo

@@ -0,0 +1,21 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+vcom -explicit  -93 "../src/core/cpu_pkg.vhd"
+vcom -explicit  -93 "../src/core/stack_ctrl.vhd"
+vcom -explicit  -93 "../src/core/reg_dual.vhd"
+vcom -explicit  -93 "../src/core/chipram.vhd"
+vcom -explicit  -93 "../src/core/pc.vhd"
+vcom -explicit  -93 "../src/core/dpath_ctrl.vhd"
+vcom -explicit  -93 "../src/core/int_ctrl.vhd"
+vcom -explicit  -93 "../src/core/alu.vhd"
+vcom -explicit  -93 "../src/core/cpu.vhd"
+vcom -explicit  -93 "../src/cpu_embedded.vhd"
+vcom -explicit  -93 "../src/tb_cpu_embedded.vhd"
+vcom -explicit  -93 "../src/test_irom.vhdl"
+vsim -t 1ps   -lib work tb_cpu_embedded
+do {tb_cpu_embedded.wdo}
+view wave
+view structure
+view signals
+run 10us

lib/CPUs/JCpu/sim/tb_cpu_embedded.wdo

@@ -0,0 +1,26 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_cpu_embedded/rst
+add wave -noupdate -format Logic /tb_cpu_embedded/clk
+add wave -noupdate -format Logic /tb_cpu_embedded/ce
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/sram
+add wave -noupdate -format Logic /tb_cpu_embedded/int_in
+add wave -noupdate -format Logic /tb_cpu_embedded/int_ack
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/rom_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/rom_data
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {2168142 ps} 0}
+configure wave -namecolwidth 143
+configure wave -valuecolwidth 101
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+update
+WaveRestoreZoom {0 ps} {10500 ns}

lib/CPUs/JCpu/sim/tb_cpu_itest.fdo

@@ -0,0 +1,22 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+vcom -explicit  -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
+vcom -explicit  -93 "../src/core/cpu_pkg.vhd"
+vcom -explicit  -93 "../src/core/stack_ctrl.vhd"
+vcom -explicit  -93 "../src/core/reg_dual.vhd"
+vcom -explicit  -93 "../src/core/chipram.vhd"
+vcom -explicit  -93 "../src/core/chipreg.vhd"
+vcom -explicit  -93 "../src/core/pc.vhd"
+vcom -explicit  -93 "../src/core/dpath_ctrl.vhd"
+vcom -explicit  -93 "../src/core/int_ctrl.vhd"
+vcom -explicit  -93 "../src/core/alu.vhd"
+vcom -explicit  -93 "../src/core/cpu.vhd"
+vcom -explicit  -93 "../src/itest_irom.vhdl"
+vcom -explicit  -93 "../src/tb_cpu_itest.vhd"
+vsim -t 1ps   -lib work tb_cpu
+do {tb_cpu_itest.wdo}
+view wave
+view structure
+view signals
+run 400us

lib/CPUs/JCpu/sim/tb_cpu_itest.wdo

@@ -0,0 +1,123 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_cpu/rst
+add wave -noupdate -format Logic /tb_cpu/clk
+add wave -noupdate -format Logic /tb_cpu/ce
+add wave -noupdate -format Logic /tb_cpu/int_in
+add wave -noupdate -format Logic /tb_cpu/int_ack
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/irom_data
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/irom_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_dout
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_addr
+add wave -noupdate -format Logic /tb_cpu/xmem_we
+add wave -noupdate -format Logic /tb_cpu/xmem_re
+add wave -noupdate -format Logic /tb_cpu/xmem_wait
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/sram
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_cpu/reg
+add wave -noupdate -format Logic /tb_cpu/uut/io_sel
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/mem_data
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/mem_addr
+add wave -noupdate -divider CPU
+add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
+add wave -noupdate -format Literal /tb_cpu/uut/cpu_status
+add wave -noupdate -format Literal /tb_cpu/uut/status_reg
+add wave -noupdate -format Literal /tb_cpu/uut/ctrl
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_out
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_reg
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/pc_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/pc_next
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/idata
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/int_pc_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/iphase
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/const_data
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_a_dout
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_b_dout
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_op1
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_op2
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_result
+add wave -noupdate -format Literal /tb_cpu/uut/alu_status
+add wave -noupdate -format Logic /tb_cpu/uut/pc_inc
+add wave -noupdate -format Logic /tb_cpu/uut/pc_load
+add wave -noupdate -format Logic /tb_cpu/uut/cpu_active
+add wave -noupdate -format Logic /tb_cpu/uut/stk_we
+add wave -noupdate -format Logic /tb_cpu/uut/cmem_we
+add wave -noupdate -format Literal /tb_cpu/uut/ctrl_iphase
+add wave -noupdate -format Logic /tb_cpu/uut/was_pcld
+add wave -noupdate -format Logic /tb_cpu/uut/was_pop2pc
+add wave -noupdate -format Logic /tb_cpu/uut/int_pc_load
+add wave -noupdate -format Logic /tb_cpu/uut/int_stk_push
+add wave -noupdate -format Logic /tb_cpu/uut/stk_push
+add wave -noupdate -format Logic /tb_cpu/uut/stk_pop
+add wave -noupdate -format Logic /tb_cpu/uut/status_save
+add wave -noupdate -format Logic /tb_cpu/uut/status_restore
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_ptr
+add wave -noupdate -divider Stack
+add wave -noupdate -format Logic /tb_cpu/clk
+add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
+add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/push
+add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/pop
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/din
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/dout
+add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/mem_we
+add wave -noupdate -divider Chipram
+add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_a
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_a
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_a
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_a
+add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_b
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_b
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_b
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_b
+add wave -noupdate -divider Sequencer
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/reg
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/inst_in
+add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/iphase_in
+add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/status_in
+add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/ctrl_out
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/idout
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/ddout
+add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/opcode
+add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/ctrl_lines
+add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_cpu/uut/inst_reg_ab/mem
+add wave -noupdate -divider {Chip register}
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/creg_dout
+add wave -noupdate -format Literal /tb_cpu/uut/creg_ctrl_out
+add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
+add wave -noupdate -format Logic /tb_cpu/clk
+add wave -noupdate -divider {Interrup Ctrl.}
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_in
+add wave -noupdate -format Literal -expand /tb_cpu/uut/inst_int_ctrl/ctrl_in
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_sampled
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_request
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_ack
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_exit
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_ack_out
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stat_save_out
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stat_rest_out
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/pc_load_out
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_push_out
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_pop_out
+add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/int_state
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/pc_load
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_push
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_pop
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {53866171 ps} 0}
+configure wave -namecolwidth 166
+configure wave -valuecolwidth 101
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+update
+WaveRestoreZoom {0 ps} {420 us}

lib/CPUs/JCpu/sim/tb_cpu_reti_issue.fdo

@@ -0,0 +1,22 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+vcom -explicit  -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
+vcom -explicit  -93 "../src/core/cpu_pkg.vhd"
+vcom -explicit  -93 "../src/core/stack_ctrl.vhd"
+vcom -explicit  -93 "../src/core/reg_dual.vhd"
+vcom -explicit  -93 "../src/core/chipram.vhd"
+vcom -explicit  -93 "../src/core/chipreg.vhd"
+vcom -explicit  -93 "../src/core/pc.vhd"
+vcom -explicit  -93 "../src/core/dpath_ctrl.vhd"
+vcom -explicit  -93 "../src/core/int_ctrl.vhd"
+vcom -explicit  -93 "../src/core/alu.vhd"
+vcom -explicit  -93 "../src/core/cpu.vhd"
+vcom -explicit  -93 "../src/irom_reti_issue.vhdl"
+vcom -explicit  -93 "../src/core/tb_cpu.vhd"
+vsim -t 1ps   -lib work tb_cpu
+do {tb_cpu_reti_issue.wdo}
+view wave
+view structure
+view signals
+run 50us

lib/CPUs/JCpu/sim/tb_cpu_reti_issue.wdo

@@ -0,0 +1,82 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Literal /tb_cpu/uut/iphase
+add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/ctrl_lines
+add wave -noupdate -divider {Chip RAM}
+add wave -noupdate -format Literal /tb_cpu/uut/iphase
+add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
+add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/clka
+add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/clkb
+add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/en_a
+add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/en_b
+add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_a
+add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_b
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_a
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_b
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_a
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_b
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_a
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_b
+add wave -noupdate -divider {Interrupt controller}
+add wave -noupdate -format Literal /tb_cpu/uut/iphase
+add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/rst
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/clk
+add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/ctrl_in
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_in
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_reg
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_request
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_request_clr
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_exit
+add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/iphase_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_int_ctrl/pc_addr_out
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_ack
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stat_save_out
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stat_rest_out
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/pc_load_out
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_push_out
+add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/int_state
+add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/int_state_next
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/pc_load
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_push
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_pop
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_pop_out
+add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_push_out
+add wave -noupdate -divider PC
+add wave -noupdate -format Literal /tb_cpu/uut/iphase
+add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
+add wave -noupdate -format Logic /tb_cpu/uut/inst_pc/rst
+add wave -noupdate -format Logic /tb_cpu/uut/inst_pc/clk
+add wave -noupdate -format Logic /tb_cpu/uut/inst_pc/inc
+add wave -noupdate -format Logic /tb_cpu/uut/inst_pc/load
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_pc/pc_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_pc/pc_out
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_pc/pc_next
+add wave -noupdate -divider {Stack controller}
+add wave -noupdate -format Literal /tb_cpu/uut/iphase
+add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
+add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/rst
+add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/clk
+add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/push
+add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/pop
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/ptr_out
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/din
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/dout
+add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/mem_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/ptr
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {8115990 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+update
+WaveRestoreZoom {8048536 ps} {8340629 ps}

lib/CPUs/JCpu/sim/tb_mul8x8.fdo

@@ -0,0 +1,21 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+vcom -explicit  -93 "../src/core/cpu_pkg.vhd"
+vcom -explicit  -93 "../src/core/stack_ctrl.vhd"
+vcom -explicit  -93 "../src/core/reg_dual.vhd"
+vcom -explicit  -93 "../src/core/chipram.vhd"
+vcom -explicit  -93 "../src/core/pc.vhd"
+vcom -explicit  -93 "../src/core/dpath_ctrl.vhd"
+vcom -explicit  -93 "../src/core/int_ctrl.vhd"
+vcom -explicit  -93 "../src/core/alu.vhd"
+vcom -explicit  -93 "../src/core/cpu.vhd"
+vcom -explicit  -93 "../src/cpu_embedded.vhd"
+vcom -explicit  -93 "../src/tb_cpu_embedded.vhd"
+vcom -explicit  -93 "../src/mul8x8_irom.vhdl"
+vsim -t 1ps   -lib work tb_cpu_embedded
+do {tb_mul8x8.wdo}
+view wave
+view structure
+view signals
+run 10us

lib/CPUs/JCpu/sim/tb_mul8x8.wdo

@@ -0,0 +1,31 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_cpu_embedded/uut/inst_cpu/rst
+add wave -noupdate -format Logic /tb_cpu_embedded/uut/inst_cpu/clk
+add wave -noupdate -format Logic /tb_cpu_embedded/uut/inst_cpu/ce
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/inst_cpu/instr_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/inst_cpu/instr_addr
+add wave -noupdate -format Literal /tb_cpu_embedded/uut/inst_cpu/cpu_status
+add wave -noupdate -format Literal /tb_cpu_embedded/uut/inst_cpu/status_reg
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/inst_cpu/alu_op1
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/inst_cpu/alu_op2
+add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/inst_cpu/alu_result
+add wave -noupdate -format Literal /tb_cpu_embedded/uut/inst_cpu/alu_status
+add wave -noupdate -format Literal /tb_cpu_embedded/uut/inst_cpu/inst_dpath_ctrl/dbg_iname
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_cpu_embedded/uut/inst_cpu/inst_reg_ab/mem
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {529679 ps} 0}
+configure wave -namecolwidth 143
+configure wave -valuecolwidth 101
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+update
+WaveRestoreZoom {9002500 ps} {10052500 ps}

lib/CPUs/JCpu/src/core/alu.vhd

@@ -0,0 +1,236 @@
+--------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The arithmetic logic unit
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.cpu_pkg.all;
+
+entity alu is
+	Generic (
+		data_width : integer := 8
+	);
+	Port (
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		op_en		: in  STD_LOGIC;
+		cy_in		: in  STD_LOGIC;
+		op1_in		: in  unsigned (data_width-1 downto 0);
+		op2_in		: in  unsigned (data_width-1 downto 0);
+		opsel		: in  alu_op_t;
+		res_out		: out unsigned (data_width-1 downto 0);
+		stat_load	: in  STD_LOGIC;
+		stat_in		: in  alu_status_t;
+		stat_out	: out alu_status_t
+	);
+end alu;
+
+architecture Behavioral of alu is
+
+	signal sum_cy, sh_cy, sum_cy_in, sh_cy_in, left_shift, add_subn : STD_LOGIC;
+	signal result, sum_res, lf_res, sh_res, res_reg : unsigned (data_width-1 downto 0);
+	signal status, stat_reg : alu_status_t;
+	
+	--------------------------------------------------------------------------
+	function test_zero(arg : unsigned) return STD_LOGIC is
+	variable result : STD_LOGIC;
+	begin
+			result := '0';
+			for i in arg'range loop
+				result := result or To_X01(arg(i));
+			end loop;
+
+			return not result;
+	end test_zero;
+
+--------------------------------------------------------------------------
+begin
+
+--------------------------------------------------------------------------
+proc_logic_func: 
+	process (op1_in, op2_in, opsel)
+	begin
+		
+		case opsel is
+		when op1_and_op2 =>
+			lf_res <= op1_in and op2_in;
+		when op1_or_op2 =>
+			lf_res <= op1_in or op2_in;
+		when op1_xor_op2 =>
+			lf_res <= op1_in xor op2_in;
+		when others =>
+			lf_res <= (others => '-');
+		end case;
+
+	end process;	
+
+--------------------------------------------------------------------------
+proc_shift_func: 
+	process (op1_in, left_shift, sh_cy_in)
+	begin
+		if left_shift = '1' then
+			sh_res <= op1_in(op1_in'left-1 downto op1_in'right) & sh_cy_in;
+			sh_cy <= op1_in(op1_in'left);
+		else	
+			sh_res <= sh_cy_in & op1_in(op1_in'left downto op1_in'right+1);
+			sh_cy <= op1_in(op1_in'right);
+		end if;	
+		
+	end process;	
+
+--------------------------------------------------------------------------
+proc_alu_out:
+	process(opsel, op1_in, op2_in, res_reg, stat_reg, lf_res, sum_res, sh_res, sum_cy, sh_cy, cy_in)
+
+	begin
+		
+		case opsel is
+		
+		when op1_add_op2 | op1_sub_op2 | op1_addc_op2 | op1_subc_op2 =>
+			status.zero <= test_zero(res_reg);
+			status.carry <= sum_cy;
+			result <= sum_res;
+		when op1_and_op2 | op1_or_op2 | op1_xor_op2 =>
+			status.zero <= test_zero(res_reg);
+			status.carry <= stat_reg.carry;
+			result <= lf_res;
+		when shl_op | shr_op | rol_op | ror_op | rolc_op | rorc_op =>
+			status.zero <= test_zero(res_reg);
+			status.carry <= sh_cy;
+			result <= sh_res;
+		when swap_op =>
+			result <= op1_in(op1_in'left-op1_in'length/2 downto op1_in'right) & op1_in(op1_in'left downto op1_in'right+op1_in'length/2);
+			status <= stat_reg;
+		when others =>
+			result <= op2_in;
+			status.zero <= stat_reg.zero;
+			status.carry <= stat_reg.carry or cy_in;
+		end case;
+		
+	end process;
+
+--------------------------------------------------------------------------
+proc_alu_in:
+	process(opsel, op1_in, stat_reg)
+
+	begin
+		
+		add_subn <= '-';
+		sum_cy_in <= '-';
+		sh_cy_in <= '-';
+		left_shift <= '-';
+
+		case opsel is
+		
+		when op1_add_op2 =>
+			sum_cy_in <= '0';
+			add_subn <= '1';
+
+		when op1_sub_op2 =>
+			sum_cy_in <= '0';
+			add_subn <= '0';
+	
+		when op1_addc_op2 => 
+			sum_cy_in <= stat_reg.carry;
+			add_subn <= '1';
+
+		when op1_subc_op2 => 
+			sum_cy_in <= stat_reg.carry;
+			add_subn <= '0';
+
+		when shl_op =>
+			sh_cy_in <= '0';
+			left_shift <= '1';
+			
+		when shr_op =>
+			sh_cy_in <= '0';
+			left_shift <= '0';
+
+		when rol_op =>
+			sh_cy_in <= op1_in(op1_in'left);
+			left_shift <= '1';
+
+		when ror_op =>
+			sh_cy_in <= op1_in(op1_in'right);
+			left_shift <= '0';
+
+		when rolc_op =>
+			sh_cy_in <= stat_reg.carry;
+			left_shift <= '1';
+
+		when rorc_op =>
+			sh_cy_in <= stat_reg.carry;
+			left_shift <= '0';
+
+		when others => null;
+
+		end case;
+		
+	end process;
+
+--------------------------------------------------------------------------
+proc_res_reg:
+	process(clk, rst, op_en, stat_load, res_reg, stat_reg)
+	begin
+		if rst = '1' then
+			res_reg <= (others => '0');
+			stat_reg <= (others => '0');
+		elsif rising_edge(clk) then
+			if op_en = '1' then
+				res_reg <= result;
+				stat_reg <= status;
+			elsif stat_load = '1' then
+				stat_reg  <= stat_in;
+			end if;	
+		end if;
+		res_out <= res_reg;
+		stat_out <= stat_reg;
+
+	end process;
+
+--------------------------------------------------------------------------
+alu_addsub:
+	process(op1_in, op2_in, sum_cy_in, add_subn)
+	variable sum  : unsigned(data_width+1 downto 0);
+	variable op1, op2 : unsigned(data_width+1 downto 0);
+	begin
+		if add_subn = '1' then
+			op1 := '0' & op1_in & '1';
+			op2 := '0' & op2_in & sum_cy_in;
+			sum := op1 + op2; 
+		else
+			op1 := '0' & op1_in & not sum_cy_in;
+			op2 := '0' & op2_in & '1';
+			sum := op1 - op2; 
+		end if;
+
+		-- Form sum + carry
+		sum_res <= sum(data_width downto 1);
+		sum_cy <= sum(sum'left);
+		
+	end process;	
+
+--------------------------------------------------------------------------
+end Behavioral;
+

lib/CPUs/JCpu/src/core/chipram.vhd

@@ -0,0 +1,85 @@
+--------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: On-chip RAM
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.cpu_pkg.all;
+
+entity chipram is
+	Generic (
+		addr_width : integer := 3;
+		data_width : integer := 8
+	);
+	Port (
+		clka		: in  STD_LOGIC;
+		clkb		: in  STD_LOGIC;
+		en_a		: in  STD_LOGIC;
+		en_b		: in  STD_LOGIC;
+		we_a		: in  STD_LOGIC;
+		we_b		: in  STD_LOGIC;
+		addr_a		: in  unsigned (addr_width-1 downto 0);
+		addr_b		: in  unsigned (addr_width-1 downto 0);
+		din_a		: in  unsigned (data_width-1 downto 0);
+		din_b		: in  unsigned (data_width-1 downto 0);
+		dout_a		: out unsigned (data_width-1 downto 0);
+		dout_b		: out unsigned (data_width-1 downto 0)
+	);
+end chipram;
+
+architecture Behavioral of chipram is
+
+	constant depth : integer := 2**addr_width;
+	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
+	shared variable RAM : RAMtype;
+	
+begin
+
+process (clka)
+begin
+if clka'event and clka = '1' then
+	if en_a = '1' then
+		if we_a = '1' then
+			RAM(to_integer(addr_a)) := din_a;
+		end if;
+		dout_a <= RAM(to_integer(addr_a));
+	end if;
+end if;
+end process;
+
+process (clkb)
+begin
+if clkb'event and clkb = '1' then
+	if en_b = '1' then
+		if we_b = '1' then
+			RAM(to_integer(addr_b)) := din_b;
+		end if;
+		dout_b <= RAM(to_integer(addr_b));
+	end if;
+end if;
+end process;
+
+
+end Behavioral;
+

lib/CPUs/JCpu/src/core/chipreg.vhd

@@ -0,0 +1,123 @@
+--------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: On-Chip registers
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.cpu_pkg.all;
+
+entity chipreg is
+	Port (
+		rst			: in  STD_LOGIC; 
+		clk			: in  STD_LOGIC;
+		we			: in  STD_LOGIC;
+		addr		: in  dmem_addr_t;
+		din			: in  dmem_data_t;
+		dout		: out dmem_data_t;
+		ctrl_in		: in  creg_ctrl_in_t;
+		ctrl_out	: out creg_ctrl_out_t
+	);
+end chipreg;
+
+architecture Behavioral of chipreg is
+
+	signal reg_bank_sel		: bank_sel_t;
+	signal reg_int_ctrl		: int_ctrl_in_t;
+	signal reg_stk_high		: unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
+	signal reg_cmem_high	: unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
+
+begin
+
+proc_assign_ctrl_lines:
+	process (clk)
+	begin
+		if rising_edge(clk) then
+			ctrl_out.bank_sel	<= reg_bank_sel;
+			ctrl_out.int_ctrl	<= reg_int_ctrl;
+			ctrl_out.stk_high	<= reg_stk_high;
+			ctrl_out.cmem_high	<= reg_cmem_high;
+		end if;
+	end process;
+
+proc_reg_write:
+	process (rst, clk)
+	begin
+		if rst = '1' then
+			reg_stk_high <= (others => '0');
+			reg_cmem_high <= (others => '0');
+			reg_bank_sel <= (others => '0');
+			reg_int_ctrl.enable		<= '0';
+			reg_int_ctrl.polarity	<= '1';
+			reg_int_ctrl.edge_sens	<= '1';
+		elsif rising_edge(clk) then
+			reg_int_ctrl.request <= '0';
+			if we = '1' then
+				case addr is
+				when X"01" =>
+					reg_bank_sel(bank_sel_t'range)	<= din(bank_sel_t'range);
+				when X"03" =>
+					reg_int_ctrl.enable		<= din(0);
+					reg_int_ctrl.polarity	<= din(1);
+					reg_int_ctrl.edge_sens	<= din(2);
+					reg_int_ctrl.request	<= din(7);
+				when X"04" =>
+					reg_cmem_high <= din(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
+				when X"05" =>
+					reg_stk_high <= din(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
+				when others => null;
+				end case;
+			end if;
+		end if;
+	end process;
+
+proc_reg_read:
+	process (clk)
+	begin
+		if rising_edge(clk) then
+			case addr is
+			when X"00" =>	-- Revison
+				dout <= to_unsigned(REVISION, dmem_data_t'length);
+			when X"01" =>	-- Control 0
+				dout <= (7 downto bank_sel_t'length => '0') & reg_bank_sel;
+			when X"02" =>	-- CPU status
+				dout <= "000000" & ctrl_in.alu.carry & ctrl_in.alu.zero;
+			when X"03" =>	-- Interrupt control
+				dout <= "00000" & reg_int_ctrl.edge_sens & reg_int_ctrl.polarity & reg_int_ctrl.enable;
+			when X"04" =>	-- Upper stack bits out
+				dout <= "0000" & reg_cmem_high;
+			when X"05" =>	-- Upper cmem bits out
+				dout <= "0000" & reg_stk_high;
+			when others => 
+				if addr(0) = '0' then
+					dout <= X"DE";
+				else
+					dout <= X"AD";
+				end if;
+			end case;
+			
+		end if;
+	end process;
+
+end Behavioral;
+

lib/CPUs/JCpu/src/core/cpu.vhd

@@ -0,0 +1,566 @@
+--------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: JCPU top file 
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.cpu_pkg.all;
+
+entity cpu is
+	Generic (
+		use_instr_register	: boolean := false;
+		use_ctrl_rom		: boolean := true
+
+	);
+	Port (
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
+		int_in		: in  STD_LOGIC;
+		int_ack		: out STD_LOGIC;
+		xmem_wait	: in  STD_LOGIC;
+		xmem_we		: out STD_LOGIC;
+		xmem_re		: out STD_LOGIC;
+		instr_din	: in  unsigned (IMEM_DATA_WIDTH-1 downto 0);
+		instr_addr	: out unsigned (IMEM_ADDR_WIDTH-1 downto 0);
+		xmem_din	: in  unsigned (DMEM_DATA_WIDTH-1 downto 0);
+		xmem_dout	: out unsigned (DMEM_DATA_WIDTH-1 downto 0);
+		xmem_addr	: out unsigned (DMEM_ADDR_WIDTH-1 downto 0);
+		io_sel		: out std_logic
+	);
+end cpu;
+
+architecture rtl of cpu is
+
+	COMPONENT stack_ctrl
+	GENERIC (
+		addr_width	: integer
+	);
+	Port (
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		push		: in  STD_LOGIC;
+		pop			: in  STD_LOGIC;
+		din			: in  inst_addr_t;
+		dout		: out inst_addr_t;
+		mem_we		: out  STD_LOGIC;
+		ptr_out		: out unsigned (addr_width-1 downto 0)
+	);
+	END COMPONENT;
+
+	COMPONENT pc
+	Port (
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		inc			: in  STD_LOGIC;
+		load		: in  STD_LOGIC;
+		pc_in		: in  inst_addr_t;
+		pc_out		: out inst_addr_t;
+		pc_next		: out inst_addr_t
+	);
+	END COMPONENT;
+
+	COMPONENT dpath_ctrl
+	GENERIC (
+		use_rom		: boolean
+	);
+	Port (
+		inst_in		: in  inst_t;
+		iphase_in	: in  iphase_t;
+		status_in	: in  cpu_status_t;
+		ctrl_out	: out dpath_ctrl_out_t;
+		idout		: out inst_addr_t;
+		ddout		: out dmem_data_t
+	);
+	END COMPONENT;
+
+	COMPONENT int_ctrl
+	Port (
+		rst				: in  STD_LOGIC;
+		clk				: in  STD_LOGIC;
+		ctrl_in			: in  int_ctrl_in_t;
+		int_in			: in  STD_LOGIC;
+		int_exit		: in  STD_LOGIC;
+		iphase_in		: in  iphase_t;
+		int_ack_out		: out STD_LOGIC;
+		stat_save_out	: out STD_LOGIC; 
+		stat_rest_out	: out STD_LOGIC; 
+		pc_addr_out		: out inst_addr_t;
+		pc_load_out		: out STD_LOGIC;
+		stk_push_out	: out STD_LOGIC;
+		stk_pop_out		: out STD_LOGIC
+	);
+	END COMPONENT;
+
+	COMPONENT reg_dual
+	GENERIC (
+		addr_width	: integer;
+		data_width	: integer
+	);
+	Port (
+		clk			: in  STD_LOGIC;
+		we_a		: in  STD_LOGIC;
+		ptr_a		: in  reg_ptr_t;
+		ptr_b		: in  reg_ptr_t;
+		din_a		: in  unsigned (data_width-1 downto 0);
+		dout_a		: out unsigned (data_width-1 downto 0);
+		dout_b		: out unsigned (data_width-1 downto 0)
+	);
+	END COMPONENT;
+
+	COMPONENT chipram
+	GENERIC (
+		addr_width : integer;
+		data_width : integer
+	);
+	Port (
+		clka		: in  STD_LOGIC;
+		clkb		: in  STD_LOGIC;
+		en_a		: in  STD_LOGIC;
+		en_b		: in  STD_LOGIC;
+		we_a		: in  STD_LOGIC;
+		we_b		: in  STD_LOGIC;
+		addr_a		: in  unsigned (addr_width-1 downto 0);
+		addr_b		: in  unsigned (addr_width-1 downto 0);
+		din_a		: in  unsigned (data_width-1 downto 0);
+		din_b		: in  unsigned (data_width-1 downto 0);
+		dout_a		: out unsigned (data_width-1 downto 0);
+		dout_b		: out unsigned (data_width-1 downto 0)
+	);
+	END COMPONENT;
+
+	COMPONENT chipreg
+	Port (
+		rst			: in  STD_LOGIC; 
+		clk			: in  STD_LOGIC;
+		we			: in  STD_LOGIC;
+		addr		: in  dmem_addr_t;
+		din			: in  dmem_data_t;
+		dout		: out dmem_data_t;
+		ctrl_in		: in  creg_ctrl_in_t;
+		ctrl_out	: out creg_ctrl_out_t
+	);
+	END COMPONENT;
+
+	COMPONENT alu
+	GENERIC (
+		data_width : integer := 8
+	);
+	Port (
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		op_en		: in  STD_LOGIC;
+		cy_in		: in  STD_LOGIC;
+		op1_in		: in  unsigned (data_width-1 downto 0);
+		op2_in		: in  unsigned (data_width-1 downto 0);
+		opsel		: in  alu_op_t;
+		res_out		: out unsigned (data_width-1 downto 0);
+		stat_load	: in  STD_LOGIC;
+		stat_in		: in  alu_status_t;
+		stat_out	: out alu_status_t
+	);
+	END COMPONENT;
+
+	signal cpu_status, status_reg : cpu_status_t; -- := cpu_status_t(others => '0');
+	signal ctrl : dpath_ctrl_out_t;
+	signal stk_out : inst_addr_t;
+	signal stk_in : inst_addr_t;
+	signal stk_reg : inst_addr_t;
+	signal pc_in, pc_out, pc_next, idata, int_pc_addr : inst_addr_t;
+	signal iphase : iphase_t;
+	signal const_data, reg_a_dout, reg_b_dout : dmem_data_t;
+	signal reg_din : dmem_data_t;
+	signal alu_op1, alu_op2, alu_result : dmem_data_t;
+	signal alu_status : alu_status_t;
+	signal pc_inc, pc_load, cpu_active, stk_we, cmem_we, creg_we : STD_LOGIC;
+	signal ctrl_inst : inst_t;
+	signal ctrl_iphase : iphase_t;
+	signal was_pcld, was_pop2pc, int_pc_load, int_stk_push, int_stk_pop, stk_push, stk_pop : STD_LOGIC;
+	signal status_save, status_restore : STD_LOGIC;
+	signal creg_dout : dmem_data_t;
+	signal cmem_din, cmem_dout : inst_addr_t;
+	signal stk_addr, cmem_addr : unsigned(CHIPRAM_SIZE_BITS-1 downto 0);
+	signal stk_ptr : unsigned(STACK_SIZE_BITS-1 downto 0);
+	signal creg_ctrl_out : creg_ctrl_out_t;
+	signal creg_ctrl_in : creg_ctrl_in_t;
+	signal irq_out : std_logic;
+	signal xio_sel, cio_sel : std_logic; 
+	signal mem_data : dmem_data_t;
+	signal mem_addr : dmem_data_t;
+	
+begin
+	io_sel <= xio_sel;
+	instr_addr <= pc_out;
+	pc_inc <= cpu_active and ctrl.lines.pc_inc;
+	stk_addr <= '0' & stk_ptr;
+	cpu_status.alu <= alu_status;
+	cpu_status.xmem_wait <= xmem_wait;
+	creg_ctrl_in.alu <= alu_status;
+
+	xmem_dout <= mem_data;
+	xmem_addr <= mem_addr;
+	cmem_din <= creg_ctrl_out.cmem_high & mem_data;
+	cmem_addr <= '1' & creg_ctrl_out.bank_sel & mem_addr(MIN(cmem_addr'length-creg_ctrl_out.bank_sel'length-1, mem_addr'length)-1 downto 0);
+
+--------------------------------------------------------------------
+mem_ctrl_lines:
+	process(ctrl.lines)
+	begin
+		xio_sel <= '0';
+		xmem_re <= '0';
+		xmem_we <= '0';
+		cio_sel <= '0';
+		cmem_we <= '0';
+		creg_we <= '0';
+		
+		case ctrl.lines.mem_access is
+			when xmem_access =>
+				xmem_re <= ctrl.lines.mem_read;
+				xmem_we <= ctrl.lines.mem_write;
+			when xio_access =>
+				xio_sel <= '1';
+				xmem_re <= ctrl.lines.mem_read;
+				xmem_we <= ctrl.lines.mem_write;
+			when cmem_access =>
+				cmem_we <= ctrl.lines.mem_write;
+			when cio_access =>
+				cio_sel <= '1';
+				creg_we <= ctrl.lines.mem_write;
+			when others => null;
+		end case;
+	end process;
+
+iphase_counter:
+	process(rst, clk, ce)
+	variable pos : integer; 
+	begin
+		if rst = '1' then
+			iphase <= iphase_t'low;
+			cpu_active <= '0';
+		elsif rising_edge(clk) then
+			cpu_active <= '0';
+			if ce = '1' then
+				cpu_active <= '1';
+				if iphase = iphase_t'high then
+					iphase <= iphase_t'low;
+				else
+					iphase <= iphase + 1;
+				end if;
+			end if;	
+		end if;
+	end process;
+
+gen_instr_reg:
+if use_instr_register = true generate
+
+instr_reg:
+	process (rst, clk, ce)
+	begin
+		if rst = '1' then
+			ctrl_inst <= (others => '0');
+			ctrl_iphase <= 0;
+		elsif rising_edge(clk) and ce = '1' then
+			ctrl_inst <= instr_din;
+			ctrl_iphase <= iphase;
+		end if;
+	end process;
+
+end generate;
+	
+gen_instr_direct:
+if use_instr_register = false generate
+
+	ctrl_inst <= instr_din;
+	ctrl_iphase <= iphase;
+
+end generate;
+
+status_register:
+	process(clk, status_save)
+	begin
+		if rising_edge(clk) and status_save = '1' then
+			status_reg.alu <= alu_status;
+		end if;
+	end process;
+
+pc_pushpop:
+	process(ctrl.lines, int_pc_load, int_stk_push, int_stk_pop, was_pop2pc)
+	begin
+		pc_load <= ctrl.lines.pc_load or int_pc_load;
+		stk_push <= (ctrl.lines.stk_pushd or ctrl.lines.stk_push) or (int_stk_push and not was_pop2pc);
+		stk_pop <= ctrl.lines.stk_popd or int_stk_pop or (ctrl.lines.stk_pop and not int_pc_load);
+	end process;
+	
+lines_delay:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			was_pcld <= ctrl.lines.pc_load;
+			was_pop2pc <= ctrl.lines.stk_pop and ctrl.lines.pc_load;
+		end if;
+	end process;
+
+stk_mux:
+	process(ctrl.lines, was_pcld, int_stk_push, pc_next, idata, reg_a_dout, creg_ctrl_out)
+	begin
+		if was_pcld = '1' and int_stk_push = '1' then 
+			stk_in <= idata;
+		elsif ctrl.lines.stk_pushd = '1' then
+			stk_in <= creg_ctrl_out.stk_high & reg_a_dout;
+		else	
+			stk_in <= pc_next;
+		end if;	
+		
+	end process;
+
+pc_mux:
+	process(ctrl.lines, int_pc_load, int_stk_pop, idata, int_pc_addr, stk_out)
+	begin
+		
+		pc_in <= stk_out;
+		if int_pc_load = '1' then 
+			if int_stk_pop = '0' then
+				pc_in <= int_pc_addr;
+			end if;	
+		elsif ctrl.lines.pc_load = '1' then
+			if ctrl.lines.stk_pop = '0' then
+				pc_in <= idata;
+			end if;	
+		end if;	
+
+	end process;
+
+mem_data_mux:
+	process(ctrl.lines.ddata_src_sel, reg_a_dout, reg_b_dout, const_data, creg_ctrl_out)
+	begin
+		case ctrl.lines.ddata_src_sel is
+		when reg_a => 
+			mem_data <= reg_a_dout;
+		when reg_b =>
+			mem_data <= reg_b_dout;
+		when const =>
+			mem_data <= const_data;
+		when others =>
+			mem_data <= const_data;
+		end case;
+
+	end process;
+
+mem_addr_mux:
+	process(ctrl.lines.daddr_src_sel, reg_a_dout, reg_b_dout, const_data, creg_ctrl_out.bank_sel)
+	begin
+		case ctrl.lines.daddr_src_sel is
+		when reg_a => 
+			mem_addr <= reg_a_dout;
+		when reg_b =>
+			mem_addr <= reg_b_dout;
+		when const =>
+			mem_addr <= const_data;
+		when others =>
+			mem_addr <= const_data;
+		end case;
+
+	end process;
+
+reg_in_mux:
+	process(ctrl.lines.reg_src_sel, cio_sel, xmem_din, alu_result, stk_out, cmem_dout, creg_dout)
+	variable data : dmem_data_t;
+	begin
+		case ctrl.lines.reg_src_sel is
+		when xmem_src =>
+			data := xmem_din;
+		when cmem_src =>
+			if cio_sel = '0' then
+				data := cmem_dout(dmem_data_t'range);
+			else
+				data := creg_dout(dmem_data_t'range);
+			end if;
+		when stk_src =>
+			data := stk_out(dmem_data_t'range);
+		when others =>
+			data := alu_result;
+		end case;
+
+		reg_din <= data;
+
+	end process;
+
+alu_op1_mux:
+	process(ctrl.lines.alu_op1_src_sel, reg_a_dout, reg_b_dout, const_data)
+	variable data : dmem_data_t;
+	begin
+		case ctrl.lines.alu_op1_src_sel is
+		when reg_a =>
+			data := reg_a_dout;
+		when reg_b =>
+			data := reg_b_dout;
+		when others =>
+			data := const_data;
+		end case;
+
+		alu_op1 <= data;
+
+	end process;
+
+alu_op2_mux:
+	process(ctrl.lines.alu_op2_src_sel, reg_a_dout, reg_b_dout, const_data)
+	variable data : dmem_data_t;
+	begin
+		case ctrl.lines.alu_op2_src_sel is
+		when reg_a =>
+			data := reg_a_dout;
+		when reg_b =>
+			data := reg_b_dout;
+		when others =>
+			data := const_data;
+		end case;
+
+		alu_op2 <= data;
+
+	end process;
+
+--------------------------------------------------------------------
+	inst_stack_ctrl: stack_ctrl
+	GENERIC MAP (
+		addr_width	=> STACK_SIZE_BITS
+	)
+	PORT MAP(
+		rst			=> rst,
+		clk			=> clk,
+		push		=> stk_push,
+		pop			=> stk_pop,
+		dout		=> stk_reg,
+		din			=> stk_in,
+		ptr_out		=> stk_ptr,
+		mem_we		=> stk_we
+	);
+
+	inst_pc: pc
+	PORT MAP(
+		rst			=> rst,
+		clk			=> clk,
+		inc			=> pc_inc,
+		load		=> pc_load,
+		pc_in		=> pc_in,
+		pc_out		=> pc_out,
+		pc_next		=> pc_next
+	);
+
+	inst_dpath_ctrl: dpath_ctrl
+	GENERIC MAP (
+		use_rom		=> use_ctrl_rom
+	)
+	PORT MAP(
+		inst_in		=> ctrl_inst,
+		iphase_in   => ctrl_iphase,
+		status_in	=> cpu_status,
+		ctrl_out	=> ctrl,
+		ddout		=> const_data,
+		idout		=> idata
+	);
+	
+	inst_int_ctrl: int_ctrl
+	PORT MAP(
+		rst				=> rst,
+		clk				=> clk,
+		ctrl_in			=> creg_ctrl_out.int_ctrl,
+		int_in			=> int_in,
+		int_ack_out		=> int_ack,
+		int_exit		=> ctrl.lines.int_exit,
+		iphase_in		=> ctrl_iphase,
+		stat_save_out	=> status_save,
+		stat_rest_out	=> status_restore,
+		pc_addr_out		=> int_pc_addr,
+		pc_load_out		=> int_pc_load,
+		stk_push_out	=> int_stk_push,
+		stk_pop_out		=> int_stk_pop
+		
+	);
+	
+	inst_reg_ab: reg_dual
+	GENERIC MAP (
+		addr_width	=> REG_SIZE_BITS,
+		data_width	=> DMEM_DATA_WIDTH
+	)
+	PORT MAP(
+		clk			=> clk,
+		we_a		=> ctrl.lines.reg_we,
+		ptr_a		=> ctrl.reg_a_ptr,
+		ptr_b		=> ctrl.reg_b_ptr,
+		din_a		=> reg_din,
+		dout_a		=> reg_a_dout,
+		dout_b		=> reg_b_dout
+	);
+
+	inst_chipram: chipram
+	GENERIC MAP (
+		addr_width	=> CHIPRAM_SIZE_BITS,
+		data_width	=> IMEM_ADDR_WIDTH
+	)
+	PORT MAP(
+		clka		=> clk,
+		clkb		=> clk,
+		en_a		=> cpu_active,
+		en_b		=> cpu_active,
+		we_a		=> stk_we,
+		we_b		=> cmem_we,
+		addr_a		=> stk_addr,
+		addr_b		=> cmem_addr,
+		din_a		=> stk_reg,
+		din_b		=> cmem_din,
+		dout_a		=> stk_out,
+		dout_b		=> cmem_dout
+	);
+
+	inst_chipreg: chipreg
+	PORT MAP(
+		rst			=> rst,
+		clk			=> clk,
+		we			=> creg_we,
+		addr		=> mem_addr,
+		din			=> mem_data,
+		dout		=> creg_dout,
+		ctrl_in		=> creg_ctrl_in,
+		ctrl_out	=> creg_ctrl_out
+	);
+
+	inst_alu: alu
+	GENERIC MAP (
+		data_width	=> DMEM_DATA_WIDTH
+	)
+	PORT MAP(
+		rst			=> rst,
+		clk			=> clk,
+		op_en		=> ctrl.lines.alu_load,
+		cy_in		=> ctrl.lines.alu_cy_in,
+		op1_in		=> alu_op1,
+		op2_in		=> alu_op2,
+		opsel		=> ctrl.lines.alu_opsel,
+		res_out		=> alu_result,
+		stat_load	=> status_restore,
+		stat_in		=> status_reg.alu,
+		stat_out	=> alu_status
+	);
+
+end rtl;

lib/CPUs/JCpu/src/core/cpu_pkg.vhd

@@ -0,0 +1,901 @@
+--------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: Types, constants and functions for JCPU
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+
+package cpu_pkg is
+
+	-- Revision of the CPU
+	constant REVISION : integer := 4;
+	
+	-- Chipram depth (valid values 9..floor(log2(BlockRamBytes)))
+	constant CHIPRAM_SIZE_BITS : integer := 10;
+	
+	-- Number of registers (16 registers fixed)
+	constant REG_SIZE_BITS : integer := 4;
+	
+	-- Instruction memory
+	constant IMEM_ADDR_WIDTH : integer := 12;
+	
+	-- Data memory
+	constant DMEM_DATA_WIDTH : integer := 8;
+	constant DMEM_ADDR_WIDTH : integer := 8;
+	
+	-- Instruction format
+	constant INST_OPCODE_WIDTH : integer := 6;
+	constant IMEM_DATA_WIDTH : integer := INST_OPCODE_WIDTH + DMEM_DATA_WIDTH + REG_SIZE_BITS;
+
+	-- Microcode ROM
+	constant MUCODE_ADDR_WIDTH : integer := 10;
+	
+	-- Stack depth (uses lower half of CHIPRAM)
+	constant STACK_SIZE_BITS : integer := CHIPRAM_SIZE_BITS-1;
+
+	--Types
+	subtype iphase_t is integer range 0 to 1;
+	type mem_access_t is (cmem_access, xmem_access, cio_access, xio_access);
+	type reg_src_t is (alu_src, stk_src, cmem_src, xmem_src);
+	type alu_src_t is (reg_a, reg_b, const);
+	type ddata_src_t is (reg_a, reg_b, const);
+	type daddr_src_t is (reg_a, reg_b, const);
+	subtype instr_name_t is string(1 to 12);
+	type instr_name_array_t is array (0 to 63) of instr_name_t;
+	subtype opcode_t is unsigned (INST_OPCODE_WIDTH-1 downto 0);
+	subtype inst_data_t is unsigned (IMEM_ADDR_WIDTH-1 downto 0);
+	subtype inst_addr_t is unsigned (IMEM_ADDR_WIDTH-1 downto 0);
+	subtype inst_t is unsigned (IMEM_DATA_WIDTH-1 downto 0);
+	subtype dmem_data_t is unsigned (DMEM_DATA_WIDTH-1 downto 0);
+	subtype dmem_addr_t is unsigned (DMEM_DATA_WIDTH-1 downto 0);
+	subtype reg_ptr_t is unsigned (3 downto 0);
+	type dmem_array_t is array (natural range <>) of dmem_data_t;
+	type instr_addr_array is array (integer range <>) of inst_addr_t;
+	subtype bank_sel_t is unsigned (CHIPRAM_SIZE_BITS-DMEM_DATA_WIDTH-2 downto 0);
+	
+	type alu_op_t is
+	(
+		pass_op2,
+		op1_add_op2,
+		op1_sub_op2,
+		op1_addc_op2,
+		op1_subc_op2,
+		op1_and_op2,
+		op1_or_op2,
+		op1_xor_op2,
+		swap_op,
+		shl_op,
+		shr_op,
+		rol_op,
+		ror_op,
+		rolc_op,
+		rorc_op
+	);
+	
+	type alu_status_t is record
+		zero		: STD_LOGIC;
+		carry		: STD_LOGIC;
+	end record;
+
+	type cpu_status_t is record
+		alu			: alu_status_t;
+		xmem_wait	: STD_LOGIC;
+	end record;
+
+	type ctrl_lines_t is record
+		reg_we			: STD_LOGIC;
+		reg_src_sel		: reg_src_t;
+		alu_op1_src_sel	: alu_src_t;
+		alu_op2_src_sel	: alu_src_t;
+		alu_opsel		: alu_op_t;
+		alu_load		: STD_LOGIC;
+		alu_cy_in		: STD_LOGIC;
+		ddata_src_sel	: ddata_src_t;
+		daddr_src_sel	: daddr_src_t; 
+		pc_load			: STD_LOGIC;
+		pc_inc			: STD_LOGIC;
+		stk_push		: STD_LOGIC; 
+		stk_pop			: STD_LOGIC;
+		stk_pushd		: STD_LOGIC; 
+		stk_popd		: STD_LOGIC;
+		mem_access		: mem_access_t;
+		mem_read		: STD_LOGIC;
+		mem_write		: STD_LOGIC;
+		int_exit		: STD_LOGIC;
+	end record;
+
+	type dpath_ctrl_out_t is record
+		lines			: ctrl_lines_t;
+		reg_a_ptr		: reg_ptr_t;
+		reg_b_ptr		: reg_ptr_t;
+	end record;
+	
+	type int_ctrl_in_t is record
+		enable			: std_logic;
+		polarity		: std_logic;
+		edge_sens		: std_logic;
+		request			: std_logic;
+	end record;
+	
+	type creg_ctrl_out_t is record
+		bank_sel		: bank_sel_t;
+		int_ctrl		: int_ctrl_in_t;
+		stk_high		: unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
+		cmem_high		: unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
+	end record;
+	
+	type creg_ctrl_in_t is record
+		alu				: alu_status_t;
+	end record;
+
+	
+	type murom_t is array (0 to integer(2**MUCODE_ADDR_WIDTH)-1) of ctrl_lines_t;
+
+	constant instr_name_array : instr_name_array_t := 
+	(
+		"NOP         ", -- 00
+		"HALT        ", -- 01
+		"MOV|R|R     ", -- 02
+		"MOV|R|K     ", -- 03
+		"MOVX|R|Ri   ", -- 04
+		"MOVX|R|Ki   ", -- 05
+		"MOVX|Ri|R   ", -- 06
+		"MOVX|Ri|K   ", -- 07
+		"MOVX|Ki|R   ", -- 08
+		"MOVC|R|Ri   ", -- 09
+		"MOVC|R|Ki   ", -- 0A
+		"MOVC|Ri|R   ", -- 0B
+		"MOVC|Ri|K   ", -- 0C
+		"MOVC|Ki|R   ", -- 0D
+		"CMP|R|R     ", -- 0E
+		"CMP|R|K     ", -- 0F
+		"ADD|R|R     ", -- 10
+		"ADD|R|K     ", -- 11
+		"ADDC|R|R    ", -- 12
+		"ADDC|R|K    ", -- 13
+		"SUB|R|R     ", -- 14
+		"SUB|R|K     ", -- 15
+		"SUBC|R|R    ", -- 16
+		"SUBC|R|K    ", -- 17
+		"AND|R|R     ", -- 18
+		"AND|R|K     ", -- 19
+		"OR|R|R      ", -- 1A
+		"OR|R|K      ", -- 1B
+		"XOR|R|R     ", -- 1C
+		"XOR|R|K     ", -- 1D
+		"SHL|R       ", -- 1E
+		"SHR|R       ", -- 1F
+		"ROL|R       ", -- 20
+		"ROR|R       ", -- 21
+		"ROLC|R      ", -- 22
+		"RORC|R      ", -- 23
+		"XOUT|Ki|R   ", -- 24
+		"XOUT|Ri|K   ", -- 25
+		"COUT|Ki|R   ", -- 26
+		"COUT|Ri|K   ", -- 27
+		"XIN|R|Ki    ", -- 28
+		"CIN|R|Ki    ", -- 29
+		"SWAP|R      ", -- 2A
+		"SETC        ", -- 2B
+		"UNDEF       ", -- 2C
+		"UNDEF       ", -- 2D
+		"SUB|K|R     ", -- 2E
+		"SUBC|K|R    ", -- 2F
+		"JMP|K       ", -- 30
+		"JZ|K        ", -- 31
+		"JNZ|K       ", -- 32
+		"JC|K        ", -- 33
+		"JNC|K       ", -- 34
+		"JLT|K       ", -- 35
+		"JGT|K       ", -- 36
+		"JLE|K       ", -- 37
+		"JGE|K       ", -- 38
+		"JEQ|K       ", -- 39
+		"JNE|K       ", -- 3A
+		"CALL|K      ", -- 3B
+		"PUSH|R      ", -- 3C
+		"POP|R       ", -- 3D
+		"RET         ", -- 3E
+		"RETI        "  -- 3F
+	);
+	-- Functions
+	function Instr(opcode : opcode_t) return inst_t;
+	function Instr(opcode : opcode_t; data : inst_data_t) return inst_t;
+	function Instr(opcode : opcode_t; data : inst_data_t; reg : integer) return inst_t;
+	function Instr(opcode : opcode_t; reg_a : integer) return inst_t;
+	function Instr(opcode : opcode_t; reg_a, reg_b : integer) return inst_t;
+	function Instr(opcode : opcode_t; reg_a, reg_b, reg_c : integer) return inst_t;
+	function ctrl_lines_default return ctrl_lines_t;
+	function idecoder(instr_name : instr_name_t; iphase : iphase_t; status : cpu_status_t) return ctrl_lines_t;
+	function idecoder(opcode : opcode_t; iphase : iphase_t; status : cpu_status_t) return ctrl_lines_t;
+	function gen_murom return murom_t;
+	function get_muromaddr (opcode : opcode_t; iphase : iphase_t; status : cpu_status_t) return unsigned;
+	function MIN (X, Y: INTEGER) return INTEGER;
+	function MAX (X, Y: INTEGER) return INTEGER;
+
+end cpu_pkg;
+
+package body cpu_pkg is
+
+	function Instr(opcode : opcode_t) return inst_t is
+	variable inst : inst_t := (others => '0'); 
+	begin
+		inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode;
+		return inst;
+
+	end Instr;
+
+	function Instr(opcode : opcode_t; data : inst_data_t) return inst_t is
+	variable inst : inst_t := (others => '0'); 
+	begin
+		inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode;
+		inst(inst_t'length-opcode_t'length-1 downto inst_t'length-opcode_t'length-inst_addr_t'length) := data;
+		return inst;
+
+	end Instr;
+
+	function Instr(opcode : opcode_t; data : inst_data_t; reg : integer) return inst_t is
+	variable inst : inst_t := (others => '0');
+	begin
+		inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode;
+		inst(inst_t'length-opcode_t'length-1 downto inst_t'length-opcode_t'length-inst_data_t'length) := data;
+		inst(reg_ptr_t'length-1 downto 0) := reg_ptr_t(to_unsigned(reg, reg_ptr_t'length));
+
+		return inst;
+
+	end Instr;
+
+	function Instr(opcode : opcode_t; reg_a : integer) return inst_t is
+	variable inst : inst_t := (others => '0');
+	begin
+		inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode;
+		inst(reg_ptr_t'length-1 downto 0) := reg_ptr_t(to_unsigned(reg_a, reg_ptr_t'length));
+
+		return inst;
+
+	end Instr;
+
+	function Instr(opcode : opcode_t; reg_a, reg_b : integer) return inst_t is
+	variable inst : inst_t := (others => '0');
+	begin
+		inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode;
+		inst(2*(reg_ptr_t'length)-1 downto reg_ptr_t'length) := reg_ptr_t(to_unsigned(reg_b, reg_ptr_t'length));
+		inst(reg_ptr_t'length-1 downto 0) := reg_ptr_t(to_unsigned(reg_a, reg_ptr_t'length));
+
+		return inst;
+
+	end Instr;
+
+	function Instr(opcode : opcode_t; reg_a, reg_b, reg_c : integer) return inst_t is
+	variable inst : inst_t := (others => '0');
+	begin
+		inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode;
+		inst(3*(reg_ptr_t'length)-1 downto 2*reg_ptr_t'length) := reg_ptr_t(to_unsigned(reg_c, reg_ptr_t'length));
+		inst(2*(reg_ptr_t'length)-1 downto reg_ptr_t'length) := reg_ptr_t(to_unsigned(reg_b, reg_ptr_t'length));
+		inst(reg_ptr_t'length-1 downto 0) := reg_ptr_t(to_unsigned(reg_a, reg_ptr_t'length));
+
+		return inst;
+
+	end Instr;
+
+	function ctrl_lines_default return ctrl_lines_t is
+	variable result : ctrl_lines_t;
+	begin
+		result.pc_load := '0';
+		result.pc_inc := '0';
+		result.stk_push := '0';
+		result.stk_pop := '0';
+		result.stk_pushd := '0';
+		result.stk_popd := '0';
+		result.reg_we := '0';
+		result.reg_src_sel := alu_src;
+		result.ddata_src_sel := reg_a;
+		result.daddr_src_sel := reg_b;
+		result.alu_opsel := pass_op2;
+		result.alu_op1_src_sel := reg_a;
+		result.alu_op2_src_sel := reg_b;
+		result.alu_load := '0';
+		result.alu_cy_in := '0';
+		result.mem_access := cmem_access;
+		result.mem_read := '0';
+		result.mem_write := '0';
+		result.int_exit := '0';
+		return result;
+	
+	end ctrl_lines_default;
+
+	function idecoder(opcode : opcode_t; iphase : iphase_t; status : cpu_status_t) return ctrl_lines_t is
+	variable instr_name : instr_name_t;
+	begin
+		instr_name := instr_name_array(to_integer(opcode));
+		return idecoder(instr_name, iphase, status);
+	end idecoder;
+
+	function idecoder(instr_name : instr_name_t; iphase : iphase_t; status : cpu_status_t) return ctrl_lines_t is
+	variable result : ctrl_lines_t;
+	variable ze, cy, xmem_wait : STD_LOGIC;
+	
+	begin
+		ze			:= status.alu.zero;
+		cy			:= status.alu.carry;
+		xmem_wait	:= status.xmem_wait;
+		
+		result := ctrl_lines_default;
+		if iphase = 0 then
+			result.pc_inc := '1';
+		end if;
+
+		case instr_name is
+
+		when "HALT        " =>
+			result.pc_inc := '0';
+		when "SETC        " => -- carry <= 1
+			result.reg_src_sel := alu_src;
+			result.alu_opsel := pass_op2;
+			result.alu_op2_src_sel := reg_b;
+			result.alu_load := '1';
+			result.alu_cy_in := '1';
+		when "MOV|R|R     " => -- R(a) <= R(b)
+			result.reg_src_sel := alu_src;
+			result.alu_opsel := pass_op2;
+			result.alu_op2_src_sel := reg_b;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "MOV|R|K     " => -- R(a) <= #kk
+			result.reg_src_sel := alu_src;
+			result.alu_opsel := pass_op2;
+			result.alu_op2_src_sel := const;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "MOVC|Ri|R   " => -- [R(b)] <= R(a)
+			result.mem_access := cmem_access;
+			result.daddr_src_sel := reg_b;
+			result.ddata_src_sel := reg_a;
+			if iphase = 0 then
+				result.mem_write := '1';
+			end if;
+		when "MOVC|Ri|K   " => -- [R(a)] <= kk
+			result.mem_access := cmem_access;
+			result.daddr_src_sel := reg_a;
+			result.ddata_src_sel := const;
+			if iphase = 0 then
+				result.mem_write := '1';
+			end if;
+		when "COUT|Ri|K   " => -- [R(a)] <= kk
+			result.mem_access := cio_access;
+			result.daddr_src_sel := reg_a;
+			result.ddata_src_sel := const;
+			if iphase = 0 then
+				result.mem_write := '1';
+			end if;
+		when "MOVC|R|Ri   " => -- R(a) <= [R(b)]
+			result.mem_access := cmem_access;
+			result.reg_src_sel := cmem_src;
+			result.daddr_src_sel := reg_b;
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "MOVC|R|Ki   " => -- R(a) <= [#addr]
+			result.mem_access := cmem_access;
+			result.reg_src_sel := cmem_src;
+			result.daddr_src_sel := const;
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "CIN|R|Ki    " => -- R(a) <= [#addr]
+			result.mem_access := cio_access;
+			result.reg_src_sel := cmem_src;
+			result.daddr_src_sel := const;
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "MOVC|Ki|R   " => -- [#addr] <= R(a)
+			result.mem_access := cmem_access;
+			result.daddr_src_sel := const;
+			result.ddata_src_sel := reg_a;
+			if iphase = 0 then
+				result.mem_write := '1';
+			end if;
+		when "COUT|Ki|R   " => -- [#addr] <= R(a)
+			result.mem_access := cio_access;
+			result.daddr_src_sel := const;
+			result.ddata_src_sel := reg_a;
+			if iphase = 0 then
+				result.mem_write := '1';
+			end if;
+		when "MOVX|Ri|R   " => -- [R(b)] <= R(a)
+			result.mem_access := xmem_access;
+			result.daddr_src_sel := reg_b;
+			result.ddata_src_sel := reg_a;
+			if iphase = 0 then
+				result.mem_write := '1';
+			end if;
+			if xmem_wait = '1' then
+				result.mem_write := '1';
+				result.pc_inc := '0';
+			end if;
+		when "MOVX|Ri|K   " => -- [R(a)] <= kk
+			result.mem_access := xmem_access;
+			result.daddr_src_sel := reg_a;
+			result.ddata_src_sel := const;
+			if iphase = 0 then
+				result.mem_write := '1';
+			end if;
+			if xmem_wait = '1' then
+				result.mem_write := '1';
+				result.pc_inc := '0';
+			end if;
+		when "XOUT|Ri|K   " => -- [R(a)] <= kk
+			result.mem_access := xio_access;
+			result.daddr_src_sel := reg_a;
+			result.ddata_src_sel := const;
+			if iphase = 0 then
+				result.mem_write := '1';
+			end if;
+			if xmem_wait = '1' then
+				result.pc_inc := '0';
+				result.mem_write := '1';
+			end if;
+		when "MOVX|R|Ri   " => -- R(a) <= [R(b)]
+			result.mem_access := xmem_access;
+			result.reg_src_sel := xmem_src;
+			result.daddr_src_sel := reg_b;
+			if iphase = 0 then
+				result.mem_read := '1';
+			end if;
+			if xmem_wait = '0' then
+				if iphase = 1 then
+					result.reg_we := '1';
+				end if;
+			else
+				result.pc_inc := '0';
+				result.mem_read := '1';
+			end if;
+		when "MOVX|R|Ki   " => -- R(a) <= [#addr]
+			result.mem_access := xmem_access;
+			result.reg_src_sel := xmem_src;
+			result.daddr_src_sel := const;
+			if iphase = 0 then
+				result.mem_read := '1';
+			end if;
+			if xmem_wait = '0' then
+				if iphase = 1 then
+					result.reg_we := '1';
+				end if;
+			else
+				result.pc_inc := '0';
+				result.mem_read := '1';
+			end if;
+		when "XIN|R|Ki    " => -- R(a) <= [#addr]
+			result.mem_access := xio_access;
+			result.reg_src_sel := xmem_src;
+			result.daddr_src_sel := const;
+			if iphase = 0 then
+				result.mem_read := '1';
+			end if;
+			if xmem_wait = '0' then
+				if iphase = 1 then
+					result.reg_we := '1';
+				end if;
+			else
+				result.pc_inc := '0';
+				result.mem_read := '1';
+			end if;
+		when "MOVX|Ki|R   " => -- [#addr] <= R(a)
+			result.mem_access := xmem_access;
+			result.daddr_src_sel := const;
+			result.ddata_src_sel := reg_a;
+			if iphase = 0 then
+				result.mem_write := '1';
+			end if;
+			if xmem_wait = '1' then
+				result.pc_inc := '0';
+				result.mem_write := '1';
+			end if;
+		when "XOUT|Ki|R   " => -- [#addr] <= R(a)
+			result.mem_access := xio_access;
+			result.daddr_src_sel := const;
+			result.ddata_src_sel := reg_a;
+			if iphase = 0 then
+				result.mem_write := '1';
+			end if;
+			if xmem_wait = '1' then
+				result.pc_inc := '0';
+				result.mem_write := '1';
+			end if;
+		when "ADD|R|R     " => -- R(a) <= R(a) + R(b)
+			result.alu_opsel := op1_add_op2;
+			result.alu_op1_src_sel := reg_a;
+			result.alu_op2_src_sel := reg_b;
+			result.reg_src_sel := alu_src;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "ADD|R|K     " => -- R(a) <= R(a) + k
+			result.alu_opsel := op1_add_op2;
+			result.alu_op1_src_sel := reg_a;
+			result.alu_op2_src_sel := const;
+			result.reg_src_sel := alu_src;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "ADDC|R|R    " => -- R(a) <= R(a) + R(b)
+			result.alu_opsel := op1_addc_op2;
+			result.alu_op1_src_sel := reg_a;
+			result.alu_op2_src_sel := reg_b;
+			result.reg_src_sel := alu_src;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "ADDC|R|K    " => -- R(a) <= R(a) + k
+			result.alu_opsel := op1_addc_op2;
+			result.alu_op1_src_sel := reg_a;
+			result.alu_op2_src_sel := const;
+			result.reg_src_sel := alu_src;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "SUB|R|R     " => -- R(a) <= R(a) + R(b)
+			result.alu_opsel := op1_sub_op2;
+			result.alu_op1_src_sel := reg_a;
+			result.alu_op2_src_sel := reg_b;
+			result.reg_src_sel := alu_src;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "SUB|R|K     " => -- R(a) <= R(a) + k
+			result.alu_opsel := op1_sub_op2;
+			result.alu_op1_src_sel := reg_a;
+			result.alu_op2_src_sel := const;
+			result.reg_src_sel := alu_src;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "SUB|K|R     " => -- R(a) <= k - R(a)
+			result.alu_opsel := op1_sub_op2;
+			result.alu_op1_src_sel := const;
+			result.alu_op2_src_sel := reg_a;
+			result.reg_src_sel := alu_src;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "SUBC|R|R    " => -- R(a) <= R(a) + R(b)
+			result.alu_opsel := op1_subc_op2;
+			result.alu_op1_src_sel := reg_a;
+			result.alu_op2_src_sel := reg_b;
+			result.reg_src_sel := alu_src;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "SUBC|R|K    " => -- R(a) <= R(a) + k
+			result.alu_opsel := op1_subc_op2;
+			result.alu_op1_src_sel := reg_a;
+			result.alu_op2_src_sel := const;
+			result.reg_src_sel := alu_src;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "SUBC|K|R    " => -- R(a) <= K - R(a)
+			result.alu_opsel := op1_subc_op2;
+			result.alu_op1_src_sel := const;
+			result.alu_op2_src_sel := reg_a;
+			result.reg_src_sel := alu_src;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "AND|R|R     " => -- R(a) <= R(a) and R(b)
+			result.alu_opsel := op1_and_op2;
+			result.alu_op1_src_sel := reg_a;
+			result.alu_op2_src_sel := reg_b;
+			result.reg_src_sel := alu_src;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "AND|R|K     " => -- R(a) <= R(a) and k
+			result.alu_opsel := op1_and_op2;
+			result.alu_op1_src_sel := reg_a;
+			result.alu_op2_src_sel := const;
+			result.reg_src_sel := alu_src;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "OR|R|R      " => -- R(a) <= R(a) or R(b)
+			result.alu_opsel := op1_or_op2;
+			result.alu_op1_src_sel := reg_a;
+			result.alu_op2_src_sel := reg_b;
+			result.reg_src_sel := alu_src;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "OR|R|K      " => -- R(a) <= R(a) or R(b)
+			result.alu_opsel := op1_or_op2;
+			result.alu_op1_src_sel := reg_a;
+			result.alu_op2_src_sel := const;
+			result.reg_src_sel := alu_src;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "XOR|R|R     " => -- R(a) <= R(a) xor R(b)
+			result.alu_opsel := op1_xor_op2;
+			result.alu_op1_src_sel := reg_a;
+			result.alu_op2_src_sel := reg_b;
+			result.reg_src_sel := alu_src;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "XOR|R|K     " => -- R(a) <= R(a) xor R(b)
+			result.alu_opsel := op1_xor_op2;
+			result.alu_op1_src_sel := reg_a;
+			result.alu_op2_src_sel := const;
+			result.reg_src_sel := alu_src;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "SWAP|R      " => -- R(a) <= R(b)
+			result.reg_src_sel := alu_src;
+			result.alu_opsel := swap_op;
+			result.alu_op1_src_sel := reg_a;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "SHL|R       " => -- R(a) <= R(a) xor R(b)
+			result.reg_src_sel := alu_src;
+			result.alu_opsel := shl_op;
+			result.alu_op1_src_sel := reg_a;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "SHR|R       " => -- R(a) <= R(a) xor R(b)
+			result.reg_src_sel := alu_src;
+			result.alu_opsel := shr_op;
+			result.alu_op1_src_sel := reg_a;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "ROL|R       " => -- R(a) <= R(a) xor R(b)
+			result.reg_src_sel := alu_src;
+			result.alu_opsel := rol_op;
+			result.alu_op1_src_sel := reg_a;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "ROR|R       " => -- R(a) <= R(a) xor R(b)
+			result.reg_src_sel := alu_src;
+			result.alu_opsel := ror_op;
+			result.alu_op1_src_sel := reg_a;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "ROLC|R      " => -- R(a) <= R(a) xor R(b)
+			result.reg_src_sel := alu_src;
+			result.alu_opsel := rolc_op;
+			result.alu_op1_src_sel := reg_a;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "RORC|R      " => -- R(a) <= R(a) xor R(b)
+			result.reg_src_sel := alu_src;
+			result.alu_opsel := rorc_op;
+			result.alu_op1_src_sel := reg_a;
+			result.alu_load := '1';
+			if iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "CMP|R|R     " => -- 
+			result.alu_opsel := op1_sub_op2;
+			result.alu_op1_src_sel := reg_a;
+			result.alu_op2_src_sel := reg_b;
+			result.alu_load := '1';
+		when "CMP|R|K     " => -- 
+			result.alu_opsel := op1_sub_op2;
+			result.alu_op1_src_sel := reg_a;
+			result.alu_op2_src_sel := const;
+			result.alu_load := '1';
+		when "JMP|K       " => -- PC <= #addr
+			if iphase = 0 then
+				result.pc_load := '1';
+			end if;
+		when "JZ|K        " => -- PC <= #addr, zero
+			if iphase = 0 then
+				if ze = '1' then
+					result.pc_load := '1';
+				end if;
+			end if;
+		when "JNZ|K       " => -- PC <= #addr, !zero
+			if iphase = 0 then
+				if ze = '0' then
+					result.pc_load := '1';
+				end if;
+			end if;
+		when "JC|K        " => -- PC <= #addr, carry
+			if iphase = 0 then
+				if cy = '1' then
+					result.pc_load := '1';
+				end if;
+			end if;
+		when "JNC|K       " => -- PC <= #addr, !carry
+			if iphase = 0 then
+				if cy = '0' then
+					result.pc_load := '1';
+				end if;
+			end if;
+		when "JLT|K       " => -- PC <= #addr, !carry
+			if iphase = 0 then
+				if cy = '1' then
+					result.pc_load := '1';
+				end if;
+			end if;
+		when "JGT|K       " => -- 
+			if iphase = 0 then
+				if (cy or ze) = '0' then
+					result.pc_load := '1';
+				end if;
+			end if;
+		when "JLE|K       " => -- 
+			if iphase = 0 then
+				if (cy xor ze) = '1' then
+					result.pc_load := '1';
+				end if;
+			end if;
+		when "JGE|K       " => -- 
+			if iphase = 0 then
+				if (not cy or ze) = '1' then
+					result.pc_load := '1';
+				end if;
+			end if;
+		when "JEQ|K       " => -- 
+			if iphase = 0 then
+				if ze = '1' then
+					result.pc_load := '1';
+				end if;
+			end if;
+		when "JNE|K       " => -- 
+			if iphase = 0 then
+				if ze = '0' then
+					result.pc_load := '1';
+				end if;
+			end if;
+		when "PUSH|R      " => -- push
+			if iphase = 0 then
+				result.stk_pushd := '1';
+			end if;
+		when "POP|R       " => -- pop
+			result.reg_src_sel := stk_src;
+			if iphase = 0 then
+				result.stk_popd := '1';
+			elsif iphase = 1 then
+				result.reg_we := '1';
+			end if;
+		when "CALL|K      " => -- call
+			if iphase = 0 then
+				result.pc_load := '1';
+				result.stk_push := '1';
+			end if;
+		when "RET         " => -- return
+			if iphase = 0 then
+				result.pc_load := '1';
+				result.stk_pop := '1';
+			end if;
+		when "RETI        " => -- return
+			result.pc_inc := '0';
+			result.int_exit := '1';
+			
+		when others => null; -- nop
+		end case;
+
+		return result;
+
+	end idecoder;
+
+	function gen_murom return murom_t is
+	variable result : murom_t; 
+	variable opcode : opcode_t;
+	variable iphase : iphase_t;
+	variable addr : unsigned(MUCODE_ADDR_WIDTH-1 downto 0);
+	variable status : cpu_status_t;
+	variable pos : integer := 0;
+	
+	begin
+		for i in 0 to 2**addr'length-1 loop
+			addr := to_unsigned(i, addr'length);
+			opcode := addr(opcode'length-1 downto 0);
+			pos := opcode'length;
+			iphase := 0;
+			if addr(pos) = '1' then
+				iphase := 1;
+			end if;
+			pos := pos + 1;
+			status.alu.zero := addr(pos);
+			pos := pos + 1;
+			status.alu.carry := addr(pos);
+			pos := pos + 1;
+			status.xmem_wait := addr(pos);
+			
+			result(i) := idecoder(opcode, iphase, status);
+		end loop;
+
+		return result;
+	end gen_murom;
+
+	function get_muromaddr (opcode : opcode_t; iphase : iphase_t; status : cpu_status_t) return unsigned is
+	variable addr : unsigned(MUCODE_ADDR_WIDTH-1 downto 0);
+	begin
+		addr := status.xmem_wait & status.alu.carry & status.alu.zero & to_unsigned(iphase, 1) & opcode;
+		return addr;
+		
+	end get_muromaddr;
+
+	-------------------------------------------------------------
+	function MIN (X, Y: INTEGER) return INTEGER is
+	variable res : integer := X;
+	begin
+	if Y < X then
+		res := Y;
+	end if;
+
+	return res;
+
+	end MIN;
+
+	-------------------------------------------------------------
+	function MAX (X, Y: INTEGER) return INTEGER is
+	variable res : integer := X;
+	begin
+	if Y > X then
+		res := Y;
+	end if;
+
+	return res;
+	
+	end MAX;
+
+
+end cpu_pkg;
+

lib/CPUs/JCpu/src/core/dpath_ctrl.vhd

@@ -0,0 +1,87 @@
+--------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The datapath controller
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.cpu_pkg.all;
+
+entity dpath_ctrl is
+	Generic (
+		use_rom		: boolean := true
+	);
+	Port (
+		inst_in		: in  inst_t;
+		iphase_in	: in  iphase_t;
+		status_in	: in  cpu_status_t;
+		ctrl_out	: out dpath_ctrl_out_t;
+		idout		: out inst_addr_t;
+		ddout		: out dmem_data_t
+	);
+end dpath_ctrl;
+
+architecture Behavioral of dpath_ctrl is
+
+	signal opcode : opcode_t;
+	signal ctrl_lines : ctrl_lines_t;
+	signal dbg_iname : instr_name_t;
+	
+begin
+
+	idout <= inst_in(IMEM_ADDR_WIDTH-1 downto 0);
+	ddout <= inst_in(REG_SIZE_BITS+DMEM_DATA_WIDTH-1 downto REG_SIZE_BITS);
+	opcode <= inst_in(IMEM_DATA_WIDTH-1 downto IMEM_DATA_WIDTH-INST_OPCODE_WIDTH);
+
+	ctrl_out.reg_a_ptr <= inst_in(reg_ptr_t'length-1 downto 0);
+	ctrl_out.reg_b_ptr <= inst_in(2*(reg_ptr_t'length)-1 downto reg_ptr_t'length);
+	ctrl_out.lines <= ctrl_lines;
+
+	-- pragma translate_off
+	dbg_iname <= instr_name_array(to_integer(opcode));
+	-- pragma translate_on
+
+gen_ctrl_rom:
+if use_rom = true generate
+
+	i_dec:
+		process(opcode, iphase_in, status_in)
+		constant rom_data : murom_t := gen_murom;
+		variable addr : unsigned(MUCODE_ADDR_WIDTH-1 downto 0);
+		begin
+			addr := get_muromaddr(opcode, iphase_in, status_in);
+			ctrl_lines <= rom_data(to_integer(addr));
+		end process;
+end generate;
+
+gen_ctrl:
+if use_rom = false generate
+	i_dec:
+		process (opcode, iphase_in, status_in)
+		begin
+			ctrl_lines <= idecoder(opcode, iphase_in, status_in);
+		end process;
+end generate;
+
+end Behavioral;
+

lib/CPUs/JCpu/src/core/int_ctrl.vhd

@@ -0,0 +1,177 @@
+--------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: Interrupt controller 
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.cpu_pkg.all;
+
+entity int_ctrl is
+	Port (
+		rst				: in  STD_LOGIC;
+		clk				: in  STD_LOGIC;
+		ctrl_in			: in  int_ctrl_in_t;
+		int_in			: in  STD_LOGIC;
+		int_exit		: in  STD_LOGIC;
+		iphase_in		: in  iphase_t;
+		pc_addr_out		: out inst_addr_t;
+		int_ack_out		: out STD_LOGIC;
+		stat_save_out	: out STD_LOGIC; 
+		stat_rest_out	: out STD_LOGIC; 
+		pc_load_out		: out STD_LOGIC;
+		stk_push_out	: out STD_LOGIC;
+		stk_pop_out		: out STD_LOGIC
+	);
+end int_ctrl;
+
+architecture Behavioral of int_ctrl is
+
+	type int_state_t is (int_idle, int_inject, int_active, int_release);
+	type pin_state_t is (pin_s0, pin_s1, pin_s2);
+	
+	signal int_state, int_state_next : int_state_t;
+	signal pin_state, pin_state_next : pin_state_t;
+	signal pc_load, int_ack, stk_push, stk_pop : STD_LOGIC;
+	signal int_request : std_logic;
+	signal int_sampled : std_logic;
+	
+begin
+
+	int_ack_out		<= int_ack;
+	pc_load_out		<= pc_load;
+	stk_push_out	<= stk_push;
+	stk_pop_out		<= stk_pop;
+	
+-----------------------------------------------------------------------
+irg_ctrl_fsm:
+	process (int_state, iphase_in, int_request, int_exit)
+	begin
+
+		pc_addr_out <= to_unsigned(1, inst_addr_t'length);
+		int_state_next <= int_state;
+		int_ack <= '0';
+		pc_load <= '0';
+		stk_push <= '0';
+		stk_pop <= '0';
+
+		case int_state is
+		
+		when int_idle =>
+			if int_request = '1' and iphase_in = 1 then
+				int_state_next <= int_inject;
+			end if;
+		when int_inject =>
+			if iphase_in = 0 then
+				int_ack <= '1';
+				pc_load <= '1';
+			elsif iphase_in = 1 then
+				stk_push <= '1';
+				int_state_next <= int_active;
+			end if;
+		when int_active =>
+			if int_exit = '1' and iphase_in = 1 then
+				int_state_next <= int_release;
+			end if;
+		when int_release =>
+			if iphase_in = 0 then
+				stk_pop <= '1';
+				pc_load <= '1';
+			elsif iphase_in = 1 then
+				int_state_next <= int_idle;
+			end if;	
+		when others => 	
+			int_state_next <= int_idle;
+		end case;	
+			
+	end process;
+	
+irq_ctrl_states:
+	process (rst, clk, int_state_next)
+	begin
+		if rst = '1' then
+			int_state <= int_idle;
+		elsif rising_edge(clk) then
+			int_state <= int_state_next;
+		end if;
+	end process;
+
+-----------------------------------------------------------------------
+pin_sample:
+	process (clk)
+	begin
+		if rising_edge(clk) then
+			int_sampled <= int_in xor (not ctrl_in.polarity);
+		end if;
+	end process;
+
+-----------------------------------------------------------------------
+pin_fsm:
+	process (pin_state, int_sampled, int_ack, ctrl_in)
+	begin
+		int_request <= '0';
+		pin_state_next <= pin_state;
+		case pin_state is
+			when pin_s0 => 
+				if int_sampled = '1' or ctrl_in.request = '1' then
+					if ctrl_in.enable = '1' then
+						pin_state_next <= pin_s1;
+					end if;	
+				end if;
+			when pin_s1 => 
+				int_request <= '1';
+				if int_ack = '1' then
+					pin_state_next <= pin_s2;
+				end if;	
+			when pin_s2 =>
+				if ctrl_in.edge_sens = '0' then
+					pin_state_next <= pin_s0;
+				elsif int_sampled = '0'	then
+					pin_state_next <= pin_s0;
+				end if;
+			when others =>
+				pin_state_next <= pin_s0;
+			end case;	
+	end process;
+			
+pin_states:
+	process (rst, clk, pin_state_next)
+	begin
+		if rst = '1' then
+			pin_state <= pin_s0;
+		elsif rising_edge(clk) then
+			pin_state <= pin_state_next;
+		end if;
+	end process;
+
+-----------------------------------------------------------------------
+stat_save_restore:
+	process (clk, stk_push, stk_pop)
+	begin
+		if rising_edge(clk) then
+			stat_save_out <= stk_push;
+			stat_rest_out <= stk_pop;
+		end if;
+	end process;
+
+end Behavioral;

lib/CPUs/JCpu/src/core/pc.vhd

@@ -0,0 +1,70 @@
+--------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: Programm counter
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.cpu_pkg.all;
+
+entity pc is
+	Port (
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		inc			: in  STD_LOGIC;
+		load		: in  STD_LOGIC;
+		pc_in		: in  inst_addr_t;
+		pc_out		: out inst_addr_t;
+		pc_next		: out inst_addr_t
+	);
+end pc;
+
+architecture Behavioral of pc is
+
+begin
+
+proc_pc:
+	process(rst, clk, inc, load, pc_in)
+	variable vpc, vpc_reg: inst_addr_t;
+	begin
+		if rst = '1' then
+			vpc_reg := (others => '0');
+		elsif rising_edge(clk) then
+			if inc = '1' or load = '1' then
+				vpc_reg := vpc;
+			elsif inc = '0'	then
+				pc_next <= vpc;		
+			end if;
+		end if;
+		
+		if load = '1' then
+			vpc := pc_in;	
+		else
+			vpc := vpc_reg + 1;
+		end if;	
+		pc_out <= vpc_reg;
+		
+	end process;
+
+end Behavioral;
+

lib/CPUs/JCpu/src/core/reg_dual.vhd

@@ -0,0 +1,81 @@
+--------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: On-Chip work registers
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.cpu_pkg.all;
+
+entity reg_dual is
+	Generic (
+		addr_width : integer := 3;
+		data_width : integer := 8
+	);
+	Port (
+		clk			: in  STD_LOGIC;
+		we_a		: in  STD_LOGIC;
+		ptr_a		: in  reg_ptr_t;
+		ptr_b		: in  reg_ptr_t;
+		din_a		: in  unsigned (data_width-1 downto 0);
+		dout_a		: out unsigned (data_width-1 downto 0);
+		dout_b		: out unsigned (data_width-1 downto 0)
+	);
+end reg_dual;
+
+architecture Behavioral of reg_dual is
+
+	constant depth : integer := 2**addr_width;
+	type mem_t is array (0 to depth-1) of unsigned (data_width-1 downto 0);
+	signal addr_a, addr_b : unsigned (addr_width-1 downto 0) := (others => '0');
+
+	signal mem : mem_t;
+begin
+
+	addr_a <= TO_01(ptr_a(addr_width-1 downto 0));
+	addr_b <= TO_01(ptr_b(addr_width-1 downto 0));
+
+reg_in_ab:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if we_a = '1' then
+				mem(to_integer(addr_a)) <= din_a;
+			end if;
+		end if;	
+	end process;
+
+reg_out_a:
+	process(mem, addr_a)
+	begin
+		dout_a <= TO_01(mem(to_integer(addr_a)));
+	end process;
+
+reg_out_b:
+	process(mem, addr_b)
+	begin
+		dout_b <= TO_01(mem(to_integer(addr_b)));
+	end process;
+
+end Behavioral;
+

lib/CPUs/JCpu/src/core/stack_ctrl.vhd

@@ -0,0 +1,73 @@
+--------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The call/return/data stack
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.cpu_pkg.all;
+
+entity stack_ctrl is
+Generic (
+	addr_width : integer := 3
+);
+Port (
+	rst			: in  STD_LOGIC;
+	clk			: in  STD_LOGIC;
+	push		: in  STD_LOGIC;
+	pop			: in  STD_LOGIC;
+	ptr_out		: out unsigned (addr_width-1 downto 0);
+	din			: in  inst_addr_t;
+	dout		: out inst_addr_t;
+	mem_we		: out STD_LOGIC
+	);
+end stack_ctrl;
+
+architecture Behavioral of stack_ctrl is
+
+	signal ptr : unsigned (addr_width-1 downto 0);
+
+begin
+
+	ptr_out <= ptr;
+
+stk_ptr:
+	process(rst, clk, ptr, push, pop)
+	begin
+		if rst = '1' then
+			ptr <= (others => '0');
+			dout <= (others => '0');
+			mem_we <= '0';
+		elsif rising_edge(clk) then
+			mem_we <= push;
+			if push = '1' then
+				ptr <= ptr + 1;
+				dout <= din;
+			elsif pop = '1' then
+				ptr <= ptr - 1;
+			end if;
+		end if;
+	end process;
+
+end Behavioral;
+

lib/CPUs/JCpu/src/cpu_embedded.vhd

@@ -0,0 +1,109 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: cpu_embedded using cpu_core and rom
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+use work.cpu_pkg.all;
+
+entity cpu_embedded is
+	Port (
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
+		int_in		: in  STD_LOGIC;
+		int_ack		: out STD_LOGIC;
+		xmem_wait	: in  STD_LOGIC;
+		xmem_we		: out STD_LOGIC;
+		xmem_re		: out STD_LOGIC;
+		xmem_din	: in  unsigned (DMEM_DATA_WIDTH-1 downto 0);
+		xmem_dout	: out unsigned (DMEM_DATA_WIDTH-1 downto 0);
+		xmem_addr	: out unsigned (DMEM_ADDR_WIDTH-1 downto 0);
+		io_sel		: out STD_LOGIC
+	);
+end cpu_embedded;
+
+architecture rtl of cpu_embedded is
+
+	signal irom_data	: unsigned (IMEM_DATA_WIDTH-1 downto 0);
+	signal irom_addr : unsigned (IMEM_ADDR_WIDTH-1 downto 0);
+
+	COMPONENT cpu
+	Port (
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
+		int_in		: in  STD_LOGIC;
+		int_ack		: out STD_LOGIC;
+		xmem_wait	: in  STD_LOGIC;
+		xmem_we		: out STD_LOGIC;
+		xmem_re		: out STD_LOGIC;
+		instr_din	: in  unsigned (IMEM_DATA_WIDTH-1 downto 0);
+		instr_addr	: out unsigned (IMEM_ADDR_WIDTH-1 downto 0);
+		xmem_din	: in  unsigned (DMEM_DATA_WIDTH-1 downto 0);
+		xmem_dout	: out unsigned (DMEM_DATA_WIDTH-1 downto 0);
+		xmem_addr	: out unsigned (DMEM_DATA_WIDTH-1 downto 0);
+		io_sel		: out STD_LOGIC
+	);
+	END COMPONENT;
+
+
+	COMPONENT irom
+		Port (
+			clk			: in  STD_LOGIC;
+			ce			: in  STD_LOGIC;
+			addr		: in  inst_addr_t;
+			dout		: out inst_t
+		);
+	END COMPONENT;
+
+begin
+
+inst_cpu: cpu
+	PORT MAP(
+		rst => rst,
+		clk => clk,
+		ce => ce,
+		int_in => int_in,
+		int_ack => int_ack,
+		xmem_wait => xmem_wait,
+		xmem_we => xmem_we,
+		xmem_re => xmem_re,
+		instr_din => irom_data,
+		instr_addr => irom_addr,
+		xmem_din => xmem_din,
+		xmem_dout => xmem_dout,
+		xmem_addr => xmem_addr,
+		io_sel => io_sel
+	);
+
+inst_irom: irom
+	PORT MAP(
+		clk			=> clk,
+		ce			=> ce,
+		addr		=> irom_addr,
+		dout 		=> irom_data
+	);
+
+end rtl;

lib/CPUs/JCpu/src/dctest_irom.vhdl

@@ -0,0 +1,79 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The ROM file for use in your VHDL design
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library work;
+use work.cpu_pkg.all;
+
+-- JASM_ROM_INSERT_HERE
+ENTITY irom IS
+	Port (
+	clk			: in  STD_LOGIC;
+	ce			: in  STD_LOGIC;
+	addr		: in  inst_addr_t;
+	dout		: out inst_t
+	);
+END irom;
+
+ARCHITECTURE dctest OF irom IS 
+
+	type imem_rom_t is array (0 to 17) of inst_t;
+
+	-- Assembled from dctest.jsm
+	constant imem_rom : imem_rom_t :=
+	(
+		"110000" & X"010", -- 0x000: JMP 0x010
+		"110000" & X"011", -- 0x001: JMP 0x011
+		"000000" & X"000", -- 0x002:
+		"000000" & X"000", -- 0x003:
+		"000000" & X"000", -- 0x004:
+		"000000" & X"000", -- 0x005:
+		"000000" & X"000", -- 0x006:
+		"000000" & X"000", -- 0x007:
+		"000000" & X"000", -- 0x008:
+		"000000" & X"000", -- 0x009:
+		"000000" & X"000", -- 0x00A:
+		"000000" & X"000", -- 0x00B:
+		"000000" & X"000", -- 0x00C:
+		"000000" & X"000", -- 0x00D:
+		"000000" & X"000", -- 0x00E:
+		"000000" & X"000", -- 0x00F:
+		"110000" & X"010", -- 0x010: JMP 0x010
+		"111111" & X"000"  -- 0x011: RETI
+	);
+
+begin
+
+PROM_READ:
+	process(clk, ce)
+	begin
+		if rising_edge(clk) and ce = '1' then
+			dout <= imem_rom(to_integer(addr));
+		end if;
+	end process;
+
+end dctest;
+

lib/CPUs/JCpu/src/dctest_xrom.vhdl

@@ -0,0 +1,317 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The ROM file for use in your VHDL design
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library work;
+use work.cpu_pkg.all;
+
+-- JASM_ROM_INSERT_HERE
+ENTITY xrom IS
+	Port (
+	clk			: in  STD_LOGIC;
+	ce			: in  STD_LOGIC;
+	addr		: in  dmem_addr_t;
+	dout		: out dmem_data_t
+	);
+END xrom;
+
+ARCHITECTURE dctest OF xrom IS 
+
+	type xmem_rom_t is array (0 to 255) of dmem_data_t;
+
+	-- Assembled from dctest.jsm
+	constant xmem_rom : xmem_rom_t :=
+	(
+		X"00", -- 0x00
+		X"00", -- 0x01
+		X"00", -- 0x02
+		X"00", -- 0x03
+		X"01", -- 0x04
+		X"12", -- 0x05
+		X"41", -- 0x06
+		X"00", -- 0x07
+		X"00", -- 0x08
+		X"00", -- 0x09
+		X"00", -- 0x0A
+		X"00", -- 0x0B
+		X"00", -- 0x0C
+		X"00", -- 0x0D
+		X"00", -- 0x0E
+		X"00", -- 0x0F
+		X"00", -- 0x10
+		X"00", -- 0x11
+		X"00", -- 0x12
+		X"00", -- 0x13
+		X"00", -- 0x14
+		X"00", -- 0x15
+		X"00", -- 0x16
+		X"48", -- 0x17
+		X"61", -- 0x18
+		X"6C", -- 0x19
+		X"6C", -- 0x1A
+		X"6F", -- 0x1B
+		X"0D", -- 0x1C
+		X"0A", -- 0x1D
+		X"00", -- 0x1E
+		X"4A", -- 0x1F
+		X"65", -- 0x20
+		X"6E", -- 0x21
+		X"73", -- 0x22
+		X"00", -- 0x23
+		X"57", -- 0x24
+		X"65", -- 0x25
+		X"6C", -- 0x26
+		X"63", -- 0x27
+		X"6F", -- 0x28
+		X"6D", -- 0x29
+		X"65", -- 0x2A
+		X"20", -- 0x2B
+		X"74", -- 0x2C
+		X"6F", -- 0x2D
+		X"20", -- 0x2E
+		X"4A", -- 0x2F
+		X"41", -- 0x30
+		X"53", -- 0x31
+		X"4D", -- 0x32
+		X"20", -- 0x33
+		X"43", -- 0x34
+		X"50", -- 0x35
+		X"55", -- 0x36
+		X"00", -- 0x37
+		X"52", -- 0x38
+		X"65", -- 0x39
+		X"61", -- 0x3A
+		X"64", -- 0x3B
+		X"79", -- 0x3C
+		X"00", -- 0x3D
+		X"54", -- 0x3E
+		X"65", -- 0x3F
+		X"73", -- 0x40
+		X"74", -- 0x41
+		X"69", -- 0x42
+		X"6E", -- 0x43
+		X"67", -- 0x44
+		X"00", -- 0x45
+		X"50", -- 0x46
+		X"61", -- 0x47
+		X"73", -- 0x48
+		X"73", -- 0x49
+		X"65", -- 0x4A
+		X"64", -- 0x4B
+		X"00", -- 0x4C
+		X"45", -- 0x4D
+		X"72", -- 0x4E
+		X"72", -- 0x4F
+		X"6F", -- 0x50
+		X"72", -- 0x51
+		X"00", -- 0x52
+		X"0D", -- 0x53
+		X"0A", -- 0x54
+		X"00", -- 0x55
+		X"00", -- 0x56
+		X"00", -- 0x57
+		X"00", -- 0x58
+		X"00", -- 0x59
+		X"00", -- 0x5A
+		X"00", -- 0x5B
+		X"00", -- 0x5C
+		X"00", -- 0x5D
+		X"00", -- 0x5E
+		X"00", -- 0x5F
+		X"00", -- 0x60
+		X"00", -- 0x61
+		X"00", -- 0x62
+		X"00", -- 0x63
+		X"00", -- 0x64
+		X"00", -- 0x65
+		X"00", -- 0x66
+		X"00", -- 0x67
+		X"00", -- 0x68
+		X"00", -- 0x69
+		X"00", -- 0x6A
+		X"00", -- 0x6B
+		X"00", -- 0x6C
+		X"00", -- 0x6D
+		X"00", -- 0x6E
+		X"00", -- 0x6F
+		X"00", -- 0x70
+		X"00", -- 0x71
+		X"00", -- 0x72
+		X"00", -- 0x73
+		X"00", -- 0x74
+		X"00", -- 0x75
+		X"00", -- 0x76
+		X"00", -- 0x77
+		X"00", -- 0x78
+		X"00", -- 0x79
+		X"00", -- 0x7A
+		X"00", -- 0x7B
+		X"00", -- 0x7C
+		X"00", -- 0x7D
+		X"00", -- 0x7E
+		X"00", -- 0x7F
+		X"00", -- 0x80
+		X"00", -- 0x81
+		X"00", -- 0x82
+		X"00", -- 0x83
+		X"00", -- 0x84
+		X"00", -- 0x85
+		X"00", -- 0x86
+		X"00", -- 0x87
+		X"00", -- 0x88
+		X"00", -- 0x89
+		X"00", -- 0x8A
+		X"00", -- 0x8B
+		X"00", -- 0x8C
+		X"00", -- 0x8D
+		X"00", -- 0x8E
+		X"00", -- 0x8F
+		X"00", -- 0x90
+		X"00", -- 0x91
+		X"00", -- 0x92
+		X"00", -- 0x93
+		X"00", -- 0x94
+		X"00", -- 0x95
+		X"00", -- 0x96
+		X"00", -- 0x97
+		X"00", -- 0x98
+		X"00", -- 0x99
+		X"00", -- 0x9A
+		X"00", -- 0x9B
+		X"00", -- 0x9C
+		X"00", -- 0x9D
+		X"00", -- 0x9E
+		X"00", -- 0x9F
+		X"00", -- 0xA0
+		X"00", -- 0xA1
+		X"00", -- 0xA2
+		X"00", -- 0xA3
+		X"00", -- 0xA4
+		X"00", -- 0xA5
+		X"00", -- 0xA6
+		X"00", -- 0xA7
+		X"00", -- 0xA8
+		X"00", -- 0xA9
+		X"00", -- 0xAA
+		X"00", -- 0xAB
+		X"00", -- 0xAC
+		X"00", -- 0xAD
+		X"00", -- 0xAE
+		X"00", -- 0xAF
+		X"00", -- 0xB0
+		X"00", -- 0xB1
+		X"00", -- 0xB2
+		X"00", -- 0xB3
+		X"00", -- 0xB4
+		X"00", -- 0xB5
+		X"00", -- 0xB6
+		X"00", -- 0xB7
+		X"00", -- 0xB8
+		X"00", -- 0xB9
+		X"00", -- 0xBA
+		X"00", -- 0xBB
+		X"00", -- 0xBC
+		X"00", -- 0xBD
+		X"00", -- 0xBE
+		X"00", -- 0xBF
+		X"00", -- 0xC0
+		X"00", -- 0xC1
+		X"00", -- 0xC2
+		X"00", -- 0xC3
+		X"00", -- 0xC4
+		X"00", -- 0xC5
+		X"00", -- 0xC6
+		X"00", -- 0xC7
+		X"00", -- 0xC8
+		X"00", -- 0xC9
+		X"00", -- 0xCA
+		X"00", -- 0xCB
+		X"00", -- 0xCC
+		X"00", -- 0xCD
+		X"00", -- 0xCE
+		X"00", -- 0xCF
+		X"00", -- 0xD0
+		X"00", -- 0xD1
+		X"00", -- 0xD2
+		X"00", -- 0xD3
+		X"00", -- 0xD4
+		X"00", -- 0xD5
+		X"00", -- 0xD6
+		X"00", -- 0xD7
+		X"00", -- 0xD8
+		X"00", -- 0xD9
+		X"00", -- 0xDA
+		X"00", -- 0xDB
+		X"00", -- 0xDC
+		X"00", -- 0xDD
+		X"00", -- 0xDE
+		X"00", -- 0xDF
+		X"00", -- 0xE0
+		X"00", -- 0xE1
+		X"00", -- 0xE2
+		X"00", -- 0xE3
+		X"00", -- 0xE4
+		X"00", -- 0xE5
+		X"00", -- 0xE6
+		X"00", -- 0xE7
+		X"00", -- 0xE8
+		X"00", -- 0xE9
+		X"00", -- 0xEA
+		X"00", -- 0xEB
+		X"00", -- 0xEC
+		X"00", -- 0xED
+		X"00", -- 0xEE
+		X"00", -- 0xEF
+		X"00", -- 0xF0
+		X"00", -- 0xF1
+		X"00", -- 0xF2
+		X"00", -- 0xF3
+		X"00", -- 0xF4
+		X"00", -- 0xF5
+		X"00", -- 0xF6
+		X"00", -- 0xF7
+		X"00", -- 0xF8
+		X"00", -- 0xF9
+		X"00", -- 0xFA
+		X"00", -- 0xFB
+		X"00", -- 0xFC
+		X"00", -- 0xFD
+		X"00", -- 0xFE
+		X"00"  -- 0xFF
+	);
+
+begin
+
+PROM_READ:
+	process(clk, ce)
+	begin
+		if rising_edge(clk) and ce = '1' then
+			dout <= xmem_rom(to_integer(addr));
+		end if;
+	end process;
+
+end dctest;
+

lib/CPUs/JCpu/src/dctest_xrom_ld.vhdl

@@ -0,0 +1,413 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: loadable ROM
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+
+library work;
+use work.cpu_pkg.all;
+
+ENTITY xrom IS
+	Port (
+		clk			: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
+		addr		: in  dmem_addr_t;
+		dout		: out dmem_data_t
+	);
+	
+END xrom;
+
+ARCHITECTURE loadable OF xrom IS 
+
+	-- JASM_ROM_INSERT_HERE
+
+	-- Assembled from dctest.jsm
+	type xmem_rom_t is array (0 to 255) of dmem_data_t;
+	signal xmem_rom : xmem_rom_t :=
+	(
+		X"00", -- 0x00
+		X"00", -- 0x01
+		X"00", -- 0x02
+		X"00", -- 0x03
+		X"01", -- 0x04
+		X"12", -- 0x05
+		X"41", -- 0x06
+		X"00", -- 0x07
+		X"00", -- 0x08
+		X"00", -- 0x09
+		X"00", -- 0x0A
+		X"00", -- 0x0B
+		X"00", -- 0x0C
+		X"00", -- 0x0D
+		X"00", -- 0x0E
+		X"00", -- 0x0F
+		X"00", -- 0x10
+		X"00", -- 0x11
+		X"00", -- 0x12
+		X"00", -- 0x13
+		X"00", -- 0x14
+		X"00", -- 0x15
+		X"00", -- 0x16
+		X"48", -- 0x17
+		X"61", -- 0x18
+		X"6C", -- 0x19
+		X"6C", -- 0x1A
+		X"6F", -- 0x1B
+		X"0D", -- 0x1C
+		X"0A", -- 0x1D
+		X"00", -- 0x1E
+		X"4A", -- 0x1F
+		X"65", -- 0x20
+		X"6E", -- 0x21
+		X"73", -- 0x22
+		X"00", -- 0x23
+		X"57", -- 0x24
+		X"65", -- 0x25
+		X"6C", -- 0x26
+		X"63", -- 0x27
+		X"6F", -- 0x28
+		X"6D", -- 0x29
+		X"65", -- 0x2A
+		X"20", -- 0x2B
+		X"74", -- 0x2C
+		X"6F", -- 0x2D
+		X"20", -- 0x2E
+		X"4A", -- 0x2F
+		X"41", -- 0x30
+		X"53", -- 0x31
+		X"4D", -- 0x32
+		X"20", -- 0x33
+		X"43", -- 0x34
+		X"50", -- 0x35
+		X"55", -- 0x36
+		X"00", -- 0x37
+		X"52", -- 0x38
+		X"65", -- 0x39
+		X"61", -- 0x3A
+		X"64", -- 0x3B
+		X"79", -- 0x3C
+		X"00", -- 0x3D
+		X"54", -- 0x3E
+		X"65", -- 0x3F
+		X"73", -- 0x40
+		X"74", -- 0x41
+		X"69", -- 0x42
+		X"6E", -- 0x43
+		X"67", -- 0x44
+		X"00", -- 0x45
+		X"50", -- 0x46
+		X"61", -- 0x47
+		X"73", -- 0x48
+		X"73", -- 0x49
+		X"65", -- 0x4A
+		X"64", -- 0x4B
+		X"00", -- 0x4C
+		X"45", -- 0x4D
+		X"72", -- 0x4E
+		X"72", -- 0x4F
+		X"6F", -- 0x50
+		X"72", -- 0x51
+		X"00", -- 0x52
+		X"0D", -- 0x53
+		X"0A", -- 0x54
+		X"00", -- 0x55
+		X"00", -- 0x56
+		X"00", -- 0x57
+		X"00", -- 0x58
+		X"00", -- 0x59
+		X"00", -- 0x5A
+		X"00", -- 0x5B
+		X"00", -- 0x5C
+		X"00", -- 0x5D
+		X"00", -- 0x5E
+		X"00", -- 0x5F
+		X"00", -- 0x60
+		X"00", -- 0x61
+		X"00", -- 0x62
+		X"00", -- 0x63
+		X"00", -- 0x64
+		X"00", -- 0x65
+		X"00", -- 0x66
+		X"00", -- 0x67
+		X"00", -- 0x68
+		X"00", -- 0x69
+		X"00", -- 0x6A
+		X"00", -- 0x6B
+		X"00", -- 0x6C
+		X"00", -- 0x6D
+		X"00", -- 0x6E
+		X"00", -- 0x6F
+		X"00", -- 0x70
+		X"00", -- 0x71
+		X"00", -- 0x72
+		X"00", -- 0x73
+		X"00", -- 0x74
+		X"00", -- 0x75
+		X"00", -- 0x76
+		X"00", -- 0x77
+		X"00", -- 0x78
+		X"00", -- 0x79
+		X"00", -- 0x7A
+		X"00", -- 0x7B
+		X"00", -- 0x7C
+		X"00", -- 0x7D
+		X"00", -- 0x7E
+		X"00", -- 0x7F
+		X"00", -- 0x80
+		X"00", -- 0x81
+		X"00", -- 0x82
+		X"00", -- 0x83
+		X"00", -- 0x84
+		X"00", -- 0x85
+		X"00", -- 0x86
+		X"00", -- 0x87
+		X"00", -- 0x88
+		X"00", -- 0x89
+		X"00", -- 0x8A
+		X"00", -- 0x8B
+		X"00", -- 0x8C
+		X"00", -- 0x8D
+		X"00", -- 0x8E
+		X"00", -- 0x8F
+		X"00", -- 0x90
+		X"00", -- 0x91
+		X"00", -- 0x92
+		X"00", -- 0x93
+		X"00", -- 0x94
+		X"00", -- 0x95
+		X"00", -- 0x96
+		X"00", -- 0x97
+		X"00", -- 0x98
+		X"00", -- 0x99
+		X"00", -- 0x9A
+		X"00", -- 0x9B
+		X"00", -- 0x9C
+		X"00", -- 0x9D
+		X"00", -- 0x9E
+		X"00", -- 0x9F
+		X"00", -- 0xA0
+		X"00", -- 0xA1
+		X"00", -- 0xA2
+		X"00", -- 0xA3
+		X"00", -- 0xA4
+		X"00", -- 0xA5
+		X"00", -- 0xA6
+		X"00", -- 0xA7
+		X"00", -- 0xA8
+		X"00", -- 0xA9
+		X"00", -- 0xAA
+		X"00", -- 0xAB
+		X"00", -- 0xAC
+		X"00", -- 0xAD
+		X"00", -- 0xAE
+		X"00", -- 0xAF
+		X"00", -- 0xB0
+		X"00", -- 0xB1
+		X"00", -- 0xB2
+		X"00", -- 0xB3
+		X"00", -- 0xB4
+		X"00", -- 0xB5
+		X"00", -- 0xB6
+		X"00", -- 0xB7
+		X"00", -- 0xB8
+		X"00", -- 0xB9
+		X"00", -- 0xBA
+		X"00", -- 0xBB
+		X"00", -- 0xBC
+		X"00", -- 0xBD
+		X"00", -- 0xBE
+		X"00", -- 0xBF
+		X"00", -- 0xC0
+		X"00", -- 0xC1
+		X"00", -- 0xC2
+		X"00", -- 0xC3
+		X"00", -- 0xC4
+		X"00", -- 0xC5
+		X"00", -- 0xC6
+		X"00", -- 0xC7
+		X"00", -- 0xC8
+		X"00", -- 0xC9
+		X"00", -- 0xCA
+		X"00", -- 0xCB
+		X"00", -- 0xCC
+		X"00", -- 0xCD
+		X"00", -- 0xCE
+		X"00", -- 0xCF
+		X"00", -- 0xD0
+		X"00", -- 0xD1
+		X"00", -- 0xD2
+		X"00", -- 0xD3
+		X"00", -- 0xD4
+		X"00", -- 0xD5
+		X"00", -- 0xD6
+		X"00", -- 0xD7
+		X"00", -- 0xD8
+		X"00", -- 0xD9
+		X"00", -- 0xDA
+		X"00", -- 0xDB
+		X"00", -- 0xDC
+		X"00", -- 0xDD
+		X"00", -- 0xDE
+		X"00", -- 0xDF
+		X"00", -- 0xE0
+		X"00", -- 0xE1
+		X"00", -- 0xE2
+		X"00", -- 0xE3
+		X"00", -- 0xE4
+		X"00", -- 0xE5
+		X"00", -- 0xE6
+		X"00", -- 0xE7
+		X"00", -- 0xE8
+		X"00", -- 0xE9
+		X"00", -- 0xEA
+		X"00", -- 0xEB
+		X"00", -- 0xEC
+		X"00", -- 0xED
+		X"00", -- 0xEE
+		X"00", -- 0xEF
+		X"00", -- 0xF0
+		X"00", -- 0xF1
+		X"00", -- 0xF2
+		X"00", -- 0xF3
+		X"00", -- 0xF4
+		X"00", -- 0xF5
+		X"00", -- 0xF6
+		X"00", -- 0xF7
+		X"00", -- 0xF8
+		X"00", -- 0xF9
+		X"00", -- 0xFA
+		X"00", -- 0xFB
+		X"00", -- 0xFC
+		X"00", -- 0xFD
+		X"00", -- 0xFE
+		X"00"  -- 0xFF
+	);
+
+	signal jtag_ld_clk		: STD_LOGIC;
+	signal jtag_ld_we		: STD_LOGIC;
+	signal jtag_ld_addr		: dmem_addr_t;
+	signal jtag_ld_dout		: dmem_data_t;
+	signal jtag_ld_din		: dmem_data_t;
+	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
+	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
+	signal user_regi, user_rego : unsigned (15 downto 0);
+	constant id : unsigned (15 downto 0) := X"BEEF";
+
+begin
+
+--------------------------------------------------------------------------
+-- Virtex-4: JTAG Loader
+--------------------------------------------------------------------------
+	i00_BUFG : BUFG
+	port map
+	(
+		O => bs_clk1,
+        I => bs_clk0
+	);
+	
+	i01_BUFG : BUFG
+	port map
+	(
+		O => bs_update1,
+        I => bs_update0
+	);
+
+	BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 
+	generic map
+	(
+		JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
+	)
+	port map 
+	(
+		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
+		DRCK => bs_clk0,       -- Data register output for USER functions
+		RESET => bs_rst,       -- Reset output from TAP controller
+		SEL => bs_sel,         -- USER active output
+		SHIFT => bs_shift,     -- SHIFT output from TAP controller
+		TDI => bs_tdi,        -- TDI output from TAP controller
+		UPDATE => bs_update0,   -- UPDATE output from TAP controller
+		TDO => bs_tdo         -- Data input for USER function
+	);
+
+	jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1);
+	jtag_ld_din <= user_regi(dmem_data_t'left downto 0);
+	jtag_ld_clk <= bs_update1;
+	jtag_ld_we <= bs_sel;
+	
+sipo:
+	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
+	begin
+		if bs_rst = '1' then
+			user_regi <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
+			end if;
+		end if;
+	end process;	
+
+piso:
+	process (bs_rst, bs_clk1, bs_shift, user_rego)
+	begin
+		bs_tdo <= user_rego(0);
+		if bs_rst = '1' then
+			user_rego <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
+			else
+				user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout;	
+--				user_rego <= id;	
+			end if;
+		end if;
+	end process;	
+	
+--------------------------------------------------------------------------
+-- ROM Read/Write
+--------------------------------------------------------------------------
+PROM_READ: 
+	process(clk, ce)
+	begin
+		if rising_edge(clk) and ce = '1' then
+			dout <= xmem_rom(to_integer(addr));
+		end if;
+	end process;
+
+PROM_WRITE: 
+	process(jtag_ld_clk, jtag_ld_we)
+	begin
+		if rising_edge(jtag_ld_clk) then
+			if jtag_ld_we = '1' then
+				xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
+			else	
+				jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr));
+			end if;
+		end if;	
+	end process;
+
+--------------------------------------------------------------------------
+end loadable;

lib/CPUs/JCpu/src/itest_xrom.vhdl

@@ -0,0 +1,317 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The ROM file for use in your VHDL design
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library work;
+use work.cpu_pkg.all;
+
+-- JASM_ROM_INSERT_HERE
+ENTITY xrom IS
+	Port (
+	clk			: in  STD_LOGIC;
+	ce			: in  STD_LOGIC;
+	addr		: in  dmem_addr_t;
+	dout		: out dmem_data_t
+	);
+END xrom;
+
+ARCHITECTURE itest OF xrom IS 
+
+	type xmem_rom_t is array (0 to 255) of dmem_data_t;
+
+	-- Assembled from itest.jsm
+	constant xmem_rom : xmem_rom_t :=
+	(
+		X"48", -- 0x00
+		X"61", -- 0x01
+		X"6C", -- 0x02
+		X"6C", -- 0x03
+		X"6F", -- 0x04
+		X"00", -- 0x05
+		X"00", -- 0x06
+		X"00", -- 0x07
+		X"00", -- 0x08
+		X"00", -- 0x09
+		X"00", -- 0x0A
+		X"00", -- 0x0B
+		X"00", -- 0x0C
+		X"00", -- 0x0D
+		X"00", -- 0x0E
+		X"00", -- 0x0F
+		X"00", -- 0x10
+		X"00", -- 0x11
+		X"00", -- 0x12
+		X"00", -- 0x13
+		X"00", -- 0x14
+		X"00", -- 0x15
+		X"00", -- 0x16
+		X"00", -- 0x17
+		X"00", -- 0x18
+		X"00", -- 0x19
+		X"00", -- 0x1A
+		X"00", -- 0x1B
+		X"00", -- 0x1C
+		X"00", -- 0x1D
+		X"00", -- 0x1E
+		X"00", -- 0x1F
+		X"00", -- 0x20
+		X"00", -- 0x21
+		X"00", -- 0x22
+		X"00", -- 0x23
+		X"00", -- 0x24
+		X"00", -- 0x25
+		X"00", -- 0x26
+		X"00", -- 0x27
+		X"00", -- 0x28
+		X"00", -- 0x29
+		X"00", -- 0x2A
+		X"00", -- 0x2B
+		X"00", -- 0x2C
+		X"00", -- 0x2D
+		X"00", -- 0x2E
+		X"00", -- 0x2F
+		X"00", -- 0x30
+		X"00", -- 0x31
+		X"00", -- 0x32
+		X"00", -- 0x33
+		X"00", -- 0x34
+		X"00", -- 0x35
+		X"00", -- 0x36
+		X"00", -- 0x37
+		X"00", -- 0x38
+		X"00", -- 0x39
+		X"00", -- 0x3A
+		X"00", -- 0x3B
+		X"00", -- 0x3C
+		X"00", -- 0x3D
+		X"00", -- 0x3E
+		X"00", -- 0x3F
+		X"00", -- 0x40
+		X"00", -- 0x41
+		X"00", -- 0x42
+		X"00", -- 0x43
+		X"00", -- 0x44
+		X"00", -- 0x45
+		X"00", -- 0x46
+		X"00", -- 0x47
+		X"00", -- 0x48
+		X"00", -- 0x49
+		X"00", -- 0x4A
+		X"00", -- 0x4B
+		X"00", -- 0x4C
+		X"00", -- 0x4D
+		X"00", -- 0x4E
+		X"00", -- 0x4F
+		X"00", -- 0x50
+		X"00", -- 0x51
+		X"00", -- 0x52
+		X"00", -- 0x53
+		X"00", -- 0x54
+		X"00", -- 0x55
+		X"00", -- 0x56
+		X"00", -- 0x57
+		X"00", -- 0x58
+		X"00", -- 0x59
+		X"00", -- 0x5A
+		X"00", -- 0x5B
+		X"00", -- 0x5C
+		X"00", -- 0x5D
+		X"00", -- 0x5E
+		X"00", -- 0x5F
+		X"00", -- 0x60
+		X"00", -- 0x61
+		X"00", -- 0x62
+		X"00", -- 0x63
+		X"00", -- 0x64
+		X"00", -- 0x65
+		X"00", -- 0x66
+		X"00", -- 0x67
+		X"00", -- 0x68
+		X"00", -- 0x69
+		X"00", -- 0x6A
+		X"00", -- 0x6B
+		X"00", -- 0x6C
+		X"00", -- 0x6D
+		X"00", -- 0x6E
+		X"00", -- 0x6F
+		X"00", -- 0x70
+		X"00", -- 0x71
+		X"00", -- 0x72
+		X"00", -- 0x73
+		X"00", -- 0x74
+		X"00", -- 0x75
+		X"00", -- 0x76
+		X"00", -- 0x77
+		X"00", -- 0x78
+		X"00", -- 0x79
+		X"00", -- 0x7A
+		X"00", -- 0x7B
+		X"00", -- 0x7C
+		X"00", -- 0x7D
+		X"00", -- 0x7E
+		X"00", -- 0x7F
+		X"00", -- 0x80
+		X"00", -- 0x81
+		X"00", -- 0x82
+		X"00", -- 0x83
+		X"00", -- 0x84
+		X"00", -- 0x85
+		X"00", -- 0x86
+		X"00", -- 0x87
+		X"00", -- 0x88
+		X"00", -- 0x89
+		X"00", -- 0x8A
+		X"00", -- 0x8B
+		X"00", -- 0x8C
+		X"00", -- 0x8D
+		X"00", -- 0x8E
+		X"00", -- 0x8F
+		X"00", -- 0x90
+		X"00", -- 0x91
+		X"00", -- 0x92
+		X"00", -- 0x93
+		X"00", -- 0x94
+		X"00", -- 0x95
+		X"00", -- 0x96
+		X"00", -- 0x97
+		X"00", -- 0x98
+		X"00", -- 0x99
+		X"00", -- 0x9A
+		X"00", -- 0x9B
+		X"00", -- 0x9C
+		X"00", -- 0x9D
+		X"00", -- 0x9E
+		X"00", -- 0x9F
+		X"00", -- 0xA0
+		X"00", -- 0xA1
+		X"00", -- 0xA2
+		X"00", -- 0xA3
+		X"00", -- 0xA4
+		X"00", -- 0xA5
+		X"00", -- 0xA6
+		X"00", -- 0xA7
+		X"00", -- 0xA8
+		X"00", -- 0xA9
+		X"00", -- 0xAA
+		X"00", -- 0xAB
+		X"00", -- 0xAC
+		X"00", -- 0xAD
+		X"00", -- 0xAE
+		X"00", -- 0xAF
+		X"00", -- 0xB0
+		X"00", -- 0xB1
+		X"00", -- 0xB2
+		X"00", -- 0xB3
+		X"00", -- 0xB4
+		X"00", -- 0xB5
+		X"00", -- 0xB6
+		X"00", -- 0xB7
+		X"00", -- 0xB8
+		X"00", -- 0xB9
+		X"00", -- 0xBA
+		X"00", -- 0xBB
+		X"00", -- 0xBC
+		X"00", -- 0xBD
+		X"00", -- 0xBE
+		X"00", -- 0xBF
+		X"00", -- 0xC0
+		X"00", -- 0xC1
+		X"00", -- 0xC2
+		X"00", -- 0xC3
+		X"00", -- 0xC4
+		X"00", -- 0xC5
+		X"00", -- 0xC6
+		X"00", -- 0xC7
+		X"00", -- 0xC8
+		X"00", -- 0xC9
+		X"00", -- 0xCA
+		X"00", -- 0xCB
+		X"00", -- 0xCC
+		X"00", -- 0xCD
+		X"00", -- 0xCE
+		X"00", -- 0xCF
+		X"00", -- 0xD0
+		X"00", -- 0xD1
+		X"00", -- 0xD2
+		X"00", -- 0xD3
+		X"00", -- 0xD4
+		X"00", -- 0xD5
+		X"00", -- 0xD6
+		X"00", -- 0xD7
+		X"00", -- 0xD8
+		X"00", -- 0xD9
+		X"00", -- 0xDA
+		X"00", -- 0xDB
+		X"00", -- 0xDC
+		X"00", -- 0xDD
+		X"00", -- 0xDE
+		X"00", -- 0xDF
+		X"00", -- 0xE0
+		X"00", -- 0xE1
+		X"00", -- 0xE2
+		X"00", -- 0xE3
+		X"00", -- 0xE4
+		X"00", -- 0xE5
+		X"00", -- 0xE6
+		X"00", -- 0xE7
+		X"00", -- 0xE8
+		X"00", -- 0xE9
+		X"00", -- 0xEA
+		X"00", -- 0xEB
+		X"00", -- 0xEC
+		X"00", -- 0xED
+		X"00", -- 0xEE
+		X"00", -- 0xEF
+		X"00", -- 0xF0
+		X"00", -- 0xF1
+		X"00", -- 0xF2
+		X"00", -- 0xF3
+		X"00", -- 0xF4
+		X"00", -- 0xF5
+		X"00", -- 0xF6
+		X"00", -- 0xF7
+		X"00", -- 0xF8
+		X"00", -- 0xF9
+		X"00", -- 0xFA
+		X"00", -- 0xFB
+		X"00", -- 0xFC
+		X"00", -- 0xFD
+		X"00", -- 0xFE
+		X"00"  -- 0xFF
+	);
+
+begin
+
+PROM_READ:
+	process(clk, ce)
+	begin
+		if rising_edge(clk) and ce = '1' then
+			dout <= xmem_rom(to_integer(addr));
+		end if;
+	end process;
+
+end itest;
+

lib/CPUs/JCpu/src/itest_xrom_ld.vhdl

@@ -0,0 +1,413 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: loadable ROM
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+
+library work;
+use work.cpu_pkg.all;
+
+ENTITY xrom IS
+	Port (
+		clk			: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
+		addr		: in  dmem_addr_t;
+		dout		: out dmem_data_t
+	);
+	
+END xrom;
+
+ARCHITECTURE loadable OF xrom IS 
+
+	-- JASM_ROM_INSERT_HERE
+
+	-- Assembled from itest.jsm
+	type xmem_rom_t is array (0 to 255) of dmem_data_t;
+	signal xmem_rom : xmem_rom_t :=
+	(
+		X"48", -- 0x00
+		X"61", -- 0x01
+		X"6C", -- 0x02
+		X"6C", -- 0x03
+		X"6F", -- 0x04
+		X"00", -- 0x05
+		X"00", -- 0x06
+		X"00", -- 0x07
+		X"00", -- 0x08
+		X"00", -- 0x09
+		X"00", -- 0x0A
+		X"00", -- 0x0B
+		X"00", -- 0x0C
+		X"00", -- 0x0D
+		X"00", -- 0x0E
+		X"00", -- 0x0F
+		X"00", -- 0x10
+		X"00", -- 0x11
+		X"00", -- 0x12
+		X"00", -- 0x13
+		X"00", -- 0x14
+		X"00", -- 0x15
+		X"00", -- 0x16
+		X"00", -- 0x17
+		X"00", -- 0x18
+		X"00", -- 0x19
+		X"00", -- 0x1A
+		X"00", -- 0x1B
+		X"00", -- 0x1C
+		X"00", -- 0x1D
+		X"00", -- 0x1E
+		X"00", -- 0x1F
+		X"00", -- 0x20
+		X"00", -- 0x21
+		X"00", -- 0x22
+		X"00", -- 0x23
+		X"00", -- 0x24
+		X"00", -- 0x25
+		X"00", -- 0x26
+		X"00", -- 0x27
+		X"00", -- 0x28
+		X"00", -- 0x29
+		X"00", -- 0x2A
+		X"00", -- 0x2B
+		X"00", -- 0x2C
+		X"00", -- 0x2D
+		X"00", -- 0x2E
+		X"00", -- 0x2F
+		X"00", -- 0x30
+		X"00", -- 0x31
+		X"00", -- 0x32
+		X"00", -- 0x33
+		X"00", -- 0x34
+		X"00", -- 0x35
+		X"00", -- 0x36
+		X"00", -- 0x37
+		X"00", -- 0x38
+		X"00", -- 0x39
+		X"00", -- 0x3A
+		X"00", -- 0x3B
+		X"00", -- 0x3C
+		X"00", -- 0x3D
+		X"00", -- 0x3E
+		X"00", -- 0x3F
+		X"00", -- 0x40
+		X"00", -- 0x41
+		X"00", -- 0x42
+		X"00", -- 0x43
+		X"00", -- 0x44
+		X"00", -- 0x45
+		X"00", -- 0x46
+		X"00", -- 0x47
+		X"00", -- 0x48
+		X"00", -- 0x49
+		X"00", -- 0x4A
+		X"00", -- 0x4B
+		X"00", -- 0x4C
+		X"00", -- 0x4D
+		X"00", -- 0x4E
+		X"00", -- 0x4F
+		X"00", -- 0x50
+		X"00", -- 0x51
+		X"00", -- 0x52
+		X"00", -- 0x53
+		X"00", -- 0x54
+		X"00", -- 0x55
+		X"00", -- 0x56
+		X"00", -- 0x57
+		X"00", -- 0x58
+		X"00", -- 0x59
+		X"00", -- 0x5A
+		X"00", -- 0x5B
+		X"00", -- 0x5C
+		X"00", -- 0x5D
+		X"00", -- 0x5E
+		X"00", -- 0x5F
+		X"00", -- 0x60
+		X"00", -- 0x61
+		X"00", -- 0x62
+		X"00", -- 0x63
+		X"00", -- 0x64
+		X"00", -- 0x65
+		X"00", -- 0x66
+		X"00", -- 0x67
+		X"00", -- 0x68
+		X"00", -- 0x69
+		X"00", -- 0x6A
+		X"00", -- 0x6B
+		X"00", -- 0x6C
+		X"00", -- 0x6D
+		X"00", -- 0x6E
+		X"00", -- 0x6F
+		X"00", -- 0x70
+		X"00", -- 0x71
+		X"00", -- 0x72
+		X"00", -- 0x73
+		X"00", -- 0x74
+		X"00", -- 0x75
+		X"00", -- 0x76
+		X"00", -- 0x77
+		X"00", -- 0x78
+		X"00", -- 0x79
+		X"00", -- 0x7A
+		X"00", -- 0x7B
+		X"00", -- 0x7C
+		X"00", -- 0x7D
+		X"00", -- 0x7E
+		X"00", -- 0x7F
+		X"00", -- 0x80
+		X"00", -- 0x81
+		X"00", -- 0x82
+		X"00", -- 0x83
+		X"00", -- 0x84
+		X"00", -- 0x85
+		X"00", -- 0x86
+		X"00", -- 0x87
+		X"00", -- 0x88
+		X"00", -- 0x89
+		X"00", -- 0x8A
+		X"00", -- 0x8B
+		X"00", -- 0x8C
+		X"00", -- 0x8D
+		X"00", -- 0x8E
+		X"00", -- 0x8F
+		X"00", -- 0x90
+		X"00", -- 0x91
+		X"00", -- 0x92
+		X"00", -- 0x93
+		X"00", -- 0x94
+		X"00", -- 0x95
+		X"00", -- 0x96
+		X"00", -- 0x97
+		X"00", -- 0x98
+		X"00", -- 0x99
+		X"00", -- 0x9A
+		X"00", -- 0x9B
+		X"00", -- 0x9C
+		X"00", -- 0x9D
+		X"00", -- 0x9E
+		X"00", -- 0x9F
+		X"00", -- 0xA0
+		X"00", -- 0xA1
+		X"00", -- 0xA2
+		X"00", -- 0xA3
+		X"00", -- 0xA4
+		X"00", -- 0xA5
+		X"00", -- 0xA6
+		X"00", -- 0xA7
+		X"00", -- 0xA8
+		X"00", -- 0xA9
+		X"00", -- 0xAA
+		X"00", -- 0xAB
+		X"00", -- 0xAC
+		X"00", -- 0xAD
+		X"00", -- 0xAE
+		X"00", -- 0xAF
+		X"00", -- 0xB0
+		X"00", -- 0xB1
+		X"00", -- 0xB2
+		X"00", -- 0xB3
+		X"00", -- 0xB4
+		X"00", -- 0xB5
+		X"00", -- 0xB6
+		X"00", -- 0xB7
+		X"00", -- 0xB8
+		X"00", -- 0xB9
+		X"00", -- 0xBA
+		X"00", -- 0xBB
+		X"00", -- 0xBC
+		X"00", -- 0xBD
+		X"00", -- 0xBE
+		X"00", -- 0xBF
+		X"00", -- 0xC0
+		X"00", -- 0xC1
+		X"00", -- 0xC2
+		X"00", -- 0xC3
+		X"00", -- 0xC4
+		X"00", -- 0xC5
+		X"00", -- 0xC6
+		X"00", -- 0xC7
+		X"00", -- 0xC8
+		X"00", -- 0xC9
+		X"00", -- 0xCA
+		X"00", -- 0xCB
+		X"00", -- 0xCC
+		X"00", -- 0xCD
+		X"00", -- 0xCE
+		X"00", -- 0xCF
+		X"00", -- 0xD0
+		X"00", -- 0xD1
+		X"00", -- 0xD2
+		X"00", -- 0xD3
+		X"00", -- 0xD4
+		X"00", -- 0xD5
+		X"00", -- 0xD6
+		X"00", -- 0xD7
+		X"00", -- 0xD8
+		X"00", -- 0xD9
+		X"00", -- 0xDA
+		X"00", -- 0xDB
+		X"00", -- 0xDC
+		X"00", -- 0xDD
+		X"00", -- 0xDE
+		X"00", -- 0xDF
+		X"00", -- 0xE0
+		X"00", -- 0xE1
+		X"00", -- 0xE2
+		X"00", -- 0xE3
+		X"00", -- 0xE4
+		X"00", -- 0xE5
+		X"00", -- 0xE6
+		X"00", -- 0xE7
+		X"00", -- 0xE8
+		X"00", -- 0xE9
+		X"00", -- 0xEA
+		X"00", -- 0xEB
+		X"00", -- 0xEC
+		X"00", -- 0xED
+		X"00", -- 0xEE
+		X"00", -- 0xEF
+		X"00", -- 0xF0
+		X"00", -- 0xF1
+		X"00", -- 0xF2
+		X"00", -- 0xF3
+		X"00", -- 0xF4
+		X"00", -- 0xF5
+		X"00", -- 0xF6
+		X"00", -- 0xF7
+		X"00", -- 0xF8
+		X"00", -- 0xF9
+		X"00", -- 0xFA
+		X"00", -- 0xFB
+		X"00", -- 0xFC
+		X"00", -- 0xFD
+		X"00", -- 0xFE
+		X"00"  -- 0xFF
+	);
+
+	signal jtag_ld_clk		: STD_LOGIC;
+	signal jtag_ld_we		: STD_LOGIC;
+	signal jtag_ld_addr		: dmem_addr_t;
+	signal jtag_ld_dout		: dmem_data_t;
+	signal jtag_ld_din		: dmem_data_t;
+	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
+	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
+	signal user_regi, user_rego : unsigned (15 downto 0);
+	constant id : unsigned (15 downto 0) := X"BEEF";
+
+begin
+
+--------------------------------------------------------------------------
+-- Virtex-4: JTAG Loader
+--------------------------------------------------------------------------
+	i00_BUFG : BUFG
+	port map
+	(
+		O => bs_clk1,
+        I => bs_clk0
+	);
+	
+	i01_BUFG : BUFG
+	port map
+	(
+		O => bs_update1,
+        I => bs_update0
+	);
+
+	BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 
+	generic map
+	(
+		JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
+	)
+	port map 
+	(
+		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
+		DRCK => bs_clk0,       -- Data register output for USER functions
+		RESET => bs_rst,       -- Reset output from TAP controller
+		SEL => bs_sel,         -- USER active output
+		SHIFT => bs_shift,     -- SHIFT output from TAP controller
+		TDI => bs_tdi,        -- TDI output from TAP controller
+		UPDATE => bs_update0,   -- UPDATE output from TAP controller
+		TDO => bs_tdo         -- Data input for USER function
+	);
+
+	jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1);
+	jtag_ld_din <= user_regi(dmem_data_t'left downto 0);
+	jtag_ld_clk <= bs_update1;
+	jtag_ld_we <= bs_sel;
+	
+sipo:
+	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
+	begin
+		if bs_rst = '1' then
+			user_regi <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
+			end if;
+		end if;
+	end process;	
+
+piso:
+	process (bs_rst, bs_clk1, bs_shift, user_rego)
+	begin
+		bs_tdo <= user_rego(0);
+		if bs_rst = '1' then
+			user_rego <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
+			else
+				user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout;	
+--				user_rego <= id;	
+			end if;
+		end if;
+	end process;	
+	
+--------------------------------------------------------------------------
+-- ROM Read/Write
+--------------------------------------------------------------------------
+PROM_READ: 
+	process(clk, ce)
+	begin
+		if rising_edge(clk) and ce = '1' then
+			dout <= xmem_rom(to_integer(addr));
+		end if;
+	end process;
+
+PROM_WRITE: 
+	process(jtag_ld_clk, jtag_ld_we)
+	begin
+		if rising_edge(jtag_ld_clk) then
+			if jtag_ld_we = '1' then
+				xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
+			else	
+				jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr));
+			end if;
+		end if;	
+	end process;
+
+--------------------------------------------------------------------------
+end loadable;

lib/CPUs/JCpu/src/mul8x8_irom.vhdl

@@ -0,0 +1,88 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The ROM file for use in your VHDL design
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library work;
+use work.cpu_pkg.all;
+
+-- JASM_ROM_INSERT_HERE
+ENTITY irom IS
+	Port (
+	clk			: in  STD_LOGIC;
+	ce			: in  STD_LOGIC;
+	addr		: in  inst_addr_t;
+	dout		: out inst_t
+	);
+END irom;
+
+ARCHITECTURE mul8x8 OF irom IS 
+
+	type imem_rom_t is array (0 to 26) of inst_t;
+
+	-- Assembled from mul8x8.jsm
+	constant imem_rom : imem_rom_t :=
+	(
+		"110000" & X"001", -- 0x000: JMP 0x001
+		"000011" & X"450", -- 0x001: MOV R00, 0x45
+		"000011" & X"F51", -- 0x002: MOV R01, 0xF5
+		"111011" & X"005", -- 0x003: CALL 0x005
+		"110000" & X"004", -- 0x004: JMP 0x004
+		"111100" & X"002", -- 0x005: PUSH R02
+		"111100" & X"003", -- 0x006: PUSH R03
+		"111100" & X"004", -- 0x007: PUSH R04
+		"000010" & X"014", -- 0x008: MOV R04, R01
+		"000011" & X"001", -- 0x009: MOV R01, 0x00
+		"000011" & X"002", -- 0x00A: MOV R02, 0x00
+		"000011" & X"003", -- 0x00B: MOV R03, 0x00
+		"001111" & X"014", -- 0x00C: CMP R04, 0x01
+		"111001" & X"015", -- 0x00D: JEQ 0x015
+		"011111" & X"004", -- 0x00E: SHR R04
+		"110100" & X"012", -- 0x00F: JNC 0x012
+		"010000" & X"002", -- 0x010: ADD R02, R00
+		"010010" & X"013", -- 0x011: ADDC R03, R01
+		"011110" & X"000", -- 0x012: SHL R00
+		"100010" & X"001", -- 0x013: ROLC R01
+		"110000" & X"00C", -- 0x014: JMP 0x00C
+		"010000" & X"020", -- 0x015: ADD R00, R02
+		"010010" & X"031", -- 0x016: ADDC R01, R03
+		"111101" & X"004", -- 0x017: POP R04
+		"111101" & X"003", -- 0x018: POP R03
+		"111101" & X"002", -- 0x019: POP R02
+		"111110" & X"000"  -- 0x01A: RET
+	);
+
+begin
+
+PROM_READ:
+	process(clk, ce)
+	begin
+		if rising_edge(clk) and ce = '1' then
+			dout <= imem_rom(to_integer(addr));
+		end if;
+	end process;
+
+end mul8x8;
+

lib/CPUs/JCpu/src/mul8x8_xrom.vhdl

@@ -0,0 +1,317 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The ROM file for use in your VHDL design
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library work;
+use work.cpu_pkg.all;
+
+-- JASM_ROM_INSERT_HERE
+ENTITY xrom IS
+	Port (
+	clk			: in  STD_LOGIC;
+	ce			: in  STD_LOGIC;
+	addr		: in  dmem_addr_t;
+	dout		: out dmem_data_t
+	);
+END xrom;
+
+ARCHITECTURE mul8x8 OF xrom IS 
+
+	type xmem_rom_t is array (0 to 255) of dmem_data_t;
+
+	-- Assembled from mul8x8.jsm
+	constant xmem_rom : xmem_rom_t :=
+	(
+		X"00", -- 0x00
+		X"00", -- 0x01
+		X"00", -- 0x02
+		X"00", -- 0x03
+		X"00", -- 0x04
+		X"00", -- 0x05
+		X"00", -- 0x06
+		X"00", -- 0x07
+		X"00", -- 0x08
+		X"00", -- 0x09
+		X"00", -- 0x0A
+		X"00", -- 0x0B
+		X"00", -- 0x0C
+		X"00", -- 0x0D
+		X"00", -- 0x0E
+		X"00", -- 0x0F
+		X"00", -- 0x10
+		X"00", -- 0x11
+		X"00", -- 0x12
+		X"00", -- 0x13
+		X"00", -- 0x14
+		X"00", -- 0x15
+		X"00", -- 0x16
+		X"00", -- 0x17
+		X"00", -- 0x18
+		X"00", -- 0x19
+		X"00", -- 0x1A
+		X"00", -- 0x1B
+		X"00", -- 0x1C
+		X"00", -- 0x1D
+		X"00", -- 0x1E
+		X"00", -- 0x1F
+		X"00", -- 0x20
+		X"00", -- 0x21
+		X"00", -- 0x22
+		X"00", -- 0x23
+		X"00", -- 0x24
+		X"00", -- 0x25
+		X"00", -- 0x26
+		X"00", -- 0x27
+		X"00", -- 0x28
+		X"00", -- 0x29
+		X"00", -- 0x2A
+		X"00", -- 0x2B
+		X"00", -- 0x2C
+		X"00", -- 0x2D
+		X"00", -- 0x2E
+		X"00", -- 0x2F
+		X"00", -- 0x30
+		X"00", -- 0x31
+		X"00", -- 0x32
+		X"00", -- 0x33
+		X"00", -- 0x34
+		X"00", -- 0x35
+		X"00", -- 0x36
+		X"00", -- 0x37
+		X"00", -- 0x38
+		X"00", -- 0x39
+		X"00", -- 0x3A
+		X"00", -- 0x3B
+		X"00", -- 0x3C
+		X"00", -- 0x3D
+		X"00", -- 0x3E
+		X"00", -- 0x3F
+		X"00", -- 0x40
+		X"00", -- 0x41
+		X"00", -- 0x42
+		X"00", -- 0x43
+		X"00", -- 0x44
+		X"00", -- 0x45
+		X"00", -- 0x46
+		X"00", -- 0x47
+		X"00", -- 0x48
+		X"00", -- 0x49
+		X"00", -- 0x4A
+		X"00", -- 0x4B
+		X"00", -- 0x4C
+		X"00", -- 0x4D
+		X"00", -- 0x4E
+		X"00", -- 0x4F
+		X"00", -- 0x50
+		X"00", -- 0x51
+		X"00", -- 0x52
+		X"00", -- 0x53
+		X"00", -- 0x54
+		X"00", -- 0x55
+		X"00", -- 0x56
+		X"00", -- 0x57
+		X"00", -- 0x58
+		X"00", -- 0x59
+		X"00", -- 0x5A
+		X"00", -- 0x5B
+		X"00", -- 0x5C
+		X"00", -- 0x5D
+		X"00", -- 0x5E
+		X"00", -- 0x5F
+		X"00", -- 0x60
+		X"00", -- 0x61
+		X"00", -- 0x62
+		X"00", -- 0x63
+		X"00", -- 0x64
+		X"00", -- 0x65
+		X"00", -- 0x66
+		X"00", -- 0x67
+		X"00", -- 0x68
+		X"00", -- 0x69
+		X"00", -- 0x6A
+		X"00", -- 0x6B
+		X"00", -- 0x6C
+		X"00", -- 0x6D
+		X"00", -- 0x6E
+		X"00", -- 0x6F
+		X"00", -- 0x70
+		X"00", -- 0x71
+		X"00", -- 0x72
+		X"00", -- 0x73
+		X"00", -- 0x74
+		X"00", -- 0x75
+		X"00", -- 0x76
+		X"00", -- 0x77
+		X"00", -- 0x78
+		X"00", -- 0x79
+		X"00", -- 0x7A
+		X"00", -- 0x7B
+		X"00", -- 0x7C
+		X"00", -- 0x7D
+		X"00", -- 0x7E
+		X"00", -- 0x7F
+		X"00", -- 0x80
+		X"00", -- 0x81
+		X"00", -- 0x82
+		X"00", -- 0x83
+		X"00", -- 0x84
+		X"00", -- 0x85
+		X"00", -- 0x86
+		X"00", -- 0x87
+		X"00", -- 0x88
+		X"00", -- 0x89
+		X"00", -- 0x8A
+		X"00", -- 0x8B
+		X"00", -- 0x8C
+		X"00", -- 0x8D
+		X"00", -- 0x8E
+		X"00", -- 0x8F
+		X"00", -- 0x90
+		X"00", -- 0x91
+		X"00", -- 0x92
+		X"00", -- 0x93
+		X"00", -- 0x94
+		X"00", -- 0x95
+		X"00", -- 0x96
+		X"00", -- 0x97
+		X"00", -- 0x98
+		X"00", -- 0x99
+		X"00", -- 0x9A
+		X"00", -- 0x9B
+		X"00", -- 0x9C
+		X"00", -- 0x9D
+		X"00", -- 0x9E
+		X"00", -- 0x9F
+		X"00", -- 0xA0
+		X"00", -- 0xA1
+		X"00", -- 0xA2
+		X"00", -- 0xA3
+		X"00", -- 0xA4
+		X"00", -- 0xA5
+		X"00", -- 0xA6
+		X"00", -- 0xA7
+		X"00", -- 0xA8
+		X"00", -- 0xA9
+		X"00", -- 0xAA
+		X"00", -- 0xAB
+		X"00", -- 0xAC
+		X"00", -- 0xAD
+		X"00", -- 0xAE
+		X"00", -- 0xAF
+		X"00", -- 0xB0
+		X"00", -- 0xB1
+		X"00", -- 0xB2
+		X"00", -- 0xB3
+		X"00", -- 0xB4
+		X"00", -- 0xB5
+		X"00", -- 0xB6
+		X"00", -- 0xB7
+		X"00", -- 0xB8
+		X"00", -- 0xB9
+		X"00", -- 0xBA
+		X"00", -- 0xBB
+		X"00", -- 0xBC
+		X"00", -- 0xBD
+		X"00", -- 0xBE
+		X"00", -- 0xBF
+		X"00", -- 0xC0
+		X"00", -- 0xC1
+		X"00", -- 0xC2
+		X"00", -- 0xC3
+		X"00", -- 0xC4
+		X"00", -- 0xC5
+		X"00", -- 0xC6
+		X"00", -- 0xC7
+		X"00", -- 0xC8
+		X"00", -- 0xC9
+		X"00", -- 0xCA
+		X"00", -- 0xCB
+		X"00", -- 0xCC
+		X"00", -- 0xCD
+		X"00", -- 0xCE
+		X"00", -- 0xCF
+		X"00", -- 0xD0
+		X"00", -- 0xD1
+		X"00", -- 0xD2
+		X"00", -- 0xD3
+		X"00", -- 0xD4
+		X"00", -- 0xD5
+		X"00", -- 0xD6
+		X"00", -- 0xD7
+		X"00", -- 0xD8
+		X"00", -- 0xD9
+		X"00", -- 0xDA
+		X"00", -- 0xDB
+		X"00", -- 0xDC
+		X"00", -- 0xDD
+		X"00", -- 0xDE
+		X"00", -- 0xDF
+		X"00", -- 0xE0
+		X"00", -- 0xE1
+		X"00", -- 0xE2
+		X"00", -- 0xE3
+		X"00", -- 0xE4
+		X"00", -- 0xE5
+		X"00", -- 0xE6
+		X"00", -- 0xE7
+		X"00", -- 0xE8
+		X"00", -- 0xE9
+		X"00", -- 0xEA
+		X"00", -- 0xEB
+		X"00", -- 0xEC
+		X"00", -- 0xED
+		X"00", -- 0xEE
+		X"00", -- 0xEF
+		X"00", -- 0xF0
+		X"00", -- 0xF1
+		X"00", -- 0xF2
+		X"00", -- 0xF3
+		X"00", -- 0xF4
+		X"00", -- 0xF5
+		X"00", -- 0xF6
+		X"00", -- 0xF7
+		X"00", -- 0xF8
+		X"00", -- 0xF9
+		X"00", -- 0xFA
+		X"00", -- 0xFB
+		X"00", -- 0xFC
+		X"00", -- 0xFD
+		X"00", -- 0xFE
+		X"00"  -- 0xFF
+	);
+
+begin
+
+PROM_READ:
+	process(clk, ce)
+	begin
+		if rising_edge(clk) and ce = '1' then
+			dout <= xmem_rom(to_integer(addr));
+		end if;
+	end process;
+
+end mul8x8;
+

lib/CPUs/JCpu/src/mul8x8_xrom_ld.vhdl

@@ -0,0 +1,413 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: loadable ROM
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+
+library work;
+use work.cpu_pkg.all;
+
+ENTITY xrom IS
+	Port (
+		clk			: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
+		addr		: in  dmem_addr_t;
+		dout		: out dmem_data_t
+	);
+	
+END xrom;
+
+ARCHITECTURE loadable OF xrom IS 
+
+	-- JASM_ROM_INSERT_HERE
+
+	-- Assembled from mul8x8.jsm
+	type xmem_rom_t is array (0 to 255) of dmem_data_t;
+	signal xmem_rom : xmem_rom_t :=
+	(
+		X"00", -- 0x00
+		X"00", -- 0x01
+		X"00", -- 0x02
+		X"00", -- 0x03
+		X"00", -- 0x04
+		X"00", -- 0x05
+		X"00", -- 0x06
+		X"00", -- 0x07
+		X"00", -- 0x08
+		X"00", -- 0x09
+		X"00", -- 0x0A
+		X"00", -- 0x0B
+		X"00", -- 0x0C
+		X"00", -- 0x0D
+		X"00", -- 0x0E
+		X"00", -- 0x0F
+		X"00", -- 0x10
+		X"00", -- 0x11
+		X"00", -- 0x12
+		X"00", -- 0x13
+		X"00", -- 0x14
+		X"00", -- 0x15
+		X"00", -- 0x16
+		X"00", -- 0x17
+		X"00", -- 0x18
+		X"00", -- 0x19
+		X"00", -- 0x1A
+		X"00", -- 0x1B
+		X"00", -- 0x1C
+		X"00", -- 0x1D
+		X"00", -- 0x1E
+		X"00", -- 0x1F
+		X"00", -- 0x20
+		X"00", -- 0x21
+		X"00", -- 0x22
+		X"00", -- 0x23
+		X"00", -- 0x24
+		X"00", -- 0x25
+		X"00", -- 0x26
+		X"00", -- 0x27
+		X"00", -- 0x28
+		X"00", -- 0x29
+		X"00", -- 0x2A
+		X"00", -- 0x2B
+		X"00", -- 0x2C
+		X"00", -- 0x2D
+		X"00", -- 0x2E
+		X"00", -- 0x2F
+		X"00", -- 0x30
+		X"00", -- 0x31
+		X"00", -- 0x32
+		X"00", -- 0x33
+		X"00", -- 0x34
+		X"00", -- 0x35
+		X"00", -- 0x36
+		X"00", -- 0x37
+		X"00", -- 0x38
+		X"00", -- 0x39
+		X"00", -- 0x3A
+		X"00", -- 0x3B
+		X"00", -- 0x3C
+		X"00", -- 0x3D
+		X"00", -- 0x3E
+		X"00", -- 0x3F
+		X"00", -- 0x40
+		X"00", -- 0x41
+		X"00", -- 0x42
+		X"00", -- 0x43
+		X"00", -- 0x44
+		X"00", -- 0x45
+		X"00", -- 0x46
+		X"00", -- 0x47
+		X"00", -- 0x48
+		X"00", -- 0x49
+		X"00", -- 0x4A
+		X"00", -- 0x4B
+		X"00", -- 0x4C
+		X"00", -- 0x4D
+		X"00", -- 0x4E
+		X"00", -- 0x4F
+		X"00", -- 0x50
+		X"00", -- 0x51
+		X"00", -- 0x52
+		X"00", -- 0x53
+		X"00", -- 0x54
+		X"00", -- 0x55
+		X"00", -- 0x56
+		X"00", -- 0x57
+		X"00", -- 0x58
+		X"00", -- 0x59
+		X"00", -- 0x5A
+		X"00", -- 0x5B
+		X"00", -- 0x5C
+		X"00", -- 0x5D
+		X"00", -- 0x5E
+		X"00", -- 0x5F
+		X"00", -- 0x60
+		X"00", -- 0x61
+		X"00", -- 0x62
+		X"00", -- 0x63
+		X"00", -- 0x64
+		X"00", -- 0x65
+		X"00", -- 0x66
+		X"00", -- 0x67
+		X"00", -- 0x68
+		X"00", -- 0x69
+		X"00", -- 0x6A
+		X"00", -- 0x6B
+		X"00", -- 0x6C
+		X"00", -- 0x6D
+		X"00", -- 0x6E
+		X"00", -- 0x6F
+		X"00", -- 0x70
+		X"00", -- 0x71
+		X"00", -- 0x72
+		X"00", -- 0x73
+		X"00", -- 0x74
+		X"00", -- 0x75
+		X"00", -- 0x76
+		X"00", -- 0x77
+		X"00", -- 0x78
+		X"00", -- 0x79
+		X"00", -- 0x7A
+		X"00", -- 0x7B
+		X"00", -- 0x7C
+		X"00", -- 0x7D
+		X"00", -- 0x7E
+		X"00", -- 0x7F
+		X"00", -- 0x80
+		X"00", -- 0x81
+		X"00", -- 0x82
+		X"00", -- 0x83
+		X"00", -- 0x84
+		X"00", -- 0x85
+		X"00", -- 0x86
+		X"00", -- 0x87
+		X"00", -- 0x88
+		X"00", -- 0x89
+		X"00", -- 0x8A
+		X"00", -- 0x8B
+		X"00", -- 0x8C
+		X"00", -- 0x8D
+		X"00", -- 0x8E
+		X"00", -- 0x8F
+		X"00", -- 0x90
+		X"00", -- 0x91
+		X"00", -- 0x92
+		X"00", -- 0x93
+		X"00", -- 0x94
+		X"00", -- 0x95
+		X"00", -- 0x96
+		X"00", -- 0x97
+		X"00", -- 0x98
+		X"00", -- 0x99
+		X"00", -- 0x9A
+		X"00", -- 0x9B
+		X"00", -- 0x9C
+		X"00", -- 0x9D
+		X"00", -- 0x9E
+		X"00", -- 0x9F
+		X"00", -- 0xA0
+		X"00", -- 0xA1
+		X"00", -- 0xA2
+		X"00", -- 0xA3
+		X"00", -- 0xA4
+		X"00", -- 0xA5
+		X"00", -- 0xA6
+		X"00", -- 0xA7
+		X"00", -- 0xA8
+		X"00", -- 0xA9
+		X"00", -- 0xAA
+		X"00", -- 0xAB
+		X"00", -- 0xAC
+		X"00", -- 0xAD
+		X"00", -- 0xAE
+		X"00", -- 0xAF
+		X"00", -- 0xB0
+		X"00", -- 0xB1
+		X"00", -- 0xB2
+		X"00", -- 0xB3
+		X"00", -- 0xB4
+		X"00", -- 0xB5
+		X"00", -- 0xB6
+		X"00", -- 0xB7
+		X"00", -- 0xB8
+		X"00", -- 0xB9
+		X"00", -- 0xBA
+		X"00", -- 0xBB
+		X"00", -- 0xBC
+		X"00", -- 0xBD
+		X"00", -- 0xBE
+		X"00", -- 0xBF
+		X"00", -- 0xC0
+		X"00", -- 0xC1
+		X"00", -- 0xC2
+		X"00", -- 0xC3
+		X"00", -- 0xC4
+		X"00", -- 0xC5
+		X"00", -- 0xC6
+		X"00", -- 0xC7
+		X"00", -- 0xC8
+		X"00", -- 0xC9
+		X"00", -- 0xCA
+		X"00", -- 0xCB
+		X"00", -- 0xCC
+		X"00", -- 0xCD
+		X"00", -- 0xCE
+		X"00", -- 0xCF
+		X"00", -- 0xD0
+		X"00", -- 0xD1
+		X"00", -- 0xD2
+		X"00", -- 0xD3
+		X"00", -- 0xD4
+		X"00", -- 0xD5
+		X"00", -- 0xD6
+		X"00", -- 0xD7
+		X"00", -- 0xD8
+		X"00", -- 0xD9
+		X"00", -- 0xDA
+		X"00", -- 0xDB
+		X"00", -- 0xDC
+		X"00", -- 0xDD
+		X"00", -- 0xDE
+		X"00", -- 0xDF
+		X"00", -- 0xE0
+		X"00", -- 0xE1
+		X"00", -- 0xE2
+		X"00", -- 0xE3
+		X"00", -- 0xE4
+		X"00", -- 0xE5
+		X"00", -- 0xE6
+		X"00", -- 0xE7
+		X"00", -- 0xE8
+		X"00", -- 0xE9
+		X"00", -- 0xEA
+		X"00", -- 0xEB
+		X"00", -- 0xEC
+		X"00", -- 0xED
+		X"00", -- 0xEE
+		X"00", -- 0xEF
+		X"00", -- 0xF0
+		X"00", -- 0xF1
+		X"00", -- 0xF2
+		X"00", -- 0xF3
+		X"00", -- 0xF4
+		X"00", -- 0xF5
+		X"00", -- 0xF6
+		X"00", -- 0xF7
+		X"00", -- 0xF8
+		X"00", -- 0xF9
+		X"00", -- 0xFA
+		X"00", -- 0xFB
+		X"00", -- 0xFC
+		X"00", -- 0xFD
+		X"00", -- 0xFE
+		X"00"  -- 0xFF
+	);
+
+	signal jtag_ld_clk		: STD_LOGIC;
+	signal jtag_ld_we		: STD_LOGIC;
+	signal jtag_ld_addr		: dmem_addr_t;
+	signal jtag_ld_dout		: dmem_data_t;
+	signal jtag_ld_din		: dmem_data_t;
+	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
+	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
+	signal user_regi, user_rego : unsigned (15 downto 0);
+	constant id : unsigned (15 downto 0) := X"BEEF";
+
+begin
+
+--------------------------------------------------------------------------
+-- Virtex-4: JTAG Loader
+--------------------------------------------------------------------------
+	i00_BUFG : BUFG
+	port map
+	(
+		O => bs_clk1,
+        I => bs_clk0
+	);
+	
+	i01_BUFG : BUFG
+	port map
+	(
+		O => bs_update1,
+        I => bs_update0
+	);
+
+	BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 
+	generic map
+	(
+		JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
+	)
+	port map 
+	(
+		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
+		DRCK => bs_clk0,       -- Data register output for USER functions
+		RESET => bs_rst,       -- Reset output from TAP controller
+		SEL => bs_sel,         -- USER active output
+		SHIFT => bs_shift,     -- SHIFT output from TAP controller
+		TDI => bs_tdi,        -- TDI output from TAP controller
+		UPDATE => bs_update0,   -- UPDATE output from TAP controller
+		TDO => bs_tdo         -- Data input for USER function
+	);
+
+	jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1);
+	jtag_ld_din <= user_regi(dmem_data_t'left downto 0);
+	jtag_ld_clk <= bs_update1;
+	jtag_ld_we <= bs_sel;
+	
+sipo:
+	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
+	begin
+		if bs_rst = '1' then
+			user_regi <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
+			end if;
+		end if;
+	end process;	
+
+piso:
+	process (bs_rst, bs_clk1, bs_shift, user_rego)
+	begin
+		bs_tdo <= user_rego(0);
+		if bs_rst = '1' then
+			user_rego <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
+			else
+				user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout;	
+--				user_rego <= id;	
+			end if;
+		end if;
+	end process;	
+	
+--------------------------------------------------------------------------
+-- ROM Read/Write
+--------------------------------------------------------------------------
+PROM_READ: 
+	process(clk, ce)
+	begin
+		if rising_edge(clk) and ce = '1' then
+			dout <= xmem_rom(to_integer(addr));
+		end if;
+	end process;
+
+PROM_WRITE: 
+	process(jtag_ld_clk, jtag_ld_we)
+	begin
+		if rising_edge(jtag_ld_clk) then
+			if jtag_ld_we = '1' then
+				xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
+			else	
+				jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr));
+			end if;
+		end if;	
+	end process;
+
+--------------------------------------------------------------------------
+end loadable;

lib/CPUs/JCpu/src/reti_issue_irom.vhdl

@@ -0,0 +1,89 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The ROM file for use in your VHDL design
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library work;
+use work.cpu_pkg.all;
+
+-- JASM_ROM_INSERT_HERE
+ENTITY irom IS
+	Port (
+	clk			: in  STD_LOGIC;
+	ce			: in  STD_LOGIC;
+	addr		: in  inst_addr_t;
+	dout		: out inst_t
+	);
+END irom;
+
+ARCHITECTURE reti_issue OF irom IS 
+
+	type imem_rom_t is array (0 to 27) of inst_t;
+
+	-- Assembled from reti_issue.jsm
+	constant imem_rom : imem_rom_t :=
+	(
+		"110000" & X"002", -- 0x000: JMP 0x002
+		"111111" & X"000", -- 0x001: RETI
+		"000011" & X"050", -- 0x002: MOV R00, 0x05
+		"100110" & X"030", -- 0x003: COUT (0x03), R00
+		"000011" & X"000", -- 0x004: MOV R00, 0x00
+		"000000" & X"000", -- 0x005: NOP
+		"010001" & X"010", -- 0x006: INC R00
+		"000000" & X"000", -- 0x007: NOP
+		"111011" & X"01B", -- 0x008: CALL 0x01B
+		"000000" & X"000", -- 0x009: NOP
+		"111100" & X"003", -- 0x00A: PUSH R03
+		"000000" & X"000", -- 0x00B: NOP
+		"111100" & X"002", -- 0x00C: PUSH R02
+		"000000" & X"000", -- 0x00D: NOP
+		"111100" & X"001", -- 0x00E: PUSH R01
+		"000000" & X"000", -- 0x00F: NOP
+		"111100" & X"000", -- 0x010: PUSH R00
+		"000000" & X"000", -- 0x011: NOP
+		"111101" & X"000", -- 0x012: POP R00
+		"000000" & X"000", -- 0x013: NOP
+		"111101" & X"001", -- 0x014: POP R01
+		"000000" & X"000", -- 0x015: NOP
+		"111101" & X"002", -- 0x016: POP R02
+		"000000" & X"000", -- 0x017: NOP
+		"111101" & X"003", -- 0x018: POP R03
+		"000000" & X"000", -- 0x019: NOP
+		"110000" & X"005", -- 0x01A: JMP 0x005
+		"111110" & X"000"  -- 0x01B: RET
+	);
+
+begin
+
+PROM_READ:
+	process(clk, ce)
+	begin
+		if rising_edge(clk) and ce = '1' then
+			dout <= imem_rom(to_integer(addr));
+		end if;
+	end process;
+
+end reti_issue;
+

lib/CPUs/JCpu/src/reti_issue_xrom.vhdl

@@ -0,0 +1,317 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The ROM file for use in your VHDL design
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library work;
+use work.cpu_pkg.all;
+
+-- JASM_ROM_INSERT_HERE
+ENTITY xrom IS
+	Port (
+	clk			: in  STD_LOGIC;
+	ce			: in  STD_LOGIC;
+	addr		: in  dmem_addr_t;
+	dout		: out dmem_data_t
+	);
+END xrom;
+
+ARCHITECTURE reti_issue OF xrom IS 
+
+	type xmem_rom_t is array (0 to 255) of dmem_data_t;
+
+	-- Assembled from reti_issue.jsm
+	constant xmem_rom : xmem_rom_t :=
+	(
+		X"00", -- 0x00
+		X"00", -- 0x01
+		X"00", -- 0x02
+		X"00", -- 0x03
+		X"00", -- 0x04
+		X"00", -- 0x05
+		X"00", -- 0x06
+		X"00", -- 0x07
+		X"00", -- 0x08
+		X"00", -- 0x09
+		X"00", -- 0x0A
+		X"00", -- 0x0B
+		X"00", -- 0x0C
+		X"00", -- 0x0D
+		X"00", -- 0x0E
+		X"00", -- 0x0F
+		X"00", -- 0x10
+		X"00", -- 0x11
+		X"00", -- 0x12
+		X"00", -- 0x13
+		X"00", -- 0x14
+		X"00", -- 0x15
+		X"00", -- 0x16
+		X"00", -- 0x17
+		X"00", -- 0x18
+		X"00", -- 0x19
+		X"00", -- 0x1A
+		X"00", -- 0x1B
+		X"00", -- 0x1C
+		X"00", -- 0x1D
+		X"00", -- 0x1E
+		X"00", -- 0x1F
+		X"00", -- 0x20
+		X"00", -- 0x21
+		X"00", -- 0x22
+		X"00", -- 0x23
+		X"00", -- 0x24
+		X"00", -- 0x25
+		X"00", -- 0x26
+		X"00", -- 0x27
+		X"00", -- 0x28
+		X"00", -- 0x29
+		X"00", -- 0x2A
+		X"00", -- 0x2B
+		X"00", -- 0x2C
+		X"00", -- 0x2D
+		X"00", -- 0x2E
+		X"00", -- 0x2F
+		X"00", -- 0x30
+		X"00", -- 0x31
+		X"00", -- 0x32
+		X"00", -- 0x33
+		X"00", -- 0x34
+		X"00", -- 0x35
+		X"00", -- 0x36
+		X"00", -- 0x37
+		X"00", -- 0x38
+		X"00", -- 0x39
+		X"00", -- 0x3A
+		X"00", -- 0x3B
+		X"00", -- 0x3C
+		X"00", -- 0x3D
+		X"00", -- 0x3E
+		X"00", -- 0x3F
+		X"00", -- 0x40
+		X"00", -- 0x41
+		X"00", -- 0x42
+		X"00", -- 0x43
+		X"00", -- 0x44
+		X"00", -- 0x45
+		X"00", -- 0x46
+		X"00", -- 0x47
+		X"00", -- 0x48
+		X"00", -- 0x49
+		X"00", -- 0x4A
+		X"00", -- 0x4B
+		X"00", -- 0x4C
+		X"00", -- 0x4D
+		X"00", -- 0x4E
+		X"00", -- 0x4F
+		X"00", -- 0x50
+		X"00", -- 0x51
+		X"00", -- 0x52
+		X"00", -- 0x53
+		X"00", -- 0x54
+		X"00", -- 0x55
+		X"00", -- 0x56
+		X"00", -- 0x57
+		X"00", -- 0x58
+		X"00", -- 0x59
+		X"00", -- 0x5A
+		X"00", -- 0x5B
+		X"00", -- 0x5C
+		X"00", -- 0x5D
+		X"00", -- 0x5E
+		X"00", -- 0x5F
+		X"00", -- 0x60
+		X"00", -- 0x61
+		X"00", -- 0x62
+		X"00", -- 0x63
+		X"00", -- 0x64
+		X"00", -- 0x65
+		X"00", -- 0x66
+		X"00", -- 0x67
+		X"00", -- 0x68
+		X"00", -- 0x69
+		X"00", -- 0x6A
+		X"00", -- 0x6B
+		X"00", -- 0x6C
+		X"00", -- 0x6D
+		X"00", -- 0x6E
+		X"00", -- 0x6F
+		X"00", -- 0x70
+		X"00", -- 0x71
+		X"00", -- 0x72
+		X"00", -- 0x73
+		X"00", -- 0x74
+		X"00", -- 0x75
+		X"00", -- 0x76
+		X"00", -- 0x77
+		X"00", -- 0x78
+		X"00", -- 0x79
+		X"00", -- 0x7A
+		X"00", -- 0x7B
+		X"00", -- 0x7C
+		X"00", -- 0x7D
+		X"00", -- 0x7E
+		X"00", -- 0x7F
+		X"00", -- 0x80
+		X"00", -- 0x81
+		X"00", -- 0x82
+		X"00", -- 0x83
+		X"00", -- 0x84
+		X"00", -- 0x85
+		X"00", -- 0x86
+		X"00", -- 0x87
+		X"00", -- 0x88
+		X"00", -- 0x89
+		X"00", -- 0x8A
+		X"00", -- 0x8B
+		X"00", -- 0x8C
+		X"00", -- 0x8D
+		X"00", -- 0x8E
+		X"00", -- 0x8F
+		X"00", -- 0x90
+		X"00", -- 0x91
+		X"00", -- 0x92
+		X"00", -- 0x93
+		X"00", -- 0x94
+		X"00", -- 0x95
+		X"00", -- 0x96
+		X"00", -- 0x97
+		X"00", -- 0x98
+		X"00", -- 0x99
+		X"00", -- 0x9A
+		X"00", -- 0x9B
+		X"00", -- 0x9C
+		X"00", -- 0x9D
+		X"00", -- 0x9E
+		X"00", -- 0x9F
+		X"00", -- 0xA0
+		X"00", -- 0xA1
+		X"00", -- 0xA2
+		X"00", -- 0xA3
+		X"00", -- 0xA4
+		X"00", -- 0xA5
+		X"00", -- 0xA6
+		X"00", -- 0xA7
+		X"00", -- 0xA8
+		X"00", -- 0xA9
+		X"00", -- 0xAA
+		X"00", -- 0xAB
+		X"00", -- 0xAC
+		X"00", -- 0xAD
+		X"00", -- 0xAE
+		X"00", -- 0xAF
+		X"00", -- 0xB0
+		X"00", -- 0xB1
+		X"00", -- 0xB2
+		X"00", -- 0xB3
+		X"00", -- 0xB4
+		X"00", -- 0xB5
+		X"00", -- 0xB6
+		X"00", -- 0xB7
+		X"00", -- 0xB8
+		X"00", -- 0xB9
+		X"00", -- 0xBA
+		X"00", -- 0xBB
+		X"00", -- 0xBC
+		X"00", -- 0xBD
+		X"00", -- 0xBE
+		X"00", -- 0xBF
+		X"00", -- 0xC0
+		X"00", -- 0xC1
+		X"00", -- 0xC2
+		X"00", -- 0xC3
+		X"00", -- 0xC4
+		X"00", -- 0xC5
+		X"00", -- 0xC6
+		X"00", -- 0xC7
+		X"00", -- 0xC8
+		X"00", -- 0xC9
+		X"00", -- 0xCA
+		X"00", -- 0xCB
+		X"00", -- 0xCC
+		X"00", -- 0xCD
+		X"00", -- 0xCE
+		X"00", -- 0xCF
+		X"00", -- 0xD0
+		X"00", -- 0xD1
+		X"00", -- 0xD2
+		X"00", -- 0xD3
+		X"00", -- 0xD4
+		X"00", -- 0xD5
+		X"00", -- 0xD6
+		X"00", -- 0xD7
+		X"00", -- 0xD8
+		X"00", -- 0xD9
+		X"00", -- 0xDA
+		X"00", -- 0xDB
+		X"00", -- 0xDC
+		X"00", -- 0xDD
+		X"00", -- 0xDE
+		X"00", -- 0xDF
+		X"00", -- 0xE0
+		X"00", -- 0xE1
+		X"00", -- 0xE2
+		X"00", -- 0xE3
+		X"00", -- 0xE4
+		X"00", -- 0xE5
+		X"00", -- 0xE6
+		X"00", -- 0xE7
+		X"00", -- 0xE8
+		X"00", -- 0xE9
+		X"00", -- 0xEA
+		X"00", -- 0xEB
+		X"00", -- 0xEC
+		X"00", -- 0xED
+		X"00", -- 0xEE
+		X"00", -- 0xEF
+		X"00", -- 0xF0
+		X"00", -- 0xF1
+		X"00", -- 0xF2
+		X"00", -- 0xF3
+		X"00", -- 0xF4
+		X"00", -- 0xF5
+		X"00", -- 0xF6
+		X"00", -- 0xF7
+		X"00", -- 0xF8
+		X"00", -- 0xF9
+		X"00", -- 0xFA
+		X"00", -- 0xFB
+		X"00", -- 0xFC
+		X"00", -- 0xFD
+		X"00", -- 0xFE
+		X"00"  -- 0xFF
+	);
+
+begin
+
+PROM_READ:
+	process(clk, ce)
+	begin
+		if rising_edge(clk) and ce = '1' then
+			dout <= xmem_rom(to_integer(addr));
+		end if;
+	end process;
+
+end reti_issue;
+

lib/CPUs/JCpu/src/reti_issue_xrom_ld.vhdl

@@ -0,0 +1,413 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: loadable ROM
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+
+library work;
+use work.cpu_pkg.all;
+
+ENTITY xrom IS
+	Port (
+		clk			: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
+		addr		: in  dmem_addr_t;
+		dout		: out dmem_data_t
+	);
+	
+END xrom;
+
+ARCHITECTURE loadable OF xrom IS 
+
+	-- JASM_ROM_INSERT_HERE
+
+	-- Assembled from reti_issue.jsm
+	type xmem_rom_t is array (0 to 255) of dmem_data_t;
+	signal xmem_rom : xmem_rom_t :=
+	(
+		X"00", -- 0x00
+		X"00", -- 0x01
+		X"00", -- 0x02
+		X"00", -- 0x03
+		X"00", -- 0x04
+		X"00", -- 0x05
+		X"00", -- 0x06
+		X"00", -- 0x07
+		X"00", -- 0x08
+		X"00", -- 0x09
+		X"00", -- 0x0A
+		X"00", -- 0x0B
+		X"00", -- 0x0C
+		X"00", -- 0x0D
+		X"00", -- 0x0E
+		X"00", -- 0x0F
+		X"00", -- 0x10
+		X"00", -- 0x11
+		X"00", -- 0x12
+		X"00", -- 0x13
+		X"00", -- 0x14
+		X"00", -- 0x15
+		X"00", -- 0x16
+		X"00", -- 0x17
+		X"00", -- 0x18
+		X"00", -- 0x19
+		X"00", -- 0x1A
+		X"00", -- 0x1B
+		X"00", -- 0x1C
+		X"00", -- 0x1D
+		X"00", -- 0x1E
+		X"00", -- 0x1F
+		X"00", -- 0x20
+		X"00", -- 0x21
+		X"00", -- 0x22
+		X"00", -- 0x23
+		X"00", -- 0x24
+		X"00", -- 0x25
+		X"00", -- 0x26
+		X"00", -- 0x27
+		X"00", -- 0x28
+		X"00", -- 0x29
+		X"00", -- 0x2A
+		X"00", -- 0x2B
+		X"00", -- 0x2C
+		X"00", -- 0x2D
+		X"00", -- 0x2E
+		X"00", -- 0x2F
+		X"00", -- 0x30
+		X"00", -- 0x31
+		X"00", -- 0x32
+		X"00", -- 0x33
+		X"00", -- 0x34
+		X"00", -- 0x35
+		X"00", -- 0x36
+		X"00", -- 0x37
+		X"00", -- 0x38
+		X"00", -- 0x39
+		X"00", -- 0x3A
+		X"00", -- 0x3B
+		X"00", -- 0x3C
+		X"00", -- 0x3D
+		X"00", -- 0x3E
+		X"00", -- 0x3F
+		X"00", -- 0x40
+		X"00", -- 0x41
+		X"00", -- 0x42
+		X"00", -- 0x43
+		X"00", -- 0x44
+		X"00", -- 0x45
+		X"00", -- 0x46
+		X"00", -- 0x47
+		X"00", -- 0x48
+		X"00", -- 0x49
+		X"00", -- 0x4A
+		X"00", -- 0x4B
+		X"00", -- 0x4C
+		X"00", -- 0x4D
+		X"00", -- 0x4E
+		X"00", -- 0x4F
+		X"00", -- 0x50
+		X"00", -- 0x51
+		X"00", -- 0x52
+		X"00", -- 0x53
+		X"00", -- 0x54
+		X"00", -- 0x55
+		X"00", -- 0x56
+		X"00", -- 0x57
+		X"00", -- 0x58
+		X"00", -- 0x59
+		X"00", -- 0x5A
+		X"00", -- 0x5B
+		X"00", -- 0x5C
+		X"00", -- 0x5D
+		X"00", -- 0x5E
+		X"00", -- 0x5F
+		X"00", -- 0x60
+		X"00", -- 0x61
+		X"00", -- 0x62
+		X"00", -- 0x63
+		X"00", -- 0x64
+		X"00", -- 0x65
+		X"00", -- 0x66
+		X"00", -- 0x67
+		X"00", -- 0x68
+		X"00", -- 0x69
+		X"00", -- 0x6A
+		X"00", -- 0x6B
+		X"00", -- 0x6C
+		X"00", -- 0x6D
+		X"00", -- 0x6E
+		X"00", -- 0x6F
+		X"00", -- 0x70
+		X"00", -- 0x71
+		X"00", -- 0x72
+		X"00", -- 0x73
+		X"00", -- 0x74
+		X"00", -- 0x75
+		X"00", -- 0x76
+		X"00", -- 0x77
+		X"00", -- 0x78
+		X"00", -- 0x79
+		X"00", -- 0x7A
+		X"00", -- 0x7B
+		X"00", -- 0x7C
+		X"00", -- 0x7D
+		X"00", -- 0x7E
+		X"00", -- 0x7F
+		X"00", -- 0x80
+		X"00", -- 0x81
+		X"00", -- 0x82
+		X"00", -- 0x83
+		X"00", -- 0x84
+		X"00", -- 0x85
+		X"00", -- 0x86
+		X"00", -- 0x87
+		X"00", -- 0x88
+		X"00", -- 0x89
+		X"00", -- 0x8A
+		X"00", -- 0x8B
+		X"00", -- 0x8C
+		X"00", -- 0x8D
+		X"00", -- 0x8E
+		X"00", -- 0x8F
+		X"00", -- 0x90
+		X"00", -- 0x91
+		X"00", -- 0x92
+		X"00", -- 0x93
+		X"00", -- 0x94
+		X"00", -- 0x95
+		X"00", -- 0x96
+		X"00", -- 0x97
+		X"00", -- 0x98
+		X"00", -- 0x99
+		X"00", -- 0x9A
+		X"00", -- 0x9B
+		X"00", -- 0x9C
+		X"00", -- 0x9D
+		X"00", -- 0x9E
+		X"00", -- 0x9F
+		X"00", -- 0xA0
+		X"00", -- 0xA1
+		X"00", -- 0xA2
+		X"00", -- 0xA3
+		X"00", -- 0xA4
+		X"00", -- 0xA5
+		X"00", -- 0xA6
+		X"00", -- 0xA7
+		X"00", -- 0xA8
+		X"00", -- 0xA9
+		X"00", -- 0xAA
+		X"00", -- 0xAB
+		X"00", -- 0xAC
+		X"00", -- 0xAD
+		X"00", -- 0xAE
+		X"00", -- 0xAF
+		X"00", -- 0xB0
+		X"00", -- 0xB1
+		X"00", -- 0xB2
+		X"00", -- 0xB3
+		X"00", -- 0xB4
+		X"00", -- 0xB5
+		X"00", -- 0xB6
+		X"00", -- 0xB7
+		X"00", -- 0xB8
+		X"00", -- 0xB9
+		X"00", -- 0xBA
+		X"00", -- 0xBB
+		X"00", -- 0xBC
+		X"00", -- 0xBD
+		X"00", -- 0xBE
+		X"00", -- 0xBF
+		X"00", -- 0xC0
+		X"00", -- 0xC1
+		X"00", -- 0xC2
+		X"00", -- 0xC3
+		X"00", -- 0xC4
+		X"00", -- 0xC5
+		X"00", -- 0xC6
+		X"00", -- 0xC7
+		X"00", -- 0xC8
+		X"00", -- 0xC9
+		X"00", -- 0xCA
+		X"00", -- 0xCB
+		X"00", -- 0xCC
+		X"00", -- 0xCD
+		X"00", -- 0xCE
+		X"00", -- 0xCF
+		X"00", -- 0xD0
+		X"00", -- 0xD1
+		X"00", -- 0xD2
+		X"00", -- 0xD3
+		X"00", -- 0xD4
+		X"00", -- 0xD5
+		X"00", -- 0xD6
+		X"00", -- 0xD7
+		X"00", -- 0xD8
+		X"00", -- 0xD9
+		X"00", -- 0xDA
+		X"00", -- 0xDB
+		X"00", -- 0xDC
+		X"00", -- 0xDD
+		X"00", -- 0xDE
+		X"00", -- 0xDF
+		X"00", -- 0xE0
+		X"00", -- 0xE1
+		X"00", -- 0xE2
+		X"00", -- 0xE3
+		X"00", -- 0xE4
+		X"00", -- 0xE5
+		X"00", -- 0xE6
+		X"00", -- 0xE7
+		X"00", -- 0xE8
+		X"00", -- 0xE9
+		X"00", -- 0xEA
+		X"00", -- 0xEB
+		X"00", -- 0xEC
+		X"00", -- 0xED
+		X"00", -- 0xEE
+		X"00", -- 0xEF
+		X"00", -- 0xF0
+		X"00", -- 0xF1
+		X"00", -- 0xF2
+		X"00", -- 0xF3
+		X"00", -- 0xF4
+		X"00", -- 0xF5
+		X"00", -- 0xF6
+		X"00", -- 0xF7
+		X"00", -- 0xF8
+		X"00", -- 0xF9
+		X"00", -- 0xFA
+		X"00", -- 0xFB
+		X"00", -- 0xFC
+		X"00", -- 0xFD
+		X"00", -- 0xFE
+		X"00"  -- 0xFF
+	);
+
+	signal jtag_ld_clk		: STD_LOGIC;
+	signal jtag_ld_we		: STD_LOGIC;
+	signal jtag_ld_addr		: dmem_addr_t;
+	signal jtag_ld_dout		: dmem_data_t;
+	signal jtag_ld_din		: dmem_data_t;
+	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
+	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
+	signal user_regi, user_rego : unsigned (15 downto 0);
+	constant id : unsigned (15 downto 0) := X"BEEF";
+
+begin
+
+--------------------------------------------------------------------------
+-- Virtex-4: JTAG Loader
+--------------------------------------------------------------------------
+	i00_BUFG : BUFG
+	port map
+	(
+		O => bs_clk1,
+        I => bs_clk0
+	);
+	
+	i01_BUFG : BUFG
+	port map
+	(
+		O => bs_update1,
+        I => bs_update0
+	);
+
+	BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 
+	generic map
+	(
+		JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
+	)
+	port map 
+	(
+		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
+		DRCK => bs_clk0,       -- Data register output for USER functions
+		RESET => bs_rst,       -- Reset output from TAP controller
+		SEL => bs_sel,         -- USER active output
+		SHIFT => bs_shift,     -- SHIFT output from TAP controller
+		TDI => bs_tdi,        -- TDI output from TAP controller
+		UPDATE => bs_update0,   -- UPDATE output from TAP controller
+		TDO => bs_tdo         -- Data input for USER function
+	);
+
+	jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1);
+	jtag_ld_din <= user_regi(dmem_data_t'left downto 0);
+	jtag_ld_clk <= bs_update1;
+	jtag_ld_we <= bs_sel;
+	
+sipo:
+	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
+	begin
+		if bs_rst = '1' then
+			user_regi <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
+			end if;
+		end if;
+	end process;	
+
+piso:
+	process (bs_rst, bs_clk1, bs_shift, user_rego)
+	begin
+		bs_tdo <= user_rego(0);
+		if bs_rst = '1' then
+			user_rego <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
+			else
+				user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout;	
+--				user_rego <= id;	
+			end if;
+		end if;
+	end process;	
+	
+--------------------------------------------------------------------------
+-- ROM Read/Write
+--------------------------------------------------------------------------
+PROM_READ: 
+	process(clk, ce)
+	begin
+		if rising_edge(clk) and ce = '1' then
+			dout <= xmem_rom(to_integer(addr));
+		end if;
+	end process;
+
+PROM_WRITE: 
+	process(jtag_ld_clk, jtag_ld_we)
+	begin
+		if rising_edge(jtag_ld_clk) then
+			if jtag_ld_we = '1' then
+				xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
+			else	
+				jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr));
+			end if;
+		end if;	
+	end process;
+
+--------------------------------------------------------------------------
+end loadable;

lib/CPUs/JCpu/src/tb_cpu_embedded.vhd

@@ -0,0 +1,129 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: testbench for embedded cpu with rom
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+use std.textio.all; --  Imports the standard textio package.
+
+library work;
+use work.cpu_pkg.all;
+
+ENTITY tb_cpu_embedded IS
+END tb_cpu_embedded;
+
+ARCHITECTURE behavior OF tb_cpu_embedded IS 
+
+	COMPONENT cpu_embedded
+	Port (
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
+		int_in		: in  STD_LOGIC;
+		int_ack		: out  STD_LOGIC;
+		xmem_wait	: in STD_LOGIC;
+		xmem_we		: out STD_LOGIC;
+		xmem_re		: out STD_LOGIC;
+		xmem_din	: in  unsigned (DMEM_DATA_WIDTH-1 downto 0);
+		xmem_dout	: out unsigned (DMEM_DATA_WIDTH-1 downto 0);
+		xmem_addr	: out unsigned (DMEM_ADDR_WIDTH-1 downto 0);
+		io_sel		: out STD_LOGIC
+	);
+	END COMPONENT;
+
+	constant CLK_PERIOD : time := 10 ns;
+	type sram_t is array (integer range <>) of dmem_data_t;
+	signal rst : std_logic := '1';
+	signal clk : std_logic := '1';
+	signal ce  : std_logic := '0';
+	signal int_in : std_logic := '0';
+	signal int_ack : std_logic;
+	signal xmem_wait : std_logic := '0';
+	signal xmem_din : dmem_data_t := (others => '-');
+	signal xmem_dout : dmem_data_t;
+	signal xmem_addr : dmem_addr_t;
+	signal xmem_we : std_logic;
+	signal xmem_re : std_logic;
+	signal io_sel : std_logic;
+	signal sram : sram_t(0 to 2**dmem_addr_t'length-1);
+	
+
+BEGIN
+
+uut: cpu_embedded
+	PORT MAP(
+		rst => rst,
+		clk => clk,
+		ce => ce,
+		int_in => int_in,
+		int_ack => int_ack,
+		xmem_wait => xmem_wait,
+		xmem_we => xmem_we,
+		xmem_re => xmem_re,
+		xmem_din => xmem_din,
+		xmem_dout => xmem_dout,
+		xmem_addr => xmem_addr,
+		io_sel => io_sel
+	);
+
+CLK_GEN: process
+	begin
+		wait for CLK_PERIOD/2;
+		clk <= not clk;
+	end process;
+
+STIMULUS: process
+
+	begin
+
+		wait for 3*CLK_PERIOD;
+		rst <= '0';
+		wait for 2*CLK_PERIOD;
+	
+		wait until rising_edge(clk);
+		ce <= '1';
+	
+		wait for 1000*CLK_PERIOD;
+
+		assert false report "Test finished" severity error;
+		wait; 
+	
+	end process;
+
+SRAM_RW: process(rst, clk, xmem_addr, xmem_dout, xmem_we)
+	begin
+		if (rst = '1') then
+			xmem_din <= X"00";
+		elsif rising_edge(clk) then
+			if io_sel = '0' then
+				if xmem_we = '1' then	
+					sram(to_integer(xmem_addr)) <= xmem_dout;
+				end if;	
+				xmem_din <= to_01(sram(to_integer(xmem_addr)));
+			else
+				xmem_din <= X"FF";
+			end if;	
+		end if;
+	end process;
+	
+END;

lib/CPUs/JCpu/src/tb_cpu_itest.vhd

@@ -0,0 +1,218 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: Formal test of correct function of JCPU,
+--            also writes 'opc.lst' for JASM-assembler
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+use std.textio.all; --  Imports the standard textio package.
+
+library work;
+use work.cpu_pkg.all;
+use work.PCK_FIO.all;
+
+ENTITY tb_cpu IS
+END tb_cpu;
+
+ARCHITECTURE behavior OF tb_cpu IS 
+
+	COMPONENT cpu
+	Generic (
+		use_instr_register	: boolean;
+		use_ctrl_rom		: boolean
+	);
+	Port (
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
+		int_in		: in  STD_LOGIC;
+		int_ack		: out  STD_LOGIC;
+		xmem_wait	: in   STD_LOGIC;
+		xmem_we		: out  STD_LOGIC;
+		xmem_re		: out  STD_LOGIC;
+		instr_din	: in  unsigned (IMEM_DATA_WIDTH-1 downto 0);
+		instr_addr	: out unsigned (IMEM_ADDR_WIDTH-1 downto 0);
+		xmem_din	: in  unsigned (DMEM_DATA_WIDTH-1 downto 0);
+		xmem_dout	: out unsigned (DMEM_DATA_WIDTH-1 downto 0);
+		xmem_addr	: out unsigned (DMEM_DATA_WIDTH-1 downto 0);
+		io_sel		: out  STD_LOGIC
+		
+	);
+	END COMPONENT;
+
+	COMPONENT irom
+		Port (
+			clk			: in  STD_LOGIC;
+			ce			: in  STD_LOGIC;
+			addr		: in  inst_addr_t;
+			dout		: out inst_t
+		);
+	END COMPONENT;
+
+	constant CLK_PERIOD : time := 10 ns;
+	type prom_t is array (integer range <>) of inst_t;
+	type sram_t is array (integer range <>) of dmem_data_t;
+	signal rst : std_logic := '1';
+	signal clk : std_logic := '1';
+	signal ce  : std_logic := '0';
+	signal int_in : std_logic := '0';
+	signal int_ack : std_logic;
+	signal xmem_wait : std_logic := '1';
+	signal irom_data	: unsigned (IMEM_DATA_WIDTH-1 downto 0) := (others => '-');
+	signal irom_addr : unsigned (IMEM_ADDR_WIDTH-1 downto 0);
+	signal xmem_din : dmem_data_t := (others => '-');
+	signal xmem_dout : dmem_data_t;
+	signal xmem_addr : unsigned (DMEM_DATA_WIDTH-1 downto 0);
+	signal xmem_we : std_logic;
+	signal xmem_re : std_logic;
+	signal io_sel : std_logic;
+	signal sram : sram_t(0 to 2**DMEM_DATA_WIDTH-1);
+	
+	type reg_t is record
+		revision : dmem_data_t;
+		testid : dmem_data_t;
+		interrupt : std_logic;
+	end record;	
+	
+	signal reg : reg_t;
+	
+
+BEGIN
+
+	int_in <= reg.interrupt;
+uut: cpu
+	GENERIC MAP
+	(	
+		use_instr_register	=> false,
+		use_ctrl_rom		=> true
+	)
+	PORT MAP(
+		rst => rst,
+		clk => clk,
+		ce => ce,
+		int_in => int_in,
+		int_ack => int_ack,
+		xmem_wait => xmem_wait,
+		xmem_we => xmem_we,
+		xmem_re => xmem_re,
+		instr_din => irom_data,
+		instr_addr => irom_addr,
+		xmem_din => xmem_din,
+		xmem_dout => xmem_dout,
+		xmem_addr => xmem_addr,
+		io_sel => io_sel
+	);
+
+the_irom: irom
+	PORT MAP(
+		clk			=> clk,
+		ce			=> ce,
+		addr		=> irom_addr,
+		dout 		=> irom_data
+	);
+
+CLK_GEN: process
+	begin
+		wait for CLK_PERIOD/2;
+		clk <= not clk;
+	end process;
+
+XWAIT_GEN:process(rst, clk)
+	variable cnt : unsigned(3 downto 0);
+	begin	
+	if (rst = '1') then
+		cnt := (others => '1');
+	elsif rising_edge(clk) then
+		if cnt /= "0000" then
+			cnt := cnt - 1;
+		else
+			cnt := (others => '1');
+			xmem_wait <= not xmem_wait;
+		end if;
+	end if;
+	end process;
+
+STIMULUS: process
+	file RESULT:        text open write_mode is "../tools/opc.list"; 
+	variable L:         line;
+
+	begin
+
+		for i in 0 to instr_name_array'length-1 loop
+			fprint(RESULT, L,"%d %s\n", fo(i), instr_name_array(i));
+		end loop;	
+
+		wait for 3*CLK_PERIOD;
+		rst <= '0';
+		wait for 2*CLK_PERIOD;
+	
+		wait until rising_edge(clk);
+		ce <= '1';
+	
+		assert false report "Test finished" severity error;
+		wait; 
+	
+	end process;
+
+SRAM_RW: process(rst, clk)
+	begin
+		if (rst = '1') then
+			reg.revision <= (others => '0');
+			reg.testid <= (others => '0');
+			reg.interrupt <= '0';
+		elsif rising_edge(clk) then
+			if int_ack = '1' then
+--				reg.interrupt <= '0';
+			end if;	
+			if xmem_we = '1' then	
+				if io_sel = '0' then
+					sram(to_integer(xmem_addr)) <= xmem_dout;
+				else	
+					case xmem_addr is
+						when X"00" =>
+							reg.revision <= xmem_dout;
+						when X"01" =>
+							reg.testid <= xmem_dout;
+						when X"02" =>
+							reg.interrupt <= xmem_dout(0);
+						when others => null;
+					end case;
+				end if;	
+			else
+				if io_sel = '0' then
+					xmem_din <= to_01(sram(to_integer(xmem_addr)));
+				else
+					case xmem_addr is
+						when X"00" =>
+							xmem_din <= reg.revision;
+						when X"01" =>
+							xmem_din <= reg.testid;
+						when others =>
+							xmem_din <= X"BC";
+					end case;
+				end if;				
+			end if;	
+		end if;
+	end process;
+	
+END;

lib/CPUs/JCpu/syn/ise91/cpu_vhdl.prj

@@ -0,0 +1,10 @@
+vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\cpu_pkg.vhd"
+vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\stack_ctrl.vhd"
+vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\reg_dual.vhd"
+vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\pc.vhd"
+vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\int_ctrl.vhd"
+vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\dpath_ctrl.vhd"
+vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\chipreg.vhd"
+vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\chipram.vhd"
+vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\alu.vhd"
+vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\cpu.vhd"

lib/CPUs/JCpu/tools/eval_scan.rb

@@ -0,0 +1,42 @@
+#!/usr/bin/env ruby
+
+str1 = %Q!lbl:		dc		"Hallo", ", ", 0, 1, " der","Jens"!
+
+i=0;
+
+def get_stri_lit (str)
+	res = [""];
+	state = "out"
+	
+	j = 0;
+	k = 0;
+	for i in (0..str.length-1)
+		c = str[i];
+		nstate = state
+		case state 
+		when "out"
+			if c == "\""[0]
+				nstate = "in"
+			end
+		when "in"	
+			if c == "\""[0]
+				nstate = "out"
+				if j > 0
+					k = k + 1;
+					res[k] = ""
+				end	
+			else
+				res[k] = res[k] + format("%c", c);
+				j = j + 1;
+			end
+		end
+		state = nstate
+	end;
+	return res
+end		
+	
+get_stri_lit(str1).each do |word|
+	puts word
+end	
+ 	
+ 

lib/CPUs/JCpu/tools/insrom.rb

@@ -0,0 +1,46 @@
+#!/usr/bin/env ruby
+
+# ----------------------------------------------------------------------
+# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+# This file: Insertion of code fragments into templates
+#
+# Copyright (C) 2007 J. Ahrensfeld
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+# 
+# For questions and ideas, please contact the author at jens@jayfield.org
+#
+# ---------------------------------------------------------------------
+
+arg = $*
+rom_filename = arg[0].to_s
+tpl_filename = arg[1].to_s
+
+subst_pattern = "JASM_ROM_INSERT_HERE"
+
+# --------------------------------------------------------
+# Open file
+# --------------------------------------------------------
+romfile = File.open(rom_filename, "r")
+tplfile = File.open(tpl_filename, "r")
+re = Regexp.new(subst_pattern)
+
+while (line = tplfile.gets)
+	puts line
+	line.scan(re).each do |word|
+		romfile.each do |raw_line|
+			puts raw_line
+		end	
+	end
+end

lib/CPUs/JCpu/tools/irom.vhd.tpl

@@ -0,0 +1,32 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The ROM file for use in your VHDL design
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library work;
+use work.cpu_pkg.all;
+
+-- JASM_ROM_INSERT_HERE
+

lib/CPUs/JCpu/tools/irom_ld.vhd.tpl

@@ -0,0 +1,151 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: loadable ROM
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+
+library work;
+use work.cpu_pkg.all;
+
+ENTITY irom IS
+	Port (
+		clk			: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
+		addr		: in  inst_addr_t;
+		dout		: out inst_t
+	);
+	
+END irom;
+
+ARCHITECTURE loadable OF irom IS 
+
+	-- JASM_ROM_INSERT_HERE
+
+	signal jtag_ld_clk		: STD_LOGIC;
+	signal jtag_ld_we		: STD_LOGIC;
+	signal jtag_ld_addr		: inst_addr_t;
+	signal jtag_ld_dout		: inst_t;
+	signal jtag_ld_din		: inst_t;
+	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
+	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
+	signal user_regi, user_rego : unsigned (31 downto 0);
+	constant id : unsigned (31 downto 0) := X"BABE" & X"BEEF";
+
+begin
+
+--------------------------------------------------------------------------
+-- Virtex-4: JTAG Loader
+--------------------------------------------------------------------------
+	i00_BUFG : BUFG
+	port map
+	(
+		O => bs_clk1,
+        I => bs_clk0
+	);
+	
+	i01_BUFG : BUFG
+	port map
+	(
+		O => bs_update1,
+        I => bs_update0
+	);
+
+	BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 
+	generic map
+	(
+		JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
+	)
+	port map 
+	(
+		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
+		DRCK => bs_clk0,       -- Data register output for USER functions
+		RESET => bs_rst,       -- Reset output from TAP controller
+		SEL => bs_sel,         -- USER active output
+		SHIFT => bs_shift,     -- SHIFT output from TAP controller
+		TDI => bs_tdi,        -- TDI output from TAP controller
+		UPDATE => bs_update0,   -- UPDATE output from TAP controller
+		TDO => bs_tdo         -- Data input for USER function
+	);
+
+	jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-inst_addr_t'length+1);
+	jtag_ld_din <= user_regi(inst_t'length-1 downto 0);
+	jtag_ld_clk <= bs_update1;
+	jtag_ld_we <= bs_sel;
+	
+sipo:
+	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
+	begin
+		if bs_rst = '1' then
+			user_regi <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
+			end if;
+		end if;
+	end process;	
+
+piso:
+	process (bs_rst, bs_clk1, bs_shift, user_rego)
+	begin
+		bs_tdo <= user_rego(0);
+		if bs_rst = '1' then
+			user_rego <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
+			else
+				user_rego <= (user_rego'left downto inst_t'length => '0') & jtag_ld_dout;	
+--				user_rego <= id;	
+			end if;
+		end if;
+	end process;	
+	
+--------------------------------------------------------------------------
+-- ROM Read/Write
+--------------------------------------------------------------------------
+PROM_READ: 
+	process(clk, ce)
+	begin
+		if rising_edge(clk) and ce = '1' then
+			dout <= imem_rom(to_integer(addr));
+		end if;
+	end process;
+
+PROM_WRITE: 
+	process(jtag_ld_clk, jtag_ld_we)
+	begin
+		if rising_edge(jtag_ld_clk) then
+			if jtag_ld_we = '1' then
+				imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
+			else	
+				jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr));
+			end if;
+		end if;	
+	end process;
+
+--------------------------------------------------------------------------
+end loadable;

lib/CPUs/JCpu/tools/jasm.bak.rb

@@ -0,0 +1,494 @@
+#!/usr/bin/env ruby
+
+# ----------------------------------------------------------------------
+# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+# This file: A small assembler for the JCPU
+
+# Copyright (C) 2007 J. Ahrensfeld
+
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2.1 of the License, or (at your option) any later version.
+
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+# Lesser General Public License for more details.
+
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+# For questions and ideas, please contact the author at jens@jayfield.org
+
+# ---------------------------------------------------------------------
+
+arg = $*
+MAX_SIZE_ROM = 1024
+PROJECT_NAME = arg.to_s.gsub(/\..*/, "")
+ENTITY_NAME = "rom"
+ENTITY_DATA_TYPE = "inst_t"
+ENTITY_ADDR_TYPE = "inst_addr_t"
+OPC_LIST_NAME = "/cygdrive/w/vhdl/lib/CPUs/JCpu/tools/opc.list"
+
+# --------------------------------------------------------
+# Open file
+# --------------------------------------------------------
+filename = arg.to_s
+if !File.exists?(filename)
+	STDERR.puts "#{filename} does not exist"
+	exit 1
+end
+
+# --------------------------------------------------------
+# Pass 1
+# --------------------------------------------------------
+lc = 0	# Line counter
+pc = 0	# Program counter
+chip_dc = [0,0,0,0]	# chip data counter
+xmem_dc = 0	# xmem data counter
+curr_segment = "UNDEF";
+page = 0
+
+label_list=[[],[]]
+instr_list=[nil]
+file = File.open(filename, "r")
+file.each do |raw_line|
+	lc += 1
+
+	# Make all upper case
+	iline = "#{raw_line}".strip.upcase
+	
+	# Remove comments
+	iline = iline.gsub(/;.*/, "")
+	
+	# Split instruction at spaces
+	iline_member = iline.split(" ")
+
+	if iline_member[0] == nil
+		next
+	end	
+	
+	mc = 0;
+	label = nil
+	clean_line = nil
+	if (iline_member[0] =~ /\w+:/)
+		mc += 1
+		label = iline_member[0].delete(":")
+		if label_list.rindex(label) != nil
+			STDERR.puts format("Error in line %d: Duplicate label \"%s\" found", lc, label)
+			exit 1
+		end
+	end
+	
+	case iline_member[mc]
+	when nil
+		value = format("0x%3.3X",pc)
+	when "EQU"
+		if 0 == (iline_member[mc+1] =~ /\d+/)
+			value = format("0x%2.2X",eval(iline_member[mc+1..iline_member.nitems].to_s))
+		else 	
+			value = iline_member[mc+1]
+		end 	
+	when "ORG", "CODE"
+		pc = eval(iline_member[mc+1..iline_member.nitems].to_s)
+		value = format("0x%3.3X",pc)
+	when "CDATA", "CMEM"
+		if iline_member[mc+1] == nil
+			STDERR.puts format("Error in line %d: CDATA needs argument!", lc)
+			exit 1
+		end 	
+		curr_segment = "CMEM";
+		page = iline_member[mc+1].to_i(16)
+	when "XDATA", "XMEM"
+		curr_segment = "XMEM";
+	when "DC"
+		len = 0;
+		iline.split("DC")[1].delete("0x").scan(/[0-9A-Fa-f]+/).each do |byte| 
+			len += 1
+		end	
+		if curr_segment == "CMEM"
+			STDERR.puts format("Error in line %d: CDATA cannot be initialized!", lc)
+			exit 1
+		else
+			value = format("0x%2.2X",xmem_dc)
+			puts format("Found DC defining %d bytes at 0x%4.4X in %s", len, xmem_dc, curr_segment);
+			xmem_dc += len
+		end	
+	when "DB"
+		len = iline_member[mc+1].to_i
+		if curr_segment == "CMEM"
+			value = format("0x%2.2X",chip_dc[page])
+			puts format("Found DB reserving %d bytes at 0x%4.4X in %s(%d)", len, chip_dc[page], curr_segment, page);
+			chip_dc[page] += len
+		else
+			value = format("0x%2.2X",xmem_dc)
+			puts format("Found DB reserving %d bytes at 0x%4.4X in %s", len, xmem_dc, curr_segment);
+			xmem_dc += len
+		end	
+	else
+		op_line = iline_member[mc+1..iline_member.nitems].to_s
+		value = format("0x%3.3X",pc)
+		opc = iline_member[mc]
+		if iline_member[mc+1] != nil
+			op1 = op_line.gsub(/,+.*$/, "")
+		end	
+		if iline_member[mc+2] != nil
+			op2 = op_line.scan(/,.+$/).to_s.delete(", ")
+		end	
+		if instr_list[pc] == nil
+			instr_list[pc] = [lc, pc, opc , op1 , op2]
+			pc += 1
+		else
+			STDERR.puts format("Error in line %d: Overlapping sections at %3.3X", lc, pc)
+			exit 1
+		end
+	end;	
+
+	# Push labels
+	if label	
+		label_list = label_list + [label, value]
+	end
+end
+file.close
+
+# --------------------------------------------------------
+def instr(opcode)
+	return format("\"%6.6B\" & X\"%3.3X\"",opcode ,0)
+end	
+
+def tcl_bits(pc, opcode)
+	return format("%10.10B%6.6B%12.12B",pc, opcode ,0)
+end
+
+def instr_k(opcode, k)
+	return format("\"%6.6B\" & X\"%3.3X\"",opcode ,k)
+end	
+
+def tcl_bits_k(pc, opcode, k)
+	return format("%10.10B%6.6B%12.12B",pc, opcode ,k)
+end
+
+def instr_r(opcode, r)
+	return format("\"%6.6B\" & X\"%2.2X%X\"",opcode ,0, r)
+end	
+
+def tcl_bits_r(pc, opcode, r)
+	return format("%10.10B%6.6B%8.8B%4.4B",pc, opcode ,0,r)
+end
+
+def instr_kr(opcode, k, r)
+	return format("\"%6.6B\" & X\"%2.2X%X\"",opcode,k, r)
+end	
+
+def tcl_bits_kr(pc, opcode, k, r)
+	return format("%10.10B%6.6B%8.8B%4.4B",pc, opcode, k, r)
+end
+
+def instr_rk(opcode, r, k)
+	return format("\"%6.6B\" & X\"%2.2X%X\"",opcode,k, r)
+end	
+
+def tcl_bits_rk(pc, opcode, r, k)
+	return format("%10.10B%6.6B%8.8B%4.4B",pc, opcode, k, r)
+end
+
+def instr_rr(opcode, ra, rb)
+	return format("\"%6.6B\" & X\"%X%X%X\"",opcode,0, rb, ra)
+end	
+
+def tcl_bits_rr(pc, opcode, ra, rb)
+	return format("%10.10B%6.6B%4.4B%4.4B%4.4B",pc, opcode, 0, rb, ra)
+end
+
+# --------------------------------------------------------
+# Read mnemonic set
+# --------------------------------------------------------
+filename = OPC_LIST_NAME
+if !File.exists?(filename)
+	STDERR.puts "#{filename} does not exist"
+	exit 1
+end
+
+mnemo_list = []
+num_opcodes = 0
+file = File.open(filename, "r")
+file.each do |raw_line|
+	mnemo_list[num_opcodes] = raw_line.split(" ")[1]
+	num_opcodes += 1
+end
+
+# --------------------------------------------------------
+# Pass 2
+# --------------------------------------------------------
+pc = 0
+opc_start = 2
+num_errors = 0
+vhdl_trans_list = [nil]
+vhdl_comment_list = [nil]
+vhdl_tcl_list = [nil]
+instr_list.each do |instruct|
+		
+	# puts instruct
+	if instruct == nil
+		vhdl_trans_list[pc] = format("\"%6.6B\" & X\"%3.3X\"",0 ,0)
+		vhdl_comment_list[pc] = format("0x%3.3X:", pc)
+		vhdl_tcl_list[pc] = tcl_bits(pc, 0)
+		pc += 1
+		next
+	end
+		
+	# determine arglen of instruction
+	ilen = 0
+	if instruct[opc_start+1] == nil
+		arglen = 0
+	elsif instruct[opc_start+2] == nil
+		arglen = 1
+	elsif instruct[opc_start+3] == nil
+		arglen = 2
+	end	
+	
+	# Symbol substitution
+	error = false
+	for i in (1..3)
+		subst_pos = opc_start+i
+		if instruct[subst_pos] == nil
+			next
+		end	
+		expr_token = ""
+		expr_subst = nil
+		is_direct = true;
+		
+#		instruct[subst_pos] = instruct[subst_pos].delete(" ")
+
+		# checks R0 .. R16, Mnemonics
+		instr_str = instruct[subst_pos]
+		if 0 == (instr_str =~ /\(.+\)/)
+			instr_str = instr_str.delete("()")
+			is_direct = false;
+		end	
+
+		expr_token = instr_str.split(/\+|\-|\*|\//)[0]
+		if (0 != (expr_token =~ /R[0-9]+/)) && (0 != (expr_token =~ /\d+/))
+			idx = label_list.rindex(expr_token)
+			if idx != nil
+				expr_subst = label_list[idx+1]
+				instruct[subst_pos] = instruct[subst_pos].gsub(expr_token, expr_subst)
+			else
+				STDERR.puts format("Error in line %d: Symbol \"%s\" not found", instruct[0], expr_token)
+				error = true
+			end
+		end	
+		
+		if expr_subst != nil
+			if 0 == (expr_subst =~ /\d+/) 
+				if is_direct == true
+					instruct[subst_pos] = format("0x%2.2X", eval(instruct[subst_pos]))
+				else
+					instruct[subst_pos] = format("(0x%2.2X)", eval(instruct[subst_pos]))
+				end	
+			else
+				if 0 != (expr_subst =~ /R[0-9]+/)
+					STDERR.puts format("Error in line %d: Invalid expression \"%s\"", instruct[0], expr_subst)
+					error = true
+				end
+			end
+		end	
+	end
+	
+	# Parse operands
+	reg = [0,0]
+	kk = 0
+	format = instruct[opc_start]
+	for i in (0..1)
+		if instruct[opc_start+i+1] =~ Regexp.new("R[0-9]+")
+			# Check indirect addressing
+			reg[i] = instruct[opc_start+i+1].delete("R()").to_i
+			format += "|R"
+			if reg[i] > 15
+				STDERR.puts format("Error in line %d: Invalid register \"R%d\" specified", instruct[0], reg[i])
+				error = true
+			end
+		else
+			if instruct[opc_start+i+1] =~ Regexp.new("[0-9A-F]+")
+				kk = instruct[opc_start+i+1].delete("()").to_i(16)
+				format += "|K"
+			end
+		end
+		if instruct[opc_start+i+1] =~ Regexp.new("\\(.+\\)")
+			format += "i";
+		end
+	end 
+	
+	# Output instruction
+	opcode = mnemo_list.rindex(format).to_i
+	mnemo = instruct[2];
+
+	case format
+	when "NOP", "HALT", "RET", "RETI"
+		vhdl_trans_list[pc] = instr(opcode)
+		vhdl_tcl_list[pc] = tcl_bits(pc, opcode)
+		minstr_comment = format("0x%3.3X: %s", pc, mnemo)
+	when "MOVC|R|Ri", "MOVX|R|Ri"
+		vhdl_trans_list[pc] = instr_rr(opcode, reg[0], reg[1]);
+		vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[0], reg[1])
+		minstr_comment = format("0x%3.3X: %s R%2.2d, (R%2.2d)", pc, mnemo, reg[0], reg[1])
+	when "MOV|R|R", "SUB|R|R", "ADD|R|R", "AND|R|R", "OR|R|R", "XOR|R|R", "CMP|R|R"
+		vhdl_trans_list[pc] = instr_rr(opcode, reg[0], reg[1]);
+		vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[0], reg[1])
+		minstr_comment = format("0x%3.3X: %s R%2.2d, R%2.2d", pc, mnemo, reg[0], reg[1])
+	when "MOVC|Ri|R", "MOVX|Ri|R"
+		vhdl_trans_list[pc] = instr_rr(opcode, reg[1], reg[0]);
+		vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[1], reg[0])
+		minstr_comment = format("0x%3.3X: %s (R%2.2d), R%2.2d", pc, mnemo, reg[1], reg[0])
+	when "MOVC|Ri|K", "MOVX|Ri|K", "COUT|Ri|K", "XOUT|Ri|K"
+		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
+		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
+		minstr_comment = format("0x%3.3X: %s (R%2.2d), 0x%2.2X", pc, mnemo, reg[0], kk)
+	when "MOVC|R|Ki", "MOVX|R|Ki", "CIN|R|Ki", "XIN|R|Ki"
+		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
+		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
+		minstr_comment = format("0x%3.3X: %s R%2.2d, (0x%2.2X)", pc, mnemo, reg[0], kk)
+	when "MOV|R|K", "SUB|R|K", "ADD|R|K", "AND|R|K", "OR|R|K", "XOR|R|K", "CMP|R|K"
+		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
+		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
+		minstr_comment = format("0x%3.3X: %s R%2.2d, 0x%2.2X", pc, mnemo, reg[0], kk)
+	when "MOVC|Ki|R", "MOVC|Ki|R", "MOVX|Ki|R", "MOVX|Ki|R", "COUT|Ki|R", "XOUT|Ki|R"
+		vhdl_trans_list[pc] = instr_kr(opcode, kk, reg[1]);
+		vhdl_tcl_list[pc] = tcl_bits_kr(pc, opcode, kk, reg[1])
+		minstr_comment = format("0x%3.3X: %s (0x%2.2X), R%2.2d", pc, mnemo, kk, reg[1])
+	when "CALL|K", "JMP|K", "JNZ|K", "JZ|K","JNC|K", "JC|K", "JLT|K", "JGT|K", "JLE|K", "JGE|K", "JEQ|K", "JNE|K"
+		vhdl_trans_list[pc] = instr_k(opcode, kk)
+		vhdl_tcl_list[pc] = tcl_bits_k(pc, opcode, kk)
+		minstr_comment = format("0x%3.3X: %s 0x%3.3X", pc, mnemo, kk)
+	when "PUSH|R", "POP|R", "SHR|R", "SHL|R", "ROR|R", "ROL|R", "RORC|R", "ROLC|R"
+		vhdl_trans_list[pc] = instr_r(opcode, reg[0])
+		vhdl_tcl_list[pc] = tcl_bits_r(pc, opcode, reg[0])
+		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
+	when "TST|R"
+		kk = 0
+		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
+		opcode = mnemo_list.rindex("CMP|R|K").to_i
+		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
+		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
+	when "INC|R"
+		kk = 1
+		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
+		opcode = mnemo_list.rindex("ADD|R|K").to_i
+		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
+		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
+	when "DEC|R"
+		kk = 1
+		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
+		opcode = mnemo_list.rindex("SUB|R|K").to_i
+		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
+		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
+	else
+		STDERR.puts format("Error in line %d: Not yet implemented %s", instruct[0], format)
+		error = true
+	end
+
+	if error
+		num_errors += 1
+		break
+	end
+	vhdl_comment_list[pc] = minstr_comment
+
+	puts vhdl_trans_list[pc] + " -- " + minstr_comment
+	
+	pc += 1
+end
+
+# --------------------------------------------------------
+# Output ROM file
+# --------------------------------------------------------
+if num_errors == 0
+
+	filename = format("rom_%s.vhdl.snip", PROJECT_NAME)
+	file = File.open(filename, "w")
+
+	file.puts format("ENTITY %s IS\n", ENTITY_NAME)
+	file.puts format("\tPort (\n")
+	file.puts format("\tclk\t\t\t: in  STD_LOGIC;\n")
+	file.puts format("\tce\t\t\t: in  STD_LOGIC;\n")
+	file.puts format("\taddr\t\t: in  %s;\n", ENTITY_ADDR_TYPE)
+	file.puts format("\tdout\t\t: out %s\n", ENTITY_DATA_TYPE)
+	file.puts format("\t);\n")
+	file.puts format("END %s;\n", ENTITY_NAME)
+	file.puts format("\n")
+	file.puts format("ARCHITECTURE %s OF %s IS \n", PROJECT_NAME, ENTITY_NAME)
+	file.puts format("\n")
+	file.puts format("\ttype instruction_rom_t is array (0 to %d) of %s;\n", pc-1, ENTITY_DATA_TYPE)
+	file.puts format("\n")
+	file.puts format("\tconstant instruction_rom : instruction_rom_t :=\n")
+	file.puts format("\t(\n");
+	for i in (0..pc-2)
+		file.puts "\t\t" + vhdl_trans_list[i] + ", -- " + vhdl_comment_list[i] + "\n"
+	end;
+	file.puts "\t\t" + vhdl_trans_list[pc-1] + " -- " + vhdl_comment_list[pc-1] + "\n"
+	file.puts format("\t);\n")
+	file.puts format("\n")
+	file.puts format("begin")
+	file.puts format("\n")
+	file.puts format("PROM_READ:")
+	file.puts format("\tprocess(clk, ce)\n")
+	file.puts format("\tbegin\n")
+	file.puts format("\t\tif rising_edge(clk) and ce = '1' then\n")
+	file.puts format("\t\t\tdout <= instruction_rom(to_integer(addr));\n")
+	file.puts format("\t\tend if;\n")
+	file.puts format("\tend process;\n")
+	file.puts format("\n")
+	file.puts format("end %s;\n", PROJECT_NAME)
+	puts format("ROM file written to \"%s\"\n",filename)
+	file.close
+end
+if num_errors == 0
+
+	filename = format("preinit_%s.vhdl.snip", PROJECT_NAME)
+	file = File.open(filename, "w")
+
+	file.puts format("\tsignal instruction_rom : instruction_rom_t :=\n")
+	file.puts format("\t(\n");
+	for i in (0..pc-2)
+		file.puts "\t\t" + vhdl_trans_list[i] + ", -- " + vhdl_comment_list[i] + "\n"
+	end;
+	if pc < (MAX_SIZE_ROM-1)
+		file.puts "\t\t" + vhdl_trans_list[pc-1] + ", -- " + vhdl_comment_list[pc-1] + "\n"
+		for i in (pc..(MAX_SIZE_ROM-2))
+			file.puts "\t\t" + instr(0) + ",\n"
+		end;
+		file.puts "\t\t" + instr(0) + "\n"
+	else
+		file.puts "\t\t" + vhdl_trans_list[pc-1] + " -- " + vhdl_comment_list[pc-1] + "\n"
+	end	
+	file.puts format("\t);\n")
+	puts format("PREINIT file written to \"%s\"\n",filename)
+	file.close
+end
+if num_errors == 0
+	filename = format("rom_%s.tcl.snip", PROJECT_NAME)
+	file = File.open(filename, "w")
+	for i in (0..pc-1)
+		# Chipscope 8.1
+#		file.puts format("jtag_shiftdr $handle -buffer \"%s\" -endstate RTI -device $devid", vhdl_tcl_list[i].reverse);
+
+		# Chipscope 9.1
+		file.puts format("\# %s", vhdl_comment_list[i]) 
+		file.puts format("::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 %d \"%8.8X\"\n\n", vhdl_tcl_list[i].length, vhdl_tcl_list[i].to_i(2));
+	end;
+	puts format("TCL snippet written to \"%s\"\n",filename)
+	file.close
+end
+
+# --------------------------------------------------------
+# Output final statistics
+# --------------------------------------------------------
+if num_errors == 0
+	puts "Program uses #{pc} instruction addresses"
+	puts "No errors found"
+	exit 0
+else
+	puts "#{num_errors} errors found"
+	exit 1
+end	

lib/CPUs/JCpu/tools/jasm.rb

@@ -0,0 +1,814 @@
+#!/usr/bin/env ruby
+
+# ----------------------------------------------------------------------
+# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+# This file: A small assembler for the JCPU
+#
+# Copyright (C) 2007 J. Ahrensfeld
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+# 
+# For questions and ideas, please contact the author at jens@jayfield.org
+#
+# ---------------------------------------------------------------------
+
+arg = $*
+FILE_SUFFIX = "jsm"
+IROM_MAX_SIZE = 1024
+IROM_ENTITY_NAME = "irom"
+IROM_DATA_TYPE = "inst_t"
+IROM_ADDR_TYPE = "inst_addr_t"
+XROM_MAX_SIZE = 256
+XROM_DATA_TYPE = "dmem_data_t"
+XROM_ADDR_TYPE = "dmem_addr_t"
+XROM_ENTITY_NAME = "xrom"
+OPC_LIST_NAME = "/cygdrive/w/vhdl/lib/CPUs/JCpu/tools/opc.list"
+
+# --------------------------------------------------------
+class Parser
+	def curr_segment
+		@curr_segment
+	end	
+	def curr_segment=(arg)
+		@curr_segment=arg
+	end	
+	def add_label(labelname, addr)
+		@label_list = @label_list + [labelname, addr]
+	end
+	def	getLabelIdByName(label)
+		return @label_list.rindex(label)
+	end
+	def	getLabelNameById(id)
+		return @label_list[id]
+	end
+	def put_instr(name, lc, opc , op1 , op2)
+		if get_instr != nil
+			STDERR.puts format("Error in line %d: Overlapping sections at %3.3X", lc, @pc)
+			exit 1
+		end
+		@instr_list[@pc] = [lc, @pc, opc , op1 , op2, name]
+	end
+	def	get_instr
+		return @instr_list[@pc]
+	end
+	def put_xmem(value, lc)
+		if get_xmem != nil
+			STDERR.puts format("Error in line %d: Overlapping sections at %3.3X (%s)", lc, xmem_dc, curr_segment)
+			exit 1
+		end
+		@xmem[xmem_dc] = value
+		@xmem_dc = xmem_dc + 1
+	end	
+	def get_xmem
+		return @xmem[xmem_dc]
+	end	
+	def xmem
+		return @xmem
+	end	
+	def put_cmem(value, lc)
+		if get_cmem(page) != nil
+			STDERR.puts format("Error in line %d: Overlapping sections at %3.3X (%s)", lc, cmem_dc, curr_segment)
+			exit 1
+		end
+		@cmem[page][cmem_dc] = value
+		@cmem_dc[page] = cmem_dc + 1
+	end	
+	def get_cmem(pg)
+		return @cmem[pg][cmem_dc]
+	end	
+	def cmem(page)
+		return @cmem[page]
+	end	
+	def	cmem_dc=(addr)
+		@cmem_dc[page] = addr
+	end	
+	def	cmem_dc
+		@cmem_dc[page]
+	end	
+	def	xmem_dc=(addr)
+		@xmem_dc = addr
+	end	
+	def	xmem_dc
+		@xmem_dc
+	end	
+	def page=(page)
+		@page = page;
+	end	
+	def page
+		@page;
+	end	
+	def pc=(pc)
+		@pc = pc;
+		if (pc > @pc_max)
+			@pc_max = pc
+		end	
+	end	
+	def pc
+		@pc;
+	end	
+	def pc_max
+		@pc_max;
+	end	
+	def	instr_list
+		@instr_list
+	end
+	def	label_list
+		@label_list
+	end
+	
+	def initialize()
+		@pc_max = 0
+		@pc = 0					# Program counter
+		@cmem_dc = [0,0,0,0]	# chip data counter
+		@xmem_dc = 0			# xmem data counter
+		@curr_segment = "UNDEF";
+		@page = 0
+		@label_list=[[],[]]
+		@instr_list=[nil]
+		@cmem = [[],[]];
+		@xmem = [];
+	end
+	def method_missing(name, *args)
+		puts "I don't know the method #{name}"
+	end
+end	
+
+# --------------------------------------------------------
+def parse(name, obj)
+
+lc = 0	# Line counter
+file = File.open(name, "r")
+
+file.each do |raw_line|
+	lc += 1
+
+	# Make all upper case
+	iline = "#{raw_line}".strip
+	
+	# Remove comments
+	iline = iline.gsub(/;.*/, "")
+	
+	# Split instruction at spaces
+	iline_member = iline.split(" ")
+
+	if iline_member[0] == nil
+		next
+	end	
+	
+	mc = 0;
+	label = nil
+	clean_line = nil
+	if (iline_member[0] =~ /\w+:/)
+		mc += 1
+		label = iline_member[0].delete(":")
+		if obj.getLabelIdByName(label) != nil
+			STDERR.puts format("Error in line %d: Duplicate label \"%s\" found", lc, label)
+			exit 1
+		end
+	end
+	
+	token = iline_member[mc]
+	if token
+		token = token.upcase
+	end
+	
+	case token
+	when nil
+		if obj.curr_segment == "CMEM"
+			curr_addr = format("0x%3.3X",obj.cmem_dc)
+		elsif obj.curr_segment == "XMEM"
+			curr_addr = format("0x%3.3X",obj.xmem_dc)
+		elsif obj.curr_segment == "CODE"
+			curr_addr = format("0x%3.3X",obj.pc)
+		else
+			STDERR.puts format("Error in line %d: Undefined segment", lc)
+			exit 1
+		end
+	when "INCLUDE"
+		if iline_member[mc+1] == nil
+			STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
+			exit 1
+		end 	
+		inc_name = iline_member[mc+1].delete("\"")
+		puts format("Inserting \"%s\" into \"%s\" at line %d", inc_name, name, lc);
+		parse(inc_name, obj)
+	when "EQU"
+		if iline_member[mc+1] == nil
+			STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
+			exit 1
+		end 	
+		if 0 == (iline_member[mc+1] =~ /\d+/)
+			curr_addr = format("0x%2.2X",eval(iline_member[mc+1..iline_member.nitems].to_s))
+		else 	
+			curr_addr = iline_member[mc+1]
+		end 	
+	when "ORG"
+		if iline_member[mc+1] == nil
+			STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
+			exit 1
+		end 	
+		offset = eval(iline_member[mc+1..iline_member.nitems].to_s)
+		case obj.curr_segment
+			when "CODE"
+			obj.pc = offset
+			curr_addr = format("0x%3.3X",obj.pc)
+			when "CMEM"
+			obj.cmem_dc = offset
+			when "XMEM"
+			obj.xmem_dc = offset
+			
+		end	
+	when "CODE"
+		curr_addr = format("0x%3.3X",obj.pc)
+		obj.curr_segment = "CODE";
+	when "CDATA", "CMEM"
+		if iline_member[mc+1] == nil
+			STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
+			exit 1
+		end 	
+		obj.curr_segment = "CMEM";
+		obj.page = iline_member[mc+1].to_i(16)
+	when "XDATA", "XMEM"
+		obj.curr_segment = "XMEM";
+	when "DC"
+		len = 0;
+		if iline_member[mc+1] == nil
+			STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
+			exit 1
+		end 	
+		if obj.curr_segment == "CMEM"
+			STDERR.puts format("Error in line %d: %s cannot be initialized!", lc, obj.curr_segment)
+			exit 1
+		elsif obj.curr_segment == "XMEM"
+			curr_addr = format("0x%2.2X",obj.xmem_dc)
+			dc_old = obj.xmem_dc;
+			val_array = raw_line.split(/dc|DC|Dc|dC/)[1].delete("\t").gsub(/;.*/, "").split(",")
+			
+			# Parse string literals
+			val_array.each do |item| 
+				if 0 == (item =~ /.*\".*\"/)
+					str = item.delete("\"")
+					puts item
+					for nn in (0..str.length-1)
+						if str[nn] > 31
+							obj.put_xmem(str[nn], lc);
+						 	puts "S: " + str[nn].to_s
+							len += 1
+						end	
+					end;
+				else
+					argument = item
+					puts "B: " + argument
+					obj.put_xmem(eval(argument), lc);
+					len += 1
+				end	
+			end	
+			puts format("Found DC defining %d bytes at 0x%4.4X in %s", len, dc_old, obj.curr_segment);
+		else	
+			STDERR.puts format("Error in line %d: Invalid segment %s for \"%s\"", lc, obj.curr_segment, token)
+			exit 1
+		end	
+	when "DB"
+		if iline_member[mc+1] == nil
+			STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
+			exit 1
+		end 	
+		len = eval(iline_member[mc+1]).to_i
+		if obj.curr_segment == "CMEM"
+			curr_addr = format("0x%2.2X",obj.cmem_dc)
+			puts format("Found DB reserving %d bytes at 0x%4.4X in %s(%d)", len, obj.cmem_dc, obj.curr_segment, obj.page);
+			for nn in (1..len)
+				obj.put_cmem(0, lc)
+			end	
+		elsif obj.curr_segment == "XMEM"
+			curr_addr = format("0x%2.2X",obj.xmem_dc)
+			puts format("Found DB reserving %d bytes at 0x%4.4X in %s", len, obj.xmem_dc, obj.curr_segment);
+			for nn in (1..len)
+				obj.put_xmem(0, lc)
+			end	
+		else	
+			STDERR.puts format("Error in line %d: Invalid segment %s for \"%s\"", lc, obj.curr_segment, token)
+			exit 1
+		end	
+	else
+		if obj.curr_segment != "CODE"
+			STDERR.puts format("Error in line %d: Invalid segment %s for \"%s\"", lc, obj.curr_segment, token)
+			exit 1
+		end			
+
+		op_line = iline_member[mc+1..iline_member.nitems].to_s
+		curr_addr = format("0x%3.3X",obj.pc)
+		opc = token
+		if iline_member[mc+1] != nil
+			op1 = op_line.gsub(/,+.*$/, "")
+		end	
+		if iline_member[mc+2] != nil
+			op2 = op_line.scan(/,.+$/).to_s.delete(", ")
+		end	
+		obj.put_instr(name, lc, opc, op1, op2)
+		obj.pc = obj.pc + 1
+	end;	
+
+	# Push labels
+	if label	
+		obj.add_label(label, curr_addr)
+	end
+end
+file.close
+return obj
+end
+
+# --------------------------------------------------------
+# Instruction formatting
+# --------------------------------------------------------
+def instr(opcode)
+	return format("\"%6.6B\" & X\"%3.3X\"",opcode ,0)
+end	
+
+def tcl_bits(pc, opcode)
+	return format("%12.12B%8.8B%12.12B",pc, opcode ,0)
+end
+
+def instr_k(opcode, k)
+	return format("\"%6.6B\" & X\"%3.3X\"",opcode ,k)
+end	
+
+def tcl_bits_k(pc, opcode, k)
+	return format("%12.12B%8.8B%12.12B",pc, opcode ,k)
+end
+
+def instr_r(opcode, r)
+	return format("\"%6.6B\" & X\"%2.2X%X\"",opcode ,0, r)
+end	
+
+def tcl_bits_r(pc, opcode, r)
+	return format("%12.12B%8.8B%8.8B%4.4B",pc, opcode ,0,r)
+end
+
+def instr_kr(opcode, k, r)
+	return format("\"%6.6B\" & X\"%2.2X%X\"",opcode,k, r)
+end	
+
+def tcl_bits_kr(pc, opcode, k, r)
+	return format("%12.12B%8.8B%8.8B%4.4B",pc, opcode, k, r)
+end
+
+def instr_rk(opcode, r, k)
+	return format("\"%6.6B\" & X\"%2.2X%X\"",opcode,k, r)
+end	
+
+def tcl_bits_rk(pc, opcode, r, k)
+	return format("%12.12B%8.8B%8.8B%4.4B",pc, opcode, k, r)
+end
+
+def instr_rr(opcode, ra, rb)
+	return format("\"%6.6B\" & X\"%X%X%X\"",opcode,0, rb, ra)
+end	
+
+def tcl_bits_rr(pc, opcode, ra, rb)
+	return format("%12.12B%8.8B%4.4B%4.4B%4.4B",pc, opcode, 0, rb, ra)
+end
+
+# --------------------------------------------------------
+# Open file
+# --------------------------------------------------------
+filename = arg.to_s
+if !File.exists?(filename)
+	STDERR.puts "#{filename} does not exist"
+	exit 1
+end
+PROJECT_NAME = File.basename(filename, "." + FILE_SUFFIX)
+
+# --------------------------------------------------------
+# Pass 1
+# --------------------------------------------------------
+first_pass = Parser.new();
+parse(filename, first_pass)
+
+# --------------------------------------------------------
+# Read mnemonic set
+# --------------------------------------------------------
+filename = OPC_LIST_NAME
+if !File.exists?(filename)
+	STDERR.puts "#{filename} does not exist"
+	exit 1
+end
+
+mnemo_list = []
+num_opcodes = 0
+file = File.open(filename, "r")
+file.each do |raw_line|
+	mnemo_list[num_opcodes] = raw_line.split(" ")[1]
+	num_opcodes += 1
+end
+
+# --------------------------------------------------------
+# Pass 2
+# --------------------------------------------------------
+pc = 0
+opc_start = 2
+num_errors = 0
+vhdl_trans_list = [nil]
+vhdl_comment_list = [nil]
+vhdl_tcl_list = [nil]
+
+# ToDo: Use class-methods
+label_list = first_pass.label_list
+instr_list = first_pass.instr_list
+
+instr_list.each do |instruct|
+		
+	# puts instruct
+	if instruct == nil
+		vhdl_trans_list[pc] = format("\"%6.6B\" & X\"%3.3X\"",0 ,0)
+		vhdl_comment_list[pc] = format("0x%3.3X:", pc)
+		vhdl_tcl_list[pc] = tcl_bits(pc, 0)
+		pc += 1
+		next
+	end
+		
+	# determine arglen of instruction
+	ilen = 0
+	if instruct[opc_start+1] == nil
+		arglen = 0
+	elsif instruct[opc_start+2] == nil
+		arglen = 1
+	elsif instruct[opc_start+3] == nil
+		arglen = 2
+	end	
+	
+	# Symbol substitution
+	error = false
+	for i in (1..2)
+		subst_pos = opc_start+i
+		if instruct[subst_pos] == nil
+			next
+		end	
+		expr_token = ""
+		expr_subst = nil
+		is_direct = true;
+		
+		# checks R0 .. R16, Mnemonics
+		instruct[subst_pos] = instruct[subst_pos].gsub(/'low/, "")
+		if (nil != (instruct[subst_pos] =~ /'high/))
+			instruct[subst_pos]= format("%s/256", instruct[subst_pos].gsub(/'high/, ""))
+		end	
+		instr_str = instruct[subst_pos]
+		if 0 == (instr_str =~ /\(.+\)/)
+			instr_str = instr_str.delete("()")
+			is_direct = false;
+		end	
+
+		expr_token = instr_str.split(/\+|\-|\*|\/|\||\&/)[0]
+		if (0 != (expr_token =~ /R[0-9]+/)) && (0 != (expr_token =~ /\d+/))
+			idx = label_list.rindex(expr_token)
+			if idx != nil
+				expr_subst = label_list[idx+1]
+				instruct[subst_pos] = instruct[subst_pos].gsub(expr_token, expr_subst)
+			else
+				STDERR.puts format("%s: Error in line %d: Symbol \"%s\" not found", instruct[5], instruct[0], expr_token)
+				error = true
+			end
+		end	
+		
+		if expr_subst != nil
+			if 0 == (expr_subst =~ /\d+/) 
+				if is_direct == true
+					instruct[subst_pos] = format("0x%2.2X", eval(instruct[subst_pos]))
+				else
+					instruct[subst_pos] = format("(0x%2.2X)", eval(instruct[subst_pos]))
+				end	
+			else
+				if 0 != (expr_subst =~ /R[0-9]+/)
+					STDERR.puts format("%s: Error in line %d: Invalid expression \"%s\"", instruct[5], instruct[0], expr_subst)
+					error = true
+				end
+			end
+		end	
+	end
+	
+	# Parse operands
+	reg = [0,0]
+	kk = 0
+	format = instruct[opc_start]
+	for i in (0..1)
+		if instruct[opc_start+i+1] =~ Regexp.new("R[0-9]+")
+			# Check indirect addressing
+			reg[i] = instruct[opc_start+i+1].delete("R()").to_i
+			format += "|R"
+			if reg[i] > 15
+				STDERR.puts format("%s: Error in line %d: Invalid register \"R%d\" specified", instruct[5], instruct[0], reg[i])
+				error = true
+			end
+		else
+			if instruct[opc_start+i+1] =~ Regexp.new("[0-9A-F]+")
+				kk = eval(instruct[opc_start+i+1].delete("()"))
+				format += "|K"
+			end
+		end
+		if instruct[opc_start+i+1] =~ Regexp.new("\\(.+\\)")
+			format += "i";
+		end
+	end 
+	
+	if error
+		num_errors += 1
+		break
+	end
+
+	# Output instruction
+	opcode = mnemo_list.rindex(format).to_i
+	mnemo = instruct[2];
+
+	case format
+	# Native instructions
+	when "NOP", "HALT", "RET", "RETI", "SETC"
+		vhdl_trans_list[pc] = instr(opcode)
+		vhdl_tcl_list[pc] = tcl_bits(pc, opcode)
+		minstr_comment = format("0x%3.3X: %s", pc, mnemo)
+	when "MOVC|R|Ri", "MOVX|R|Ri"
+		vhdl_trans_list[pc] = instr_rr(opcode, reg[0], reg[1]);
+		vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[0], reg[1])
+		minstr_comment = format("0x%3.3X: %s R%2.2d, (R%2.2d)", pc, mnemo, reg[0], reg[1])
+	when "MOV|R|R", "SUB|R|R", "SUBC|R|R", "ADD|R|R", "ADDC|R|R", "AND|R|R", "OR|R|R", "XOR|R|R", "CMP|R|R"
+		vhdl_trans_list[pc] = instr_rr(opcode, reg[0], reg[1]);
+		vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[0], reg[1])
+		minstr_comment = format("0x%3.3X: %s R%2.2d, R%2.2d", pc, mnemo, reg[0], reg[1])
+	when "MOVC|Ri|R", "MOVX|Ri|R"
+		vhdl_trans_list[pc] = instr_rr(opcode, reg[1], reg[0]);
+		vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[1], reg[0])
+		minstr_comment = format("0x%3.3X: %s (R%2.2d), R%2.2d", pc, mnemo, reg[1], reg[0])
+	when "MOVC|Ri|K", "MOVX|Ri|K", "COUT|Ri|K", "XOUT|Ri|K"
+		kk = kk % 256;
+		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
+		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
+		minstr_comment = format("0x%3.3X: %s (R%2.2d), 0x%2.2X", pc, mnemo, reg[0], kk)
+	when "MOVC|R|Ki", "MOVX|R|Ki", "CIN|R|Ki", "XIN|R|Ki"
+		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
+		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
+		minstr_comment = format("0x%3.3X: %s R%2.2d, (0x%2.2X)", pc, mnemo, reg[0], kk)
+	when "MOV|R|K", "SUB|R|K", "SUBC|R|K", "ADD|R|K", "ADDC|R|K", "AND|R|K", "OR|R|K", "XOR|R|K", "CMP|R|K"
+		kk = kk % 256;
+		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
+		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
+		minstr_comment = format("0x%3.3X: %s R%2.2d, 0x%2.2X", pc, mnemo, reg[0], kk)
+	when "SUB|K|R", "SUBC|K|R"
+		kk = kk % 256;
+		vhdl_trans_list[pc] = instr_kr(opcode, kk, reg[1]);
+		vhdl_tcl_list[pc] = tcl_bits_kr(pc, opcode, kk, reg[1])
+		minstr_comment = format("0x%3.3X: %s 0x%2.2d, R%2.2X", pc, mnemo, kk, reg[1])
+	when "MOVC|Ki|R", "MOVC|Ki|R", "MOVX|Ki|R", "MOVX|Ki|R", "COUT|Ki|R", "XOUT|Ki|R"
+		vhdl_trans_list[pc] = instr_kr(opcode, kk, reg[1]);
+		vhdl_tcl_list[pc] = tcl_bits_kr(pc, opcode, kk, reg[1])
+		minstr_comment = format("0x%3.3X: %s (0x%2.2X), R%2.2d", pc, mnemo, kk, reg[1])
+	when "CALL|K", "JMP|K", "JNZ|K", "JZ|K","JNC|K", "JC|K", "JLT|K", "JGT|K", "JLE|K", "JGE|K", "JEQ|K", "JNE|K"
+		vhdl_trans_list[pc] = instr_k(opcode, kk)
+		vhdl_tcl_list[pc] = tcl_bits_k(pc, opcode, kk)
+		minstr_comment = format("0x%3.3X: %s 0x%3.3X", pc, mnemo, kk)
+	when "PUSH|R", "POP|R", "SHR|R", "SHL|R", "ROR|R", "ROL|R", "RORC|R", "ROLC|R", "SWAP|R"
+		vhdl_trans_list[pc] = instr_r(opcode, reg[0])
+		vhdl_tcl_list[pc] = tcl_bits_r(pc, opcode, reg[0])
+		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
+	# Synthetic instructions
+	when "CLRC"
+		kk = 0;
+		minstr_comment = format("0x%3.3X: %s", pc, mnemo)
+		opcode = mnemo_list.rindex("SUB|R|K").to_i
+		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
+		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
+	when "TST|R"
+		kk = 0
+		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
+		opcode = mnemo_list.rindex("CMP|R|K").to_i
+		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
+		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
+	when "NEG|R"
+		kk = 0
+		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
+		opcode = mnemo_list.rindex("SUB|K|R").to_i
+		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
+		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
+	when "NOT|R"
+		kk = 0
+		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
+		opcode = mnemo_list.rindex("XOR|R|K").to_i
+		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
+		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
+	when "INC|R"
+		kk = 1
+		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
+		opcode = mnemo_list.rindex("ADD|R|K").to_i
+		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
+		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
+	when "DEC|R"
+		kk = 1
+		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
+		opcode = mnemo_list.rindex("SUB|R|K").to_i
+		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
+		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
+	else
+		STDERR.puts format("%s: Error in line %d: Not yet implemented %s", instruct[5], instruct[0], format)
+		error = true
+	end
+
+	if error
+		num_errors += 1
+		break
+	end
+
+	vhdl_comment_list[pc] = minstr_comment
+
+	puts vhdl_trans_list[pc] + " -- " + minstr_comment
+	
+	pc += 1
+end
+
+# --------------------------------------------------------
+# Output ROM file
+# --------------------------------------------------------
+if num_errors == 0
+
+	# I-ROM VHDL-ROM
+	filename = format("%s.irom.vhdl.snip", PROJECT_NAME)
+	file = File.open(filename, "w")
+
+	file.puts format("ENTITY %s IS\n", IROM_ENTITY_NAME)
+	file.puts format("\tPort (\n")
+	file.puts format("\tclk\t\t\t: in  STD_LOGIC;\n")
+	file.puts format("\tce\t\t\t: in  STD_LOGIC;\n")
+	file.puts format("\taddr\t\t: in  %s;\n", IROM_ADDR_TYPE)
+	file.puts format("\tdout\t\t: out %s\n", IROM_DATA_TYPE)
+	file.puts format("\t);\n")
+	file.puts format("END %s;\n", IROM_ENTITY_NAME)
+	file.puts format("\n")
+	file.puts format("ARCHITECTURE %s OF %s IS \n", PROJECT_NAME, IROM_ENTITY_NAME)
+	file.puts format("\n")
+	file.puts format("\ttype imem_rom_t is array (0 to %d) of %s;\n", [IROM_MAX_SIZE, pc].min-1 , IROM_DATA_TYPE)
+	file.puts format("\n")
+	file.puts format("\t-- Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
+	file.puts format("\tconstant imem_rom : imem_rom_t :=\n")
+	file.puts format("\t(\n");
+	for i in (0..[IROM_MAX_SIZE, pc].min-2)
+		file.puts "\t\t" + vhdl_trans_list[i] + ", -- " + vhdl_comment_list[i] + "\n"
+	end;
+	file.puts "\t\t" + vhdl_trans_list[pc-1] + "  -- " + vhdl_comment_list[pc-1] + "\n"
+	file.puts format("\t);\n")
+	file.puts format("\n")
+	file.puts format("begin")
+	file.puts format("\n")
+	file.puts format("PROM_READ:")
+	file.puts format("\tprocess(clk, ce)\n")
+	file.puts format("\tbegin\n")
+	file.puts format("\t\tif rising_edge(clk) and ce = '1' then\n")
+	file.puts format("\t\t\tdout <= imem_rom(to_integer(addr));\n")
+	file.puts format("\t\tend if;\n")
+	file.puts format("\tend process;\n")
+	file.puts format("\n")
+	file.puts format("end %s;\n", PROJECT_NAME)
+	puts format("I-ROM file written to \"%s\"\n",filename)
+	file.close
+
+	# I-ROM VHDL-ROM (loadable)
+	filename = format("%s.irom_ld.vhdl.snip", PROJECT_NAME)
+	file = File.open(filename, "w")
+
+	file.puts format("\n\t-- Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
+	file.puts format("\ttype imem_rom_t is array (0 to %d) of %s;\n", IROM_MAX_SIZE-1, IROM_DATA_TYPE)
+	file.puts format("\tsignal imem_rom : imem_rom_t :=\n")
+	file.puts format("\t(\n");
+	for i in (0..pc-2)
+		file.puts "\t\t" + vhdl_trans_list[i] + ", -- " + vhdl_comment_list[i] + "\n"
+	end;
+	if pc < (IROM_MAX_SIZE-1)
+		file.puts "\t\t" + vhdl_trans_list[pc-1] + ", -- " + vhdl_comment_list[pc-1] + "\n"
+		for i in (pc..(IROM_MAX_SIZE-2))
+			file.puts "\t\t" + instr(0) + ",\n"
+		end;
+		file.puts "\t\t" + instr(0) + "\n"
+	else
+		file.puts "\t\t" + vhdl_trans_list[pc-1] + "  -- " + vhdl_comment_list[pc-1] + "\n"
+	end	
+	file.puts format("\t);\n")
+	puts format("I-ROM (loadable) file written to \"%s\"\n",filename)
+	file.close
+
+	# I-ROM TCL-Loader
+	filename = format("%s.irom.tcl.snip", PROJECT_NAME)
+	file = File.open(filename, "w")
+	file.puts format("# Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
+	file.puts format("# ---------------------------------------------------------------");
+	file.puts format("# Shift the USER1 Instruction (b1111000010) into the Instruction Register of FPGA");
+	file.puts format("# User 1")
+	file.puts format("set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C2\"]\n\n")
+	for i in (0..pc-1)
+		# Chipscope 8.1
+#		file.puts format("jtag_shiftdr $handle -buffer \"%s\" -endstate RTI -device $devid", vhdl_tcl_list[i].reverse);
+
+		# Chipscope 9.1
+		file.puts format("\# %s", vhdl_comment_list[i]) 
+		file.puts format("::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%8.8X\"\n\n", vhdl_tcl_list[i].length, vhdl_tcl_list[i].to_i(2));
+	end;
+	puts format("I-ROM TCL-loader written to \"%s\"\n",filename)
+	file.close
+
+	# X-ROM VHDL-ROM
+	filename = format("%s.xrom.vhdl.snip", PROJECT_NAME)
+	file = File.open(filename, "w")
+
+	file.puts format("ENTITY %s IS\n", XROM_ENTITY_NAME)
+	file.puts format("\tPort (\n")
+	file.puts format("\tclk\t\t\t: in  STD_LOGIC;\n")
+	file.puts format("\tce\t\t\t: in  STD_LOGIC;\n")
+	file.puts format("\taddr\t\t: in  %s;\n", XROM_ADDR_TYPE)
+	file.puts format("\tdout\t\t: out %s\n", XROM_DATA_TYPE)
+	file.puts format("\t);\n")
+	file.puts format("END %s;\n", XROM_ENTITY_NAME)
+	file.puts format("\n")
+	file.puts format("ARCHITECTURE %s OF %s IS \n", PROJECT_NAME, XROM_ENTITY_NAME)
+	file.puts format("\n")
+	file.puts format("\ttype xmem_rom_t is array (0 to %d) of %s;\n", XROM_MAX_SIZE-1, XROM_DATA_TYPE)
+	file.puts format("\n")
+	file.puts format("\t-- Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
+	file.puts format("\tconstant xmem_rom : xmem_rom_t :=\n")
+	file.puts format("\t(\n");
+	for i in (0..XROM_MAX_SIZE-2)
+		file.puts format("\t\tX\"%2.2X\", -- 0x%2.2X\n", first_pass.xmem[i], i)
+	end;
+	i = XROM_MAX_SIZE-1
+	file.puts format("\t\tX\"%2.2X\"  -- 0x%2.2X\n", first_pass.xmem[i], i)
+	file.puts format("\t);\n")
+	file.puts format("\n")
+	file.puts format("begin")
+	file.puts format("\n")
+	file.puts format("PROM_READ:")
+	file.puts format("\tprocess(clk, ce)\n")
+	file.puts format("\tbegin\n")
+	file.puts format("\t\tif rising_edge(clk) and ce = '1' then\n")
+	file.puts format("\t\t\tdout <= xmem_rom(to_integer(addr));\n")
+	file.puts format("\t\tend if;\n")
+	file.puts format("\tend process;\n")
+	file.puts format("\n")
+	file.puts format("end %s;\n", PROJECT_NAME)
+	puts format("X-ROM file written to \"%s\"\n",filename)
+	file.close
+
+	# X-ROM VHDL-ROM (loadable)
+	filename = format("%s.xrom_ld.vhdl.snip", PROJECT_NAME)
+	file = File.open(filename, "w")
+
+	file.puts format("\n\t-- Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
+	file.puts format("\ttype xmem_rom_t is array (0 to %d) of %s;\n", XROM_MAX_SIZE-1, XROM_DATA_TYPE)
+	file.puts format("\tsignal xmem_rom : xmem_rom_t :=\n")
+	file.puts format("\t(\n");
+	for i in (0..XROM_MAX_SIZE-2)
+		file.puts format("\t\tX\"%2.2X\", -- 0x%2.2X\n", first_pass.xmem[i], i)
+	end;
+	i = XROM_MAX_SIZE-1
+	file.puts format("\t\tX\"%2.2X\"  -- 0x%2.2X\n", first_pass.xmem[i], i)
+	file.puts format("\t);\n")
+	puts format("X-ROM (loadable) file written to \"%s\"\n",filename)
+	file.close
+
+	# X-ROM TCL-Loader
+	filename = format("%s.xrom.tcl.snip", PROJECT_NAME)
+	file = File.open(filename, "w")
+	file.puts format("# Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
+	file.puts format("# ---------------------------------------------------------------");
+	file.puts format("# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA");
+	file.puts format("# User 2")
+	file.puts format("set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C3\"]\n\n")
+	for i in (0..first_pass.xmem.length-1)
+		# Chipscope 8.1
+#		file.puts format("jtag_shiftdr $handle -buffer \"%s\" -endstate RTI -device $devid", vhdl_tcl_list[i].reverse);
+
+		# Chipscope 9.1
+		file.puts format("::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%2.2X%2.2X\"\n", 16, i, first_pass.xmem[i]);
+	end;
+	puts format("X-ROM TCL-loader written to \"%s\"\n",filename)
+	file.close
+
+end
+
+# --------------------------------------------------------
+# Output final statistics
+# --------------------------------------------------------
+if num_errors == 0
+	puts "Program uses #{first_pass.pc_max} instruction addresses"
+	puts "No errors found"
+	exit 0
+else
+	puts "#{num_errors} errors found"
+	exit 1
+end	
+

lib/CPUs/JCpu/tools/lib/cg.inc.jsm

@@ -0,0 +1,72 @@
+; -------------------------------------------------
+; lcd.inc.jsm
+; -------------------------------------------------
+; needs xio-address equates for
+; reg_cg_char_addr:	equ		0xXX	; RW
+; reg_cg_line_addr:	equ		0xXX	; RW
+; reg_cg_data:		equ		0xXX	; RW
+; reg_cg_ctrl:		equ		0xXX	; WO
+
+; needs delay.inc.jsm
+
+; -------------------------------------------------
+cg_clr_line:	push	R0
+				mov		R0, 2
+				xout	(reg_cg_ctrl), R0	
+				pop		R0
+				ret
+				
+; -------------------------------------------------
+cg_clr_screen:	push	R0
+				mov		R0, 1
+				xout	(reg_cg_ctrl), R0	
+				pop		R0
+				ret
+				
+; -------------------------------------------------
+; R0 : char address
+; R1 : line address
+cg_set_addr:	call	cg_wait_rdy
+				xout	(reg_cg_line_addr), R1
+				xout	(reg_cg_char_addr), R0
+				ret
+
+; -------------------------------------------------
+; R0 : character
+cg_putchar:		call	cg_wait_rdy
+				xout	(reg_cg_data), R0
+				ret				
+
+; -------------------------------------------------
+; R1 : ptr to string
+cg_puts:		push	R0
+cg_p_lp:		movx	R0, (R1)
+				inc		R1
+				tst		R0
+				jz		ex_cgp
+				call	cg_putchar
+				jmp		cg_p_lp
+ex_cgp:			pop		R0
+				ret				
+
+; -------------------------------------------------
+; R1 : ptr to string
+cg_clr_puts:	call	cg_clr_line
+				call	cg_puts
+				ret				
+
+; -------------------------------------------------
+; R1 : ptr to string
+cg_puts_clr:	call	cg_puts
+				call	cg_clr_line
+				ret				
+
+; -------------------------------------------------
+cg_wait_rdy:	push	R0
+cg_wr_lp:		xin		R0, (reg_hwstat)
+				and		R0, 0x02
+				jz		cg_wr_lp
+				pop		R0
+				ret
+
+; -------------------------------------------------

lib/CPUs/JCpu/tools/lib/cregs.inc.jsm

@@ -0,0 +1,7 @@
+; JCPU On-Chip register
+cpu_revision:		equ		0x00	; RO
+cpu_control:		equ		0x01	; R/W
+cpu_status:			equ		0x02	; RO
+cpu_int_ctrl:		equ		0x03	; RW
+cpu_cmem_high:		equ		0x04	; RW
+cpu_stack_high:		equ		0x05	; RW

lib/CPUs/JCpu/tools/lib/delays.inc.jsm

@@ -0,0 +1,64 @@
+; -------------------------------------------------
+; Delays
+; -------------------------------------------------
+delay1s:		push	R15
+				mov		R15, 10
+loop1s:			call 	delay100ms		
+				dec		R15
+				jnz		loop1s
+				pop		R15
+				ret
+
+delay100ms:		push	R15
+				mov		R15, 10
+loop100ms:		call 	delay10ms		
+				dec		R15
+				jnz		loop100ms
+				pop		R15
+				ret
+			
+delay10ms:		push	R15
+				mov		R15, 10
+loop10ms:		call	delay1ms		
+				dec		R15
+				jnz		loop10ms
+				pop		R15
+				ret
+		
+delay1ms:		push	R15
+				mov		R15, 10
+loop1ms:		call	delay100us
+				dec		R15
+				jnz		loop1ms
+				pop		R15
+				ret
+
+delay100us:		push	R15
+				mov		R15, 10
+loop100us:		call	delay10us
+				dec		R15
+				jnz		loop100us
+				pop		R15
+				ret
+
+delay10us:		push	R15
+				mov		R15, 99
+loop10us:		nop
+				nop
+				nop
+				dec		R15
+				jnz		loop10us
+				pop		R15
+				ret
+
+delay1us:		push	R15
+				mov		R15, 9
+loop1us:		nop
+				nop
+				nop
+				dec		R15
+				jnz		loop1us
+				pop		R15
+				ret
+				
+; -------------------------------------------------

lib/CPUs/JCpu/tools/lib/lcd.inc.jsm

@@ -0,0 +1,208 @@
+; -------------------------------------------------
+; lcd.inc.jsm
+; -------------------------------------------------
+; needs xmem-address definition for
+; - lcd_port (LCD-Base)
+
+; needs delay.inc.jsm
+
+; -------------------------------------------------
+lcd_cmd:		equ		0x00
+lcd_rd:			equ		0x20
+lcd_data:		equ		0x40
+lcd_enable:		equ		0x80
+
+LCD_CMD_Z1:		equ		0x80
+LCD_CMD_Z2:		equ		0xC0
+LCD_CMD_CLEAR:	equ		0x01
+
+; -------------------------------------------------
+; Init LCD
+; -------------------------------------------------
+LCD_init:		mov		R2, 0x00		
+				mov		R0, 0x03
+				call	_write_lcd
+				call	delay10ms
+				mov		R2, 0x00		
+				mov		R0, 0x03
+				call	_write_lcd
+				call	delay10ms
+
+				mov		R2, 0x00		
+				mov		R0, 0x02
+				call	_write_lcd
+				call	delay1ms
+
+				; 1. Function set: 4-Bit mode, two display lines
+				mov		R0, 0x28
+				call	LCD_writecmd
+
+				; 2. Display on, no cursor
+				mov		R0, 0x0C		
+				call	LCD_writecmd
+
+				; 3. Cursor shift during write
+				mov		R0, 0x06
+				call	LCD_writecmd
+
+				; 4. Display clear
+				mov		R0, 0x01
+				call	LCD_writecmd
+
+				ret
+				
+; -------------------------------------------------
+; LCD_waitbsy
+; -------------------------------------------------
+LCD_waitbsy:	push	R0
+bsy_loop:		call	LCD_readstat
+				and		R0, 0x80
+				jz		ex_bsy
+				call	delay1us
+				jmp		bsy_loop
+ex_bsy:			pop		R0
+				ret
+
+; -------------------------------------------------
+; LCD_writecmd
+; -------------------------------------------------
+; R0 = cmd
+LCD_writeaddr:
+LCD_writecmd:	push	R2
+				mov		R2, lcd_cmd
+				call	LCD_write
+				pop		R2
+				ret
+
+; -------------------------------------------------
+; LCD_putsx
+; -------------------------------------------------
+; R1 = address of null-terminated string in XMEM
+LCD_putsx:		push	R0
+putsx_loop:		movx	R0, (R1)
+				inc		R1
+				tst		R0
+				jz		putsx_ex
+				call	LCD_writechar
+				jmp		putsx_loop
+putsx_ex:		pop		R0
+				ret
+				
+; -------------------------------------------------
+; LCD_putsc
+; -------------------------------------------------
+; R1 = address of null-terminated string in CMEM
+LCD_putsc:		push	R0
+putsc_loop:		movc	R0, (R1)
+				inc		R1
+				tst		R0
+				jz		putsc_ex
+				call	LCD_writechar
+				jmp		putsc_loop
+putsc_ex:		pop		R0
+				ret
+				
+; -------------------------------------------------
+; LCD_writechar
+; -------------------------------------------------
+; R0 = char
+LCD_writedata:
+LCD_writechar:	push	R2
+				mov		R2, lcd_data
+				call	LCD_write
+				pop		R2
+				ret
+				
+; -------------------------------------------------
+; LCD_write
+; -------------------------------------------------
+; R0 = input
+; R2 = register
+LCD_write:		call	LCD_waitbsy
+				push	R0
+				swap	R0
+				call	_write_lcd
+				pop		R0
+				call	_write_lcd
+				ret
+
+; -------------------------------------------------
+; LCD_readstat
+; -------------------------------------------------
+; R0 = status
+LCD_readstat:	push	R2
+				mov		R2, lcd_cmd
+				call	LCD_read
+				pop		R2
+				ret
+
+; -------------------------------------------------
+; LCD_read
+; -------------------------------------------------
+; R0 = output
+; R2 = register
+LCD_read:		call	_read_lcd
+				swap	R0
+				push	R0
+				call	_read_lcd
+				pop		R2
+				or		R0, R2
+				ret
+				
+; -------------------------------------------------
+; _write
+; -------------------------------------------------
+; R0 = input
+_write_lcd:		push	R1
+
+				and		R0, 0x0F
+				mov		R1, R0
+				or		R1, R2
+				xout	(lcd_port), R1
+				call	delay1us
+
+				mov		R1, R0
+				or		R1, R2
+				or		R1, lcd_enable
+				xout	(lcd_port), R1
+				call	delay1us
+
+				mov		R1, R0
+				or		R1, R2
+				xout	(lcd_port), R1
+				call	delay1us
+
+				or		R1, lcd_rd
+				xout	(lcd_port), R1
+
+				pop		R1
+				ret
+
+; -------------------------------------------------
+; _read
+; -------------------------------------------------
+; R0 = output
+_read_lcd:		push	R1
+
+				mov		R1, lcd_rd
+				or		R1, R2
+				xout	(lcd_port), R1
+				call	delay1us
+
+				mov		R1, lcd_rd
+				or		R1, R2
+				or		R1, lcd_enable
+				xout	(lcd_port), R1
+				call	delay1us
+				xin		R0, (lcd_port)
+				and		R0, 0x0F
+
+				mov		R1, lcd_rd
+				or		R1, R2
+				xout	(lcd_port), R1
+				call	delay1us
+
+				pop		R1
+				ret
+
+				

lib/CPUs/JCpu/tools/lib/mul8x8.inc.jsm

@@ -0,0 +1,42 @@
+; -------------------------------------------------
+; mul8x8.inc.jsm
+; -------------------------------------------------
+
+; -------------------------------------------------
+; Parameter:
+; R0 : operand 1
+; R1 : operand 2
+; Return:
+; R0 : product low
+; R1 : product high
+mul8x8:			push	R2
+				push	R3
+				push	R4
+				
+				mov		R4, R1
+				mov		R1, 0
+				mov		R2, 0
+				mov		R3, 0
+				
+loop1:			cmp		R4, 0x01
+				jeq		ende1
+
+				shr		R4
+				jnc		next1
+
+				add		R2, R0
+				addc	R3, R1
+
+next1:			shl		R0
+				rolc	R1
+				jmp		loop1
+				
+ende1:			add		R0, R2
+				addc	R1, R3
+				
+				pop		R4
+				pop		R3
+				pop		R2
+				ret
+
+; -------------------------------------------------

lib/CPUs/JCpu/tools/lib/uart.inc.jsm

@@ -0,0 +1,32 @@
+; -------------------------------------------------
+; uart.inc.jsm
+; -------------------------------------------------
+; needs xmem-address definition for
+; - uart_status (Status register)
+; - uart_data	(Data register)
+
+; -------------------------------------------------
+; sout
+; -------------------------------------------------
+; R0 = input
+sout:			push 	R1
+sout1:			xin		R1, (uart_status)
+				and		R1, 0x02
+				jnz		sout1
+				xout	(uart_data), R0
+				pop		R1
+				ret
+
+; -------------------------------------------------
+; sin
+; -------------------------------------------------
+; R0 = output
+sin:			push 	R1
+sin1:			xin		R1, (uart_status)
+				and		R1, 0x10
+				jnz		sin1
+				xin		R0, (uart_data)
+				pop		R1
+				ret
+
+; -------------------------------------------------

lib/CPUs/JCpu/tools/lib/utils.inc.jsm

@@ -0,0 +1,32 @@
+; -------------------------------------------------
+; utils.inc.jsm
+; -------------------------------------------------
+
+
+; -------------------------------------------------
+; Parameter
+; R0 : Bin value in lower nibble
+; Return
+; R0 : Hex character representing lower nibble
+nibble2hex:		and		R0, 0x0F
+				cmp		R0, 0x0A
+				jlt		isNum1
+				add		R0, 0x07
+isNum1:			add		R0, 0x30
+				ret
+
+; -------------------------------------------------
+; Parameter
+; R0 : Bin value
+; Return
+; R0 : Hex character high
+; R1 : Hex character low
+bin2hex:		push	R0
+				call	nibble2hex
+				mov		R1, R0
+				pop		R0
+				swap	R0
+				call	nibble2hex
+				ret
+
+; -------------------------------------------------

lib/CPUs/JCpu/tools/opc.list

@@ -0,0 +1,64 @@
+0 NOP         
+1 HALT        
+2 MOV|R|R     
+3 MOV|R|K     
+4 MOVX|R|Ri   
+5 MOVX|R|Ki   
+6 MOVX|Ri|R   
+7 MOVX|Ri|K   
+8 MOVX|Ki|R   
+9 MOVC|R|Ri   
+10 MOVC|R|Ki   
+11 MOVC|Ri|R   
+12 MOVC|Ri|K   
+13 MOVC|Ki|R   
+14 CMP|R|R     
+15 CMP|R|K     
+16 ADD|R|R     
+17 ADD|R|K     
+18 ADDC|R|R    
+19 ADDC|R|K    
+20 SUB|R|R     
+21 SUB|R|K     
+22 SUBC|R|R    
+23 SUBC|R|K    
+24 AND|R|R     
+25 AND|R|K     
+26 OR|R|R      
+27 OR|R|K      
+28 XOR|R|R     
+29 XOR|R|K     
+30 SHL|R       
+31 SHR|R       
+32 ROL|R       
+33 ROR|R       
+34 ROLC|R      
+35 RORC|R      
+36 XOUT|Ki|R   
+37 XOUT|Ri|K   
+38 COUT|Ki|R   
+39 COUT|Ri|K   
+40 XIN|R|Ki    
+41 CIN|R|Ki    
+42 SWAP|R      
+43 SETC        
+44 UNDEF       
+45 UNDEF       
+46 SUB|K|R     
+47 SUBC|K|R    
+48 JMP|K       
+49 JZ|K        
+50 JNZ|K       
+51 JC|K        
+52 JNC|K       
+53 JLT|K       
+54 JGT|K       
+55 JLE|K       
+56 JGE|K       
+57 JEQ|K       
+58 JNE|K       
+59 CALL|K      
+60 PUSH|R      
+61 POP|R       
+62 RET         
+63 RETI        

lib/CPUs/JCpu/tools/regx.rb

@@ -0,0 +1,20 @@
+#!/usr/bin/env ruby
+
+st = "\033[7m"
+en = "\033[m"
+
+ while TRUE
+   print "str> "
+   STDOUT.flush
+   str = gets
+   break if not str
+   str.chop!
+   print "pat> "
+   STDOUT.flush
+   re = gets
+   break if not re
+   re.chop!
+   str.gsub! re, "#{st}\\&#{en}"
+   print str, "\n"
+end
+print "\n"

lib/CPUs/JCpu/tools/rom.tcl.tpl

@@ -0,0 +1,61 @@
+# ----------------------------------------------------------------------
+# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+# This file: The ROM file for upload to target over JTAG 
+#
+# Copyright (C) 2007 J. Ahrensfeld
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+# 
+# For questions and ideas, please contact the author at jens@jayfield.org
+#
+# ---------------------------------------------------------------------
+
+# ---------------------------------------------------------------------
+# For Chipscope 9.1
+# ---------------------------------------------------------------------
+# Source JTAG/TCL frame work
+cd $env(CHIPSCOPE)\\bin\\nt
+source csejtag.tcl
+
+namespace import ::chipscope::*
+
+# Platform USB Cable
+set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"]
+# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
+
+# Create session
+set handle [::chipscope::csejtag_session create 0]
+
+# Open JTAG and lock
+set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
+set lock_result [::chipscope::csejtag_target lock $handle 1000]
+
+set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
+
+# Get Device ID
+set devtype "Virtex-4SX"
+set devid 2
+set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
+set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
+
+set CSE_OP $CSEJTAG_SHIFT_READWRITE
+set CSE_ES $CSEJTAG_RUN_TEST_IDLE
+
+# Write Program
+# JASM_ROM_INSERT_HERE
+
+::chipscope::csejtag_target unlock $handle
+::chipscope::csejtag_target close $handle
+::chipscope::csejtag_session destroy $handle
+exit

lib/CPUs/JCpu/tools/templates.rb

@@ -0,0 +1,44 @@
+#!/usr/bin/env ruby
+
+
+template = <<'END'
+		-- (tv #1342) read output FIFO
+		(
+			cycles		=>	1,
+			cm_i		=>	bus_read_init(addr => ADDR_KS_OFIFO_DOUT),
+			sep			=>	msg(""),
+			cm_o 		=>	bus_no_ack,
+			irq			=>	(others => '0')
+		),
+
+		-- (tv #1343) wait while FIFO is read
+		(
+			cycles		=>	2,
+			cm_i		=>	bus_wait_ack,
+			sep			=>	msg(""),
+			cm_o 		=>	bus_no_ack,
+			irq			=>	(others => '0')
+		),
+
+		-- (tv #1343) wait for ack
+		(
+			cycles		=>	1,
+			cm_i		=>	bus_wait_ack,
+			sep			=>	msg(""),
+			cm_o 		=>	bus_read_ack(dat => #{exp_data}),
+			irq			=>	(others => '0')
+		),
+
+END
+
+puts "KS-128 testvectors:\n"
+puts "\n" * 3
+
+
+0.upto(10) { |sk_no|
+	3.downto(0) { |sl_no|
+		exp_data = "slice_32(TC1_SUBKEYS(#{sk_no}), #{sl_no})"
+		t = template.gsub(/"/, '\\"')
+		puts eval("format(\"#{t}\")")
+	}
+}

lib/CPUs/JCpu/tools/xrom.vhd.tpl

@@ -0,0 +1,32 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: The ROM file for use in your VHDL design
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library work;
+use work.cpu_pkg.all;
+
+-- JASM_ROM_INSERT_HERE
+

lib/CPUs/JCpu/tools/xrom_ld.vhd.tpl

@@ -0,0 +1,151 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: loadable ROM
+--
+-- Copyright (C) 2007 J. Ahrensfeld
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-- For questions and ideas, please contact the author at jens@jayfield.org
+--
+--------------------------------------------------------------------------
+
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+
+library work;
+use work.cpu_pkg.all;
+
+ENTITY xrom IS
+	Port (
+		clk			: in  STD_LOGIC;
+		ce			: in  STD_LOGIC;
+		addr		: in  dmem_addr_t;
+		dout		: out dmem_data_t
+	);
+	
+END xrom;
+
+ARCHITECTURE loadable OF xrom IS 
+
+	-- JASM_ROM_INSERT_HERE
+
+	signal jtag_ld_clk		: STD_LOGIC;
+	signal jtag_ld_we		: STD_LOGIC;
+	signal jtag_ld_addr		: dmem_addr_t;
+	signal jtag_ld_dout		: dmem_data_t;
+	signal jtag_ld_din		: dmem_data_t;
+	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
+	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
+	signal user_regi, user_rego : unsigned (15 downto 0);
+	constant id : unsigned (15 downto 0) := X"BEEF";
+
+begin
+
+--------------------------------------------------------------------------
+-- Virtex-4: JTAG Loader
+--------------------------------------------------------------------------
+	i00_BUFG : BUFG
+	port map
+	(
+		O => bs_clk1,
+        I => bs_clk0
+	);
+	
+	i01_BUFG : BUFG
+	port map
+	(
+		O => bs_update1,
+        I => bs_update0
+	);
+
+	BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 
+	generic map
+	(
+		JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
+	)
+	port map 
+	(
+		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
+		DRCK => bs_clk0,       -- Data register output for USER functions
+		RESET => bs_rst,       -- Reset output from TAP controller
+		SEL => bs_sel,         -- USER active output
+		SHIFT => bs_shift,     -- SHIFT output from TAP controller
+		TDI => bs_tdi,        -- TDI output from TAP controller
+		UPDATE => bs_update0,   -- UPDATE output from TAP controller
+		TDO => bs_tdo         -- Data input for USER function
+	);
+
+	jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1);
+	jtag_ld_din <= user_regi(dmem_data_t'left downto 0);
+	jtag_ld_clk <= bs_update1;
+	jtag_ld_we <= bs_sel;
+	
+sipo:
+	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
+	begin
+		if bs_rst = '1' then
+			user_regi <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
+			end if;
+		end if;
+	end process;	
+
+piso:
+	process (bs_rst, bs_clk1, bs_shift, user_rego)
+	begin
+		bs_tdo <= user_rego(0);
+		if bs_rst = '1' then
+			user_rego <= (others => '0');
+		elsif rising_edge(bs_clk1) then
+			if bs_shift = '1' then
+				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
+			else
+				user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout;	
+--				user_rego <= id;	
+			end if;
+		end if;
+	end process;	
+	
+--------------------------------------------------------------------------
+-- ROM Read/Write
+--------------------------------------------------------------------------
+PROM_READ: 
+	process(clk, ce)
+	begin
+		if rising_edge(clk) and ce = '1' then
+			dout <= xmem_rom(to_integer(addr));
+		end if;
+	end process;
+
+PROM_WRITE: 
+	process(jtag_ld_clk, jtag_ld_we)
+	begin
+		if rising_edge(jtag_ld_clk) then
+			if jtag_ld_we = '1' then
+				xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
+			else	
+				jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr));
+			end if;
+		end if;	
+	end process;
+
+--------------------------------------------------------------------------
+end loadable;

lib/CPUs/MIPS/bsp/examples/Bessel.c

@@ -0,0 +1,87 @@
+/************************************************************************/
+/* Ein Programm zur Berechnung der Bessel-Koeffizienten Jn
+/* Dateiname		    : Bessel.cpp
+/* Autoren		    	: T. Burr, J. Ahrensfeld
+/* Datum			      : 28.10.1999
+/* letzte Änderung	: 28.01.2000
+/* Version			    : 1.0
+/************************************************************************/
+
+#include "stdio.h"
+#include "math.h"
+#include "stdlib.h"
+
+
+#define MAX_SUM 25
+#define VERSION "1.0"
+
+/************************************************************************/
+/* Funktionsdeklarationen */
+/************************************************************************/
+// Fakultätsberechnung
+double fak (int N)
+{
+	int index;
+	double erg=1;
+
+	for (index = 1; index <= N; index++)
+		erg = erg * index;
+
+	return erg;
+}
+
+// Bessel()
+// Berechnung von Jn von mfm
+double bessel(int n, double mfm)
+{
+	int m;
+	double Jn=0;
+
+	for (m=0; m < MAX_SUM; m++)
+	{
+		Jn = Jn + (pow(-1.0,m)/(fak(m)*fak(m+n))*pow(mfm/2.0,(2*m+n)));
+	}
+	return Jn;
+}
+
+
+/************************************************************************/
+/* Das Hauptprogramm
+/************************************************************************/
+void main()
+{
+
+	int N, Nmax;
+	double erg;
+	float mfm;
+
+	printf("\n\t     Besselfunktion Version %s",VERSION);
+	printf("\n\t     ~~~~~~~~~~~~~~~~~~~~~~~~~~\n");
+	printf("\n\tCopyright by J. Ahrensfeld & T. Burr\n\n");
+
+// ---------------------------------------------------------------------------------
+		// Benutzereingaben
+		printf("\nBerechnungen fuer J = 0...");
+		if(scanf("%d",&Nmax)==0)
+			exit (-1);
+
+		printf("Bitte Modulationsindex eingeben : ");
+		if(scanf("%f",&mfm)==0)
+			exit(-1);
+
+		printf("\n");
+
+// ---------------------------------------------------------------------------------
+		// Berechnung
+		for (N=0; N <= Nmax; N++)
+		{
+			erg = bessel(N,(double)mfm);
+			printf("J(%d) = %10.8f\n",N,erg);
+		}
+
+		printf("FERTIG.\n");
+
+	}
+
+/************************************************************************/
+

lib/CPUs/MIPS/bsp/examples/Makefile

@@ -0,0 +1,134 @@
+TOOLS_DIR=../../tools
+
+CFLAGS=-msoft-float -O2 -march=r3000 -I.
+LFLAGS=-M -T link.ld
+LIB_DIRS=-L . -L /usr/local/mipsel-elf/lib -L /usr/local/lib/gcc/mipsel-elf/4.3.2
+LIBS=-lc -lm -lgcc
+
+AS=mipsel-elf-as
+AR=mipsel-elf-ar
+CC=mipsel-elf-gcc
+LD=mipsel-elf-ld
+OBJDUMP=mipsel-elf-objdump
+OBJCOPY=mipsel-elf-objcopy
+FLASHGEN=$(TOOLS_DIR)/flashgen_little
+
+PROG = hello testbench test_irq dhry queens stanford paranoia rmd160_test Bessel whet phrasen dttl richards_benchmark
+
+all: $(PROG)
+
+libsys: startup.S init.S kernel.S libsys.c xcpt.c irq.c
+	$(CC) $(CFLAGS) -G 0 -c startup.S -o startup.o
+	$(CC) $(CFLAGS) -G 0 -c kernel.S -o kernel.o
+	$(CC) $(CFLAGS) -G 0 -c init.S -o init.o
+	$(CC) $(CFLAGS) -G 0 -c libsys.c -o libsys.o
+	$(CC) $(CFLAGS) -G 0 -c xcpt.c -o xcpt.o
+	$(CC) $(CFLAGS) -G 0 -c irq.c -o irq.o
+	$(AR) -r libsys.a init.o libsys.o xcpt.o irq.o
+
+hello: hello.c 
+	$(CC) $(CFLAGS) -c hello.c
+	$(LD) $(LFLAGS) $(LIB_DIRS) hello.o -o $@.elf $(LIBS) >$@.map
+	$(OBJDUMP) -d $@.elf > $@.dis
+	$(OBJCOPY) $@.elf -O binary $@.bin
+	$(OBJCOPY) -O srec $@.elf $@.srec
+	$(FLASHGEN) $@.bin
+
+testbench: testbench.c 
+	$(CC) $(CFLAGS) -c testbench.c paranoia.c -DNOSIGNAL -DBATCHMODE -DNOMAIN
+	$(LD) $(LFLAGS) $(LIB_DIRS) paranoia.o testbench.o -o $@.elf $(LIBS) >$@.map
+	$(OBJDUMP) -d $@.elf > $@.dis
+	$(OBJCOPY) $@.elf -O binary $@.bin
+	$(OBJCOPY) -O srec $@.elf $@.srec
+	$(FLASHGEN) $@.bin
+
+test_irq: test_irq.c 
+	$(CC) $(CFLAGS) -c test_irq.c
+	$(LD) $(LFLAGS) $(LIB_DIRS) test_irq.o -o $@.elf $(LIBS) >$@.map
+	$(OBJDUMP) -d $@.elf > $@.dis
+	$(OBJCOPY) $@.elf -O binary $@.bin
+	$(OBJCOPY) -O srec $@.elf $@.srec
+	$(FLASHGEN) $@.bin
+
+dhry: dhry_1.c dhry_2.c dhry.h
+	$(CC) $(CFLAGS) -DHZ=1000 -c dhry_1.c dhry_2.c
+	$(LD) $(LFLAGS) $(LIB_DIRS) dhry_1.o dhry_2.o -o $@.elf $(LIBS) >$@.map
+	$(OBJDUMP) -d $@.elf > $@.dis
+	$(OBJCOPY) $@.elf -O binary $@.bin
+	$(OBJCOPY) -O srec $@.elf $@.srec
+	$(FLASHGEN) $@.bin
+
+queens: queens.c 
+	$(CC) $(CFLAGS) -DUNIX_Old -DHZ=1000 -c queens.c
+	$(LD) $(LFLAGS) $(LIB_DIRS) queens.o -o $@.elf $(LIBS) >$@.map
+	$(OBJDUMP) -d $@.elf > $@.dis
+	$(OBJCOPY) $@.elf -O binary $@.bin
+	$(OBJCOPY) -O srec $@.elf $@.srec
+	$(FLASHGEN) $@.bin
+
+stanford: stanford.c
+	$(CC) $(CFLAGS) -DHZ=1000 -c stanford.c
+	$(LD) $(LFLAGS) $(LIB_DIRS) stanford.o -o $@.elf $(LIBS) >$@.map
+	$(OBJDUMP) -d $@.elf > $@.dis
+	$(OBJCOPY) $@.elf -O binary $@.bin
+	$(OBJCOPY) -O srec $@.elf $@.srec
+	$(FLASHGEN) $@.bin
+
+paranoia: paranoia.c
+	$(CC) $(CFLAGS) -DNOSIGNAL -DBATCHMODE -g -c paranoia.c
+	$(LD) $(LFLAGS) $(LIB_DIRS) paranoia.o -o $@.elf $(LIBS) >$@.map
+	$(OBJDUMP) -d $@.elf > $@.dis
+	$(OBJCOPY) $@.elf -O binary $@.bin
+	$(OBJCOPY) -O srec $@.elf $@.srec
+	$(FLASHGEN) $@.bin
+
+rmd160_test: rmd160_test.c rmd160.c rmd160.h
+	$(CC) $(CFLAGS) -DNOSIGNAL -DBATCHMODE -g -c rmd160.c rmd160_test.c
+	$(LD) $(LFLAGS) $(LIB_DIRS) rmd160.o rmd160_test.o -o $@.elf $(LIBS) >$@.map
+	$(OBJDUMP) -d $@.elf > $@.dis
+	$(OBJCOPY) $@.elf -O binary $@.bin
+	$(OBJCOPY) -O srec $@.elf $@.srec
+	$(FLASHGEN) $@.bin
+
+Bessel: Bessel.c 
+	$(CC) $(CFLAGS) -g -c Bessel.c
+	$(LD) $(LFLAGS) $(LIB_DIRS) Bessel.o -o $@.elf $(LIBS) >$@.map
+	$(OBJDUMP) -d $@.elf > $@.dis
+	$(OBJCOPY) $@.elf -O binary $@.bin
+	$(OBJCOPY) -O srec $@.elf $@.srec
+	$(FLASHGEN) $@.bin
+
+whet: whet.c 
+	$(CC) $(CFLAGS) -c whet.c
+	$(LD) $(LFLAGS) $(LIB_DIRS) whet.o -o $@.elf $(LIBS) >$@.map
+	$(OBJDUMP) -d $@.elf > $@.dis
+	$(OBJCOPY) $@.elf -O binary $@.bin
+	$(OBJCOPY) -O srec $@.elf $@.srec
+	$(FLASHGEN) $@.bin
+
+phrasen: phrasen.c 
+	$(CC) $(CFLAGS) -g -c phrasen.c
+	$(LD) $(LFLAGS) $(LIB_DIRS) phrasen.o -o $@.elf $(LIBS) >$@.map
+	$(OBJDUMP) -d $@.elf > $@.dis
+	$(OBJCOPY) $@.elf -O binary $@.bin
+	$(OBJCOPY) -O srec $@.elf $@.srec
+	$(FLASHGEN) $@.bin
+
+dttl: dttl.c random.c
+	$(CC) $(CFLAGS) -g -c dttl.c random.c
+	$(LD) $(LFLAGS) $(LIB_DIRS) random.o dttl.o -o $@.elf $(LIBS) >$@.map
+	$(OBJDUMP) -d $@.elf > $@.dis
+	$(OBJCOPY) $@.elf -O binary $@.bin
+	$(OBJCOPY) -O srec $@.elf $@.srec
+	$(FLASHGEN) $@.bin
+
+richards_benchmark: richards_benchmark.c 
+	$(CC) $(CFLAGS) -c richards_benchmark.c
+	$(LD) $(LFLAGS) $(LIB_DIRS) richards_benchmark.o -o $@.elf $(LIBS) >$@.map
+	$(OBJDUMP) -d $@.elf > $@.dis
+	$(OBJCOPY) $@.elf -O binary $@.bin
+	$(OBJCOPY) -O srec $@.elf $@.srec
+	$(FLASHGEN) $@.bin
+
+clean:
+	rm -rf *.a *.o *.bin *.map *.dis *.srec *.elf $(PROG) > /dev/null

lib/CPUs/MIPS/bsp/examples/bootloader.c

@@ -0,0 +1,403 @@
+#include "libsys.h"
+#include "cfiflash.h"
+
+typedef struct _ssrec_t
+{
+	UINT32 addr;
+	UINT32 size;
+	UINT32 type;
+	UINT8 *data;
+
+} srec_t;
+
+enum srec_type
+{
+	srec_err, srec_sob, srec_data, srec_rec, srec_eob
+};
+
+UINT8 h2i(UINT8 *c)
+{
+	int i;
+	UINT8 t, b = 0;
+
+	for (i=0; i < 2; i++)
+	{
+		t = c[i];
+		if (t >= 'A')
+			t = t - 'A' + 10;
+		else
+			t -= '0';
+
+		b = (b << 4) | t;
+	}
+	return b;
+}
+
+int decode_srec(srec_t *pRec, UINT8 *pBuf, int buflen)
+{
+	UINT8 chksum, byte;
+	int alen, i;
+
+	if (!buflen)
+		return srec_err;
+
+	pRec->type = srec_rec;
+	alen = 0;
+	if ((pBuf[1] > '0') && (pBuf[1] < '4'))
+	{
+	  alen = pBuf[1] - '0' + 1;
+	  pRec->type = srec_data;
+	}
+	else if ((pBuf[1] >= '7') && (pBuf[1] <= '9'))
+	{
+	  alen = 11 - (pBuf[1] - '0');
+	  pRec->type = srec_eob;
+	}
+	else if (pBuf[1] == '0')
+	{
+	  alen = 2;
+	  pRec->type = srec_sob;
+	}
+
+	byte = h2i(&pBuf[2]);
+	pRec->size = byte;
+	chksum = byte;
+
+	pRec->addr = 0;
+	for (i=0; i < alen; i++)
+	{
+		byte = h2i(&pBuf[4+2*i]);
+        pRec->addr = pRec->addr << 8 | byte;
+		chksum += byte;
+	}
+	pRec->size -= (alen+1);
+
+	pRec->data = (UINT8*) &pBuf[4 + 2*alen];
+	for (i=0; i < (int)pRec->size; i++)
+	{
+		byte = h2i(&pRec->data[2*i]);
+		pRec->data[i] = byte;
+		chksum += byte;
+	}
+	chksum = ~chksum;
+	byte = h2i(&pRec->data[2*i]);
+	if (chksum != byte)
+		return 0;
+
+	return pRec->type;
+}
+
+int srec_getline(UINT8 *pLine)
+{
+	char c;
+	int i = 0;
+
+	do
+	{
+		c = readchar();
+
+	} while ((c != 's') && (c != 'S'));
+
+	while(((c != 0x0D) && (c != 0x0A)))
+	{
+		pLine[i++] = c;
+		c = readchar();
+	};
+
+	return i;
+}
+
+void Exec_at(void *pEntry)
+{
+	__asm
+	(
+		".set	noreorder\n"
+		"mfc0	$26, $12\n"			// change exception vector
+		"li		$27, 0xFFBFFFFF\n"
+		"and	$26, $27\n"
+		"mtc0	$26, $12\n"
+		"jr		$4\n"				// jump entry
+		"rfe\n"
+		".set	reorder\n"
+
+	);
+}
+
+void PrintCPUinfo(void)
+{
+	int result, rev_id;
+
+	char *cpu_type_str[7] = {"invalid", "R2000", "R3000", "R6000", "R4000", "reserved", "R6000A"};
+
+	// Print Status register
+	result = CP0_SR_read();
+
+	sputs("Status  : ");
+	print_word(result);
+	sputs("\n");
+
+	// Print Revision
+	result = CP0_PRID_read();
+	rev_id = (result >> 8) & 0xFF;
+	sputs("CPU type: ");
+	if ((rev_id > 0) && (rev_id < 0x07))
+	{
+		sputs(cpu_type_str[rev_id]);
+		sputs(" Rev.");
+		rev_id = result & 0xFF;
+		print_byte((char)rev_id);
+	}
+	else
+		sputs("Unknown");
+
+	sputs("\n");
+
+}
+
+
+#define	TEST_SIZE			(1024*1024)	// bytes
+//#define	TEST_SIZE			(1024)	// bytes
+#define SDRAM_BASE			0x40000000
+#define	IMAGE_OFFSET		0x01000000
+#define	FLASH_OFFSET		0x00700000
+
+int main(int argc, char *argv[])
+{
+	UINT8 buf[256];
+	srec_t srec;
+	int result, i;
+	UINT32 haddr, addr;
+	flash_t flash;
+
+	volatile UINT32 *pReg = (UINT32*)sys_led_port;
+	volatile UINT32 *pBtn = (UINT32*)sys_gpio0;
+	volatile UINT8 *pMem;
+	volatile UINT32 *pROM32;
+	volatile UINT32 *pMem32;
+	volatile UINT32 *pFlash = (UINT32*)sys_flash_io;
+	volatile UINT32 *pUSB = (UINT32*)sys_usb_data;
+
+	volatile UINT8 *ram8 = (UINT8*)SDRAM_BASE;
+	volatile UINT16 *ram16 = (UINT16*)SDRAM_BASE;
+	volatile UINT32 *ram32 = (UINT32*)SDRAM_BASE;
+
+	*pReg = 0;
+	haddr = 0;
+/*
+	__asm __volatile
+	(
+		".set	noreorder\n"
+		"li $a0, 0xA0020000\n"
+		"li $t0, 0x12345678\n"
+		"li $t1, 0x5555AAAA\n"
+		"sw $t0, 0($a0)\n"
+//		"nop\n"
+		"sw $t1, 4($a0)\n"
+//		"nop\n"
+		"lw $v0, 0($a0)\n"
+//		"nop\n"
+		"lw $v0, 4($a0)\n"
+//		"nop\n"
+		"sw $t0, 0($a0)\n"
+//		"nop\n"
+		"lw $v0, 4($a0)\n"
+//		"nop\n"
+		"sw $t1, 4($a0)\n"
+//		"nop\n"
+		"lw $v0, 0($a0)\n"
+		".set	reorder\n"
+	);
+	__asm __volatile
+	(
+		".set	noreorder\n"
+		"lui    $v1, 0xA002\n"
+		"lui	$v0,0x70\n"
+		"ori	$v0,$v0,0x70\n"
+		"sw	$v0,0($v1)\n"
+		"lui	$a0,0x4002\n"
+		"lw	$a1,0($v1)\n"
+		"lw	$ra,12($sp)\n"
+		"lw	$s1,8($sp)\n"
+		"lw	$s0,4($sp)\n"
+		".set	reorder\n"
+	);
+
+*/
+//	PrintCPUinfo();
+/*
+	*(pFlash+0) = 0x12345678;
+	*(pFlash+1) = 0xAAAA5555;
+	*(pFlash+2) = 0xFFFF0000;
+	*(pFlash+3) = 0x0000FFFF;
+
+	*pReg = *(pFlash+0);
+	*pReg = *(pFlash+1);
+	*pReg = *(pFlash+2);
+	*pReg = *(pFlash+3);
+
+	*(pUSB+0) = 0x12345678;
+	*(pUSB+1) = 0xAAAA5555;
+	*(pUSB+2) = 0xFFFF0000;
+	*(pUSB+3) = 0x0000FFFF;
+
+	*pReg = *(pUSB+0);
+	*pReg = *(pUSB+1);
+	*pReg = *(pUSB+2);
+	*pReg = *(pUSB+3);
+	sputs("BOOT ");
+
+	pMem32 = (UINT32*)0x40000000;
+	pROM32 = (UINT32*)0x00000000;
+	for (i=0; i < 0x3500; i+=4)
+		*pMem32++ = *pROM32++;
+
+	Exec_at((void*)0x40000000);
+
+
+	// Memtest BEGIN
+	sputs("SDRAM Memory Test\r\n");
+	sputs("Write (8-Bit access)...");
+	for (i=0; i < TEST_SIZE; i++)
+		ram8[i] = (UINT8)i;
+
+	sputs("done\r\n");
+
+	sputs("Verify (8-Bit access)...");
+	for (i=TEST_SIZE-1; i >= 0; i--)
+		if (ram8[i] != (UINT8)i)
+			break;
+	i++;
+	if (i)
+		sputs("failed\r\n");
+	else
+		sputs("passed\r\n");
+
+
+	sputs("Write (16-Bit access)...");
+	for (i=0; i < TEST_SIZE/2; i++)
+		ram16[i] = (UINT16)i;
+
+	sputs("done\r\n");
+
+	sputs("Verify (16-Bit access)...");
+	for (i=TEST_SIZE/2-1; i >= 0; i--)
+		if (ram16[i] != (UINT16)i)
+			break;
+	i++;
+	if (i)
+		sputs("failed\r\n");
+	else
+		sputs("passed\r\n");
+
+
+	sputs("Write (32-Bit access)...");
+	for (i=0; i < TEST_SIZE/4; i++)
+		ram32[i] = (UINT32)i;
+
+	sputs("done\r\n");
+
+	sputs("Verify (32-Bit access)...");
+	for (i=TEST_SIZE/4-1; i >= 0; i--)
+		if (ram32[i] != (UINT32)i)
+			break;
+	i++;
+	if (i)
+		sputs("failed\r\n");
+	else
+		sputs("passed\r\n");
+
+	for (i=0; i < TEST_SIZE/4; i++)
+		ram32[i] = 0;
+
+	// Memtest END
+	// ----------------------------------------------------------
+*/
+	ram32 = (UINT32*)(SDRAM_BASE + IMAGE_OFFSET);
+	pFlash = (UINT32*)(sys_flash_io + FLASH_OFFSET);
+	print_word((UINT32)*pBtn);
+	if (!*pBtn)
+	{
+		sputs("Booting from flash..");
+		for (i=0; i < TEST_SIZE/4; i++)
+			ram32[i] = pFlash[i];
+
+		sputs("done");
+
+		Exec_at((void*)ram32);
+	}
+	else
+	{
+
+		sputs("SDRAM erase at        : ");
+		print_word((UINT32)ram32);
+		sputs("\n");
+		for (i=0; i < TEST_SIZE/4; i++)
+			ram32[i] = 0;
+
+		cfi_init(&flash, sys_flash_io);
+		if (cfi_find(&flash) < 0)
+			return 1;
+
+		sputs("Found Flash at ");
+		print_word((UINT32)flash.pBase);
+		sputs("\n");
+
+		addr = FLASH_OFFSET;
+		sputs("Flash erase at        : ");
+		print_word(addr);
+		sputs("\n");
+		cfi_block_erase(&flash, addr/4);
+
+		while(1)
+		{
+			sputs("BOOT ");
+
+			while(1)
+			{
+				result = srec_getline(buf);
+				result = decode_srec(&srec, buf, result);
+				*pReg = 0;
+				srec.addr += IMAGE_OFFSET;
+				switch (result)
+				{
+					case srec_data:
+						if ((srec.addr + srec.size) > haddr)
+							haddr = srec.addr + srec.size;
+
+						pMem = (UINT8*)srec.addr;
+						for (i=0; i < srec.size; i++)
+							*pMem++ = srec.data[i];
+
+						break;
+
+					case srec_eob:
+						*pReg = 1;
+						print_word(srec.addr);
+						sputs(" to ");
+						print_word(haddr-4);
+						sputs("\n");
+
+						addr = FLASH_OFFSET;
+						sputs("Program Flash at      : ");
+						print_word(addr);
+						sputs("\n");
+						cfi_program_multi(&flash, addr/4, (UINT32*)ram32, TEST_SIZE/4);
+
+	//					Exec_at((void*)srec.addr);
+						break;
+
+					default:
+						break;
+				}
+				if (result == srec_err)
+				{
+					*pReg = 0x40000000;
+					break;
+				}
+
+			};
+		}
+	}
+	return 0;
+}
+

lib/CPUs/MIPS/bsp/examples/bootloader/Makefile

@@ -0,0 +1,40 @@
+ROM_WORDADDR_WIDTH=11
+TOOLS_DIR=../../../tools
+
+CFLAGS=-Os -I. -I../ -msoft-float -march=r3000
+LFLAGS=-M -T bootloader.ld
+LIB_DIRS=-L /usr/local/mipsel-elf/lib -L /usr/local/lib/gcc/mipsel-elf/4.3.2
+LIBS=-lc -lm -lgcc
+
+CC=mipsel-elf-gcc
+LD=mipsel-elf-ld
+OBJDUMP=mipsel-elf-objdump
+OBJCOPY=mipsel-elf-objcopy
+
+all: bootloader_flash
+
+libsys: startup_boot.S init_boot.S kernel_boot.S libsys_boot.c
+	$(CC) $(CFLAGS) -c startup_boot.S -o startup.o
+	$(CC) $(CFLAGS) -c init_boot.S -o init.o
+	$(CC) $(CFLAGS) -c kernel_boot.S -o kernel.o
+	$(CC) $(CFLAGS) -c libsys_boot.c -o libsys.o
+
+bootloader: libsys bootloader.c 
+	$(CC) $(CFLAGS) -g -c bootloader.c
+	$(LD) $(LFLAGS) $(LIB_DIRS) startup.o init.o kernel.o libsys.o bootloader.o -o bootloader.elf $(LIBS) >bootloader.map
+	$(OBJDUMP) -d bootloader.elf > bootloader.dis
+	$(OBJCOPY) bootloader.elf -O binary bootloader.ROM.bin
+	$(OBJCOPY) -O srec bootloader.elf bootloader.srec
+	$(TOOLS_DIR)/romgen bootloader.ROM.bin 10
+
+bootloader_flash: libsys bootloader_with_flash.c 
+	$(CC) $(CFLAGS) -g -c bootloader_with_flash.c
+	$(CC) $(CFLAGS) -g -c ../cfiflash.c
+	$(LD) $(LFLAGS) $(LIB_DIRS) startup.o init.o kernel.o libsys.o cfiflash.o bootloader_with_flash.o -o bootloader.elf $(LIBS) >bootloader.map
+	$(OBJDUMP) -d bootloader.elf > bootloader.dis
+	$(OBJCOPY) bootloader.elf -O binary bootloader.ROM.bin
+	$(OBJCOPY) -O srec bootloader.elf bootloader.srec
+	$(TOOLS_DIR)/romgen bootloader.ROM.bin 11
+
+clean:
+	rm -rf *.o *.bin *.map *.dis *.srec *.elf *.vhd* *.tcl bootloader > /dev/null

lib/CPUs/MIPS/bsp/examples/bootloader/bootloader.c

@@ -0,0 +1,252 @@
+#include "libsys_boot.h"
+
+typedef struct _ssrec_t
+{
+	UINT32 addr;
+	UINT32 size;
+	UINT32 type;
+	UINT8 *data;
+
+} srec_t;
+
+enum srec_type
+{
+	srec_err, srec_sob, srec_data, srec_rec, srec_eob
+};
+
+UINT8 h2i(UINT8 *c)
+{
+	int i;
+	UINT8 t, b = 0;
+
+	for (i=0; i < 2; i++)
+	{
+		t = c[i];
+		if (t >= 'A')
+			t = t - 'A' + 10;
+		else
+			t -= '0';
+
+		b = (b << 4) | t;
+	}
+	return b;
+}
+
+int decode_srec(srec_t *pRec, UINT8 *pBuf, int buflen)
+{
+	UINT8 chksum, byte;
+	int alen, i;
+
+	if (!buflen)
+		return srec_err;
+
+	pRec->type = srec_rec;
+	alen = 0;
+	if ((pBuf[1] > '0') && (pBuf[1] < '4'))
+	{
+	  alen = pBuf[1] - '0' + 1;
+	  pRec->type = srec_data;
+	}
+	else if ((pBuf[1] >= '7') && (pBuf[1] <= '9'))
+	{
+	  alen = 11 - (pBuf[1] - '0');
+	  pRec->type = srec_eob;
+	}
+	else if (pBuf[1] == '0')
+	{
+	  alen = 2;
+	  pRec->type = srec_sob;
+	}
+
+	byte = h2i(&pBuf[2]);
+	pRec->size = byte;
+	chksum = byte;
+
+	pRec->addr = 0;
+	for (i=0; i < alen; i++)
+	{
+		byte = h2i(&pBuf[4+2*i]);
+        pRec->addr = pRec->addr << 8 | byte;
+		chksum += byte;
+	}
+	pRec->size -= (alen+1);
+
+	pRec->data = (UINT8*) &pBuf[4 + 2*alen];
+	for (i=0; i < (int)pRec->size; i++)
+	{
+		byte = h2i(&pRec->data[2*i]);
+		pRec->data[i] = byte;
+		chksum += byte;
+	}
+	chksum = ~chksum;
+	byte = h2i(&pRec->data[2*i]);
+	if (chksum != byte)
+		return 0;
+
+	return pRec->type;
+}
+
+int srec_getline(UINT8 *pLine)
+{
+	char c;
+	int i = 0;
+
+	do
+	{
+		c = readchar();
+
+	} while ((c != 's') && (c != 'S'));
+
+	while(((c != 0x0D) && (c != 0x0A)))
+	{
+		pLine[i++] = c;
+		c = readchar();
+	};
+
+	return i;
+}
+
+void Jump_to(void *pEntry)
+{
+	__asm
+	(
+		".set	noreorder\n"
+	);
+	__asm
+	(
+		"jr		%[pEntry]\n"				// jump entry
+		:
+		: [pEntry] "r" (pEntry)
+	);
+	__asm
+	(
+		"nop\n"
+	);
+	__asm
+	(
+		".set	reorder\n"
+	);
+}
+
+void Exec_at(void *pEntry)
+{
+	__asm
+	(
+		".set	noreorder\n"
+	);
+
+	__asm
+	(
+		"mfc0	$26, $12\n"			// change exception vector
+		"li		$27, 0xFFBFFFFF\n"
+		"and	$26, $27\n"
+		"mtc0	$26, $12\n"
+	);
+
+	__asm
+	(
+		"jr		%[pEntry]\n"				// jump entry
+		:
+		: [pEntry] "r" (pEntry)
+	);
+
+	__asm
+	(
+		"rfe\n"
+	);
+
+	__asm
+	(
+		".set	reorder\n"
+	);
+}
+
+void PrintCPUinfo(void)
+{
+	int result, rev_id;
+
+	char *cpu_type_str[7] = {"invalid", "R2000", "R3000", "R6000", "R4000", "reserved", "R6000A"};
+
+	// Print Status register
+	result = CP0_SR_read();
+
+	sputs("Status  : ");
+	print_word(result);
+	sputs("\n");
+
+	// Print Revision
+	result = CP0_PRID_read();
+	rev_id = (result >> 8) & 0xFF;
+	sputs("CPU type: ");
+	if ((rev_id > 0) && (rev_id < 0x07))
+	{
+		sputs(cpu_type_str[rev_id]);
+		sputs(" Rev.");
+		rev_id = result & 0xFF;
+		print_byte((char)rev_id);
+	}
+	else
+		sputs("Unknown");
+
+	sputs("\n");
+
+}
+
+#define	MAX_IMG_SIZE		(1024*1024)	// bytes
+
+int main(int argc, char *argv[])
+{
+	UINT8 buf[256];
+	srec_t srec;
+	int result, srec_state, i;
+	UINT32 haddr;
+	volatile UINT8 *pMem;
+	haddr = 0;
+
+	// ----------------------------------------------------------
+	sputs("\n\n");
+	PrintCPUinfo();
+	sputs("Booting from UART..");
+
+	while(1)
+	{
+		sputs(".");
+		while(1)
+		{
+			result = srec_getline(buf);
+			srec_state = decode_srec(&srec, buf, result);
+			switch (srec_state)
+			{
+				case srec_data:
+					if ((srec.addr + srec.size) > haddr)
+						haddr = srec.addr + srec.size;
+
+					pMem = (UINT8*)srec.addr;
+					for (i=0; i < srec.size; i++)
+						*pMem++ = srec.data[i];
+
+					break;
+
+				case srec_eob:
+					sputs("done\n\n");
+					sputs("Execute program at ");
+					print_word(srec.addr);
+					sputs("\n\n");
+
+					Exec_at((void*)srec.addr);
+					break;
+
+				default:
+					result = -1;
+					break;
+			}
+			if (result < 0)
+			{
+				break;
+			}
+
+		};
+	}
+	return 0;
+}
+

lib/CPUs/MIPS/bsp/examples/bootloader/bootloader.ld

@@ -0,0 +1,47 @@
+MEMORY
+{
+  rom          : ORIGIN = 0xBFC00000, LENGTH = 0x00002000  /*   8K    */
+  sram         : ORIGIN = 0x40000000, LENGTH = 0x02000000  /*   32M   */
+}
+
+stack_ptr = 0x7FFFFFF0;
+baudrate = 0x0D;
+sys_led_port = 0xA0000000;
+sys_uart_data = 0xA0010000;
+sys_uart_stat = 0xA0010004;
+sys_uart_baud = 0xA0010008;
+sys_timer_usec = 0xA000008;
+sys_timer_sec = 0xA000000C;
+
+
+SECTIONS
+{
+   .stext ORIGIN(rom) :
+   {
+      start = ALIGN(4);
+      entry = ALIGN(4);
+      _entry = ALIGN(4);
+      __entry = ALIGN(4);
+     *(.stext)
+   }  > rom
+   
+   .ktext ORIGIN(rom) + 0x180 :
+   {
+     *(.ktext)
+   }  > rom
+
+   .text . :
+   {
+     *(.text)
+   }  > rom
+
+   .rodata . :
+   {
+     *(.rodata*)
+   }  > rom
+
+   .data ORIGIN(rom) :
+   {
+     *(.data)
+   }  > rom
+}

lib/CPUs/MIPS/bsp/examples/bootloader/bootloader_with_flash.c

@@ -0,0 +1,360 @@
+#include "libsys_boot.h"
+#include "cfiflash.h"
+
+typedef struct _ssrec_t
+{
+	UINT32 addr;
+	UINT32 size;
+	UINT32 type;
+	UINT8 *data;
+
+} srec_t;
+
+typedef struct _sflash_img_hdr_t
+{
+	UINT8 magic[4];
+	UINT32 target_addr;
+	UINT32 img_offset;
+	UINT32 img_size;
+	UINT32 hdr_next;
+	UINT8 img_name[128];
+	UINT8 res[108];
+
+} flash_img_hdr_t;
+
+enum srec_type
+{
+	srec_err, srec_sob, srec_data, srec_rec, srec_eob
+};
+
+UINT8 h2i(UINT8 *c)
+{
+	int i;
+	UINT8 t, b = 0;
+
+	for (i=0; i < 2; i++)
+	{
+		t = c[i];
+		if (t >= 'A')
+			t = t - 'A' + 10;
+		else
+			t -= '0';
+
+		b = (b << 4) | t;
+	}
+	return b;
+}
+
+int decode_srec(srec_t *pRec, UINT8 *pBuf, int buflen)
+{
+	UINT8 chksum, byte;
+	int alen, i;
+
+	if (!buflen)
+		return srec_err;
+
+	pRec->type = srec_rec;
+	alen = 0;
+	if ((pBuf[1] > '0') && (pBuf[1] < '4'))
+	{
+	  alen = pBuf[1] - '0' + 1;
+	  pRec->type = srec_data;
+	}
+	else if ((pBuf[1] >= '7') && (pBuf[1] <= '9'))
+	{
+	  alen = 11 - (pBuf[1] - '0');
+	  pRec->type = srec_eob;
+	}
+	else if (pBuf[1] == '0')
+	{
+	  alen = 2;
+	  pRec->type = srec_sob;
+	}
+
+	byte = h2i(&pBuf[2]);
+	pRec->size = byte;
+	chksum = byte;
+
+	pRec->addr = 0;
+	for (i=0; i < alen; i++)
+	{
+		byte = h2i(&pBuf[4+2*i]);
+        pRec->addr = pRec->addr << 8 | byte;
+		chksum += byte;
+	}
+	pRec->size -= (alen+1);
+
+	pRec->data = (UINT8*) &pBuf[4 + 2*alen];
+	for (i=0; i < (int)pRec->size; i++)
+	{
+		byte = h2i(&pRec->data[2*i]);
+		pRec->data[i] = byte;
+		chksum += byte;
+	}
+	chksum = ~chksum;
+	byte = h2i(&pRec->data[2*i]);
+	if (chksum != byte)
+		return 0;
+
+	return pRec->type;
+}
+
+int srec_getline(UINT8 *pLine)
+{
+	char c;
+	int i = 0;
+
+	do
+	{
+		c = readchar();
+
+	} while ((c != 's') && (c != 'S'));
+
+	while(((c != 0x0D) && (c != 0x0A)))
+	{
+		pLine[i++] = c;
+		c = readchar();
+	};
+
+	return i;
+}
+
+void Jump_to(void *pEntry)
+{
+	__asm
+	(
+		".set	noreorder\n"
+	);
+	__asm
+	(
+		"jr		%[pEntry]\n"				// jump entry
+		:
+		: [pEntry] "r" (pEntry)
+	);
+	__asm
+	(
+		"nop\n"
+	);
+	__asm
+	(
+		".set	reorder\n"
+	);
+}
+
+void Exec_at(void *pEntry)
+{
+	__asm
+	(
+		".set	noreorder\n"
+	);
+
+	__asm
+	(
+		"mfc0	$26, $12\n"			// change exception vector
+		"li		$27, 0xFFBFFFFF\n"
+		"and	$26, $27\n"
+		"mtc0	$26, $12\n"
+	);
+
+	__asm
+	(
+		"jr		%[pEntry]\n"				// jump entry
+		:
+		: [pEntry] "r" (pEntry)
+	);
+
+	__asm
+	(
+		"rfe\n"
+	);
+
+	__asm
+	(
+		".set	reorder\n"
+	);
+}
+
+void PrintCPUinfo(void)
+{
+	int result, rev_id;
+
+	char *cpu_type_str[7] = {"invalid", "R2000", "R3000", "R6000", "R4000", "reserved", "R6000A"};
+
+	// Print Status register
+	result = CP0_SR_read();
+
+	sputs("Status  : ");
+	print_word(result);
+	sputs("\n");
+
+	// Print Revision
+	result = CP0_PRID_read();
+	rev_id = (result >> 8) & 0xFF;
+	sputs("CPU type: ");
+	if ((rev_id > 0) && (rev_id < 0x07))
+	{
+		sputs(cpu_type_str[rev_id]);
+		sputs(" Rev.");
+		rev_id = result & 0xFF;
+		print_byte((char)rev_id);
+	}
+	else
+		sputs("Unknown");
+
+	sputs("\n");
+
+}
+
+#define	MAX_IMG_SIZE		(1024*1024)	// bytes
+#define SDRAM_BASE			0x40000000
+#define	FLASH_OFFSET		0x00000000
+
+int main(int argc, char *argv[])
+{
+	UINT8 buf[256];
+	srec_t srec;
+	int result, srec_state, i;
+	UINT32 haddr;
+	flash_t flash;
+	flash_img_hdr_t img_hdr = {0};
+	flash_img_hdr_t *pImg_hdr;
+	UINT32 img_size;
+
+	volatile UINT32 *pReg = (UINT32*)sys_led_port;
+	volatile UINT32 *pBtn = (UINT32*)sys_gpio0;
+	volatile UINT8 *pMem;
+	volatile UINT32 *pROM32;
+	volatile UINT32 *pMem32;
+	volatile UINT32 *pFlash = (UINT32*)sys_flash_io;
+	volatile UINT32 *pUSB = (UINT32*)sys_usb_data;
+
+	volatile UINT8 *ram8 = (UINT8*)SDRAM_BASE;
+	volatile UINT16 *ram16 = (UINT16*)SDRAM_BASE;
+	volatile UINT32 *ram32 = (UINT32*)SDRAM_BASE;
+
+	*pReg = 0;
+	haddr = 0;
+
+	// ----------------------------------------------------------
+	ram32 = (UINT32*)(SDRAM_BASE);
+	pFlash = (UINT32*)(sys_flash_io + FLASH_OFFSET);
+
+	if (!*pBtn)
+	{
+		sputs("\n\n");
+		sputs("Booting from flash...");
+
+		pImg_hdr = (flash_img_hdr_t*)pFlash;
+		ram32 = (UINT32*)pImg_hdr->target_addr;
+		pFlash = (UINT32*)(sys_flash_io + pImg_hdr->img_offset);
+		img_size = pImg_hdr->img_size;
+
+		for (i=0; i < img_size/4; i++)
+			ram32[i] = pFlash[i];
+
+		sputs("done\n\n");
+
+		Exec_at((void*)ram32);
+	}
+	else
+	{
+
+		if (flash_find(&flash, sys_flash_io) < 0)
+		{
+			sputs("Cannot find flash device. Exit now!\n\n");
+			return 1;
+		}
+
+		// Erase SDRAM
+		for (i=0; i < MAX_IMG_SIZE/4; i++)
+			ram32[i] = 0;
+
+		sputs("\n\n");
+		sputs("Booting from UART..");
+
+		while(1)
+		{
+			sputs(".");
+			while(1)
+			{
+				result = srec_getline(buf);
+				srec_state = decode_srec(&srec, buf, result);
+				*pReg = 0;
+				switch (srec_state)
+				{
+					case srec_data:
+						if ((srec.addr + srec.size) > haddr)
+							haddr = srec.addr + srec.size;
+
+						pMem = (UINT8*)srec.addr;
+						for (i=0; i < srec.size; i++)
+							*pMem++ = srec.data[i];
+
+						break;
+
+					case srec_eob:
+						sputs("done\n\n");
+
+						img_hdr.magic[0] = 'J';
+						img_hdr.magic[1] = 'F';
+						img_hdr.magic[2] = 'I';
+						img_hdr.magic[3] = '1';
+						img_hdr.target_addr = srec.addr;
+						img_hdr.img_size = haddr - srec.addr;
+						img_hdr.img_offset = FLASH_OFFSET + sizeof(flash_img_hdr_t);
+						img_hdr.hdr_next = FLASH_OFFSET;
+
+						sputs("Flash erase...");
+						result = flash_erase(&flash, FLASH_OFFSET, img_hdr.img_size + sizeof(flash_img_hdr_t));
+						if (result < 0)
+						{
+							sputs("failed!\n");
+							break;
+						}
+						sputs("done\n");
+
+						sputs("Flash write...");
+						result = flash_program(&flash, FLASH_OFFSET, (UINT8*)&img_hdr, sizeof(flash_img_hdr_t));
+						if (result < 0)
+						{
+							sputs("failed!\n");
+							break;
+						}
+						result = flash_program(&flash, img_hdr.img_offset, (UINT8*)ram32, img_hdr.img_size);
+						if (result < 0)
+						{
+							sputs("failed!\n");
+							break;
+						}
+						sputs("done\n");
+
+						sputs("Flash verify...");
+						result = flash_verify(&flash, img_hdr.img_offset, (UINT8*)ram32, img_hdr.img_size);
+						if (result < 0)
+						{
+							sputs("failed!\n");
+							break;
+						}
+						sputs("passed\n");
+						Jump_to((void*)0xBFC00000);
+//						sputs("\nPush reset button to boot!\n");
+//						*pReg = 1;
+
+						break;
+
+					default:
+						result = -1;
+						break;
+				}
+				if (result < 0)
+				{
+					*pReg = 0x40000000;
+					break;
+				}
+
+			};
+		}
+	}
+	return 0;
+}
+

lib/CPUs/MIPS/bsp/examples/bootloader/init_boot.S

@@ -0,0 +1,208 @@
+		.file	"init.S"
+	
+		.text
+		.align	2
+		.globl _init
+		.extern end
+	
+_init:
+		.set	noreorder
+
+		# set uart
+		la	$26, sys_uart_baud
+		addiu	$27, $0, baudrate
+		sb	$27, 0($26)
+
+		# set stack pointer 
+		la $sp, stack_ptr
+#		j	$jmain
+		
+		# TEST
+		li	$26, +5
+		beqz	$26, _terminate	
+		li	$26, -5
+		beqz	$26, _terminate	
+		li	$26, 0
+		beqz	$26, $_L11
+		nop
+		j	_terminate
+		nop
+$_L11:		
+		li	$26, +5
+		li	$27, +6
+		beq	$26, $27, _terminate	
+		li	$26, -5
+		beq	$26, $27, _terminate	
+		li	$26, 0
+		beq	$26, $27, _terminate	
+		li	$26, +6
+		beq	$26, $27, $_L12
+		nop
+		j	_terminate
+		nop
+$_L12:			
+		li	$26, -5
+		bgez	$26, _terminate	
+		li	$26, +5
+		bgez	$26, $_L13
+		nop
+		j	_terminate
+$_L13:		li	$26, 0
+		bgez	$26, $_L14
+		nop
+		j	_terminate
+$_L14:		
+		li	$26, -5
+		bgtz	$26, _terminate	
+		li	$26, 0
+		bgtz	$26, _terminate	
+		li	$26, +5
+		bgtz	$26, $_L15
+		nop
+		j	_terminate
+		
+$_L15:			
+		li	$26, +5
+		blez	$26, _terminate	
+		li	$26, 0
+		blez	$26, $_L16
+		nop
+		j	_terminate
+$_L16:		li	$26, -5
+		blez	$26, $_L17
+		nop
+		j	_terminate
+			
+$_L17:			
+		li	$26, +5
+		bltz	$26, _terminate	
+		li	$26, 0
+		bltz	$26, _terminate	
+		li	$26, -5
+		bltz	$26, $_L18
+		nop
+		j	_terminate
+$_L18:			
+		li	$26, +5
+		li	$27, +6
+		bne	$26, $27, $_L19
+		nop
+		j	_terminate
+$_L19:		li	$26, -5
+		bne	$26, $27, $_L20
+		nop
+		j	_terminate
+$_L20:		li	$26, -6
+		bne	$26, $27, $_L21
+		nop
+		j	_terminate
+$_L21:		li	$26, 0
+		bne	$26, $27, $_L22
+		nop
+		j	_terminate
+$_L22:		li	$26, +6
+		bne	$26, $27, _terminate
+		li	$26, +5
+		bnez	$26, $_L23
+		nop
+		j	_terminate
+$_L23:		li	$26, -5
+		bnez	$26, $_L24
+		nop
+		j	_terminate
+$_L24:		li	$26, 0
+		bnez	$26, _terminate
+
+$_L25:
+		li	$27, +5
+		sltiu	$26,$27,+6
+		sltiu	$26,$27,-6
+		li	$27, -5
+		sltiu	$26,$27,+6
+		sltiu	$26,$27,-6
+		li	$27, +6
+		sltiu	$26,$27,+5
+		sltiu	$26,$27,-5
+		li	$27, -6
+		sltiu	$26,$27,+5
+		sltiu	$26,$27,-5
+
+		li	$27, +5
+		slti	$26,$27,+6
+		slti	$26,$27,-6
+		li	$27, -5
+		slti	$26,$27,+6
+		slti	$26,$27,-6
+		li	$27, +6
+		slti	$26,$27,+5
+		slti	$26,$27,-5
+		li	$27, -6
+		slti	$26,$27,+5
+		slti	$26,$27,-5
+
+		
+		li	$26, +5
+		li	$27, +6
+		sltu	$26,$26,$27
+		li	$26, +5
+		li	$27, -6
+		sltu	$26,$26,$27
+		li	$26, -5
+		li	$27, +6
+		sltu	$26,$26,$27
+		li	$26, -5
+		li	$27, -6
+		sltu	$26,$26,$27
+
+		li	$26, +6
+		li	$27, +5
+		sltu	$26,$26,$27
+		li	$26, +6
+		li	$27, -5
+		sltu	$26,$26,$27
+		li	$26, -6
+		li	$27, +5
+		sltu	$26,$26,$27
+		li	$26, -6
+		li	$27, -5
+		sltu	$26,$26,$27
+
+		li	$26, +5
+		li	$27, +6
+		slt	$26,$26,$27
+		li	$26, +5
+		li	$27, -6
+		slt	$26,$26,$27
+		li	$26, -5
+		li	$27, +6
+		slt	$26,$26,$27
+		li	$26, -5
+		li	$27, -6
+		slt	$26,$26,$27
+
+		li	$26, +6
+		li	$27, +5
+		slt	$26,$26,$27
+		li	$26, +6
+		li	$27, -5
+		slt	$26,$26,$27
+		li	$26, -6
+		li	$27, +5
+		slt	$26,$26,$27
+		li	$26, -6
+		li	$27, -5
+		slt	$26,$26,$27
+
+		# TEST
+		
+		
+		# jump main
+$jmain:		la $26, main
+		jalr $26
+
+_terminate:
+		nop
+		j		_terminate
+		nop
+		
+		.set	reorder

lib/CPUs/MIPS/bsp/examples/bootloader/kernel_boot.S

@@ -0,0 +1,45 @@
+		.file	"kernel.S"
+
+		.section .ktext,"ax"
+		.align	2
+
+		.macro kpush reg
+		addiu	$sp, 4
+		sw		\reg, 0($sp)
+		.endm
+		
+		.macro kpop reg
+		lw		\reg, 0($sp)
+		addiu	$sp, -4
+		.endm
+
+_exc_handler:
+
+		.set	noreorder
+		
+		# Set Error LED and ExcCode LEDs
+		# Get Cause
+		mfc0	$26, $13
+		la 		$27, sys_led_port
+		srl		$26, 2
+		andi	$26, 0x000F
+		or 		$26, $27
+		sw 		$26, 0($27)
+
+		# wait for all interrupts = 0
+$w4x:	mfc0	$26, $13
+		nop
+		srl		$26, 8
+		andi	$26, 0xFF
+		bnez	$26, $w4x
+		nop
+		
+		# Get return address
+		mfc0	$26, $14
+
+		# Return
+		nop
+		jr	$26
+		rfe
+		.set	reorder
+	

lib/CPUs/MIPS/bsp/examples/bootloader/libsys_boot.c

@@ -0,0 +1,142 @@
+#include <sys/times.h>
+#include <sys/time.h>
+#include <sys/resource.h>
+#include <sys/stat.h>
+#include <errno.h>
+#include <stdlib.h>
+#include "libsys_boot.h"
+
+// ---------------------------------------------------------------------------------
+// MIPS specific
+UINT32 CP0_SR_read(void)
+{
+	UINT32 result;
+
+	__asm
+	(
+		"mfc0   %[val], $12\n"
+		: [val] "=r" (result)
+	);
+
+	return result;
+}
+
+void CP0_SR_write(UINT32 val)
+{
+	__asm
+	(
+		"mtc0   %[val], $12\n"
+		: /* no output */
+		: [val] "r" (val)
+	);
+}
+
+UINT32 CP0_CR_read(void)
+{
+	UINT32 result;
+
+	__asm
+	(
+		"mfc0   %[val], $13\n"
+		: [val] "=r" (result)
+	);
+
+	return result;
+}
+
+void CP0_CR_write(UINT32 val)
+{
+	__asm
+	(
+		"mtc0   %[val], $13\n"
+		:
+		: [val] "r" (val)
+	);
+}
+
+UINT32 CP0_PRID_read(void)
+{
+	UINT32 result;
+
+	__asm
+	(
+		"mfc0   %[val], $15\n"
+		: [val] "=r" (result)
+	);
+
+	return result;
+}
+
+// ---------------------------------------------------------------------------------
+char readchar(void)
+{
+	volatile UINT32 *pUART_stat = (UINT32*)sys_uart_stat;
+	volatile UINT32 *pUART_data = (UINT32*)sys_uart_data;
+
+	while(!(0x10 & *pUART_stat));
+
+	return (char)*pUART_data;
+}
+
+void writechar(char c)
+{
+	volatile UINT32 *pUART_stat = (UINT32*)sys_uart_stat;
+	volatile UINT32 *pUART_data = (UINT32*)sys_uart_data;
+
+	while((0x02 & *pUART_stat) != 0);
+
+	*pUART_data = (UINT32)c;
+}
+
+void _putchar(char c)
+{
+	if (c == 0x0A)
+	{
+		writechar(0x0D);
+	}
+	writechar(c);
+}
+
+int sputs(char *pStr)
+{
+	char *start;
+	start = pStr;
+
+	while(*pStr)
+		_putchar(*(pStr++));
+
+	return pStr - start;
+}
+
+void print_byte(char byte)
+{
+	int i;
+	unsigned char c, nibble;
+
+	for (i=0; i < 2; i++)
+	{
+		nibble = (char)((byte >> 4) & 0xF);
+		byte <<= 4;
+
+		if (nibble < 10)
+			c = nibble + '0';
+		else
+			c = nibble + 'A' - 10;
+
+		_putchar(c);
+	}
+}
+
+void print_word(int word)
+{
+	int i;
+	unsigned char c, nibble;
+
+	for (i=0; i < 4; i++)
+	{
+		c = (char) (word >> 24);
+		print_byte(c);
+		word <<= 8;
+	}
+}
+

lib/CPUs/MIPS/bsp/examples/bootloader/libsys_boot.h

@@ -0,0 +1,50 @@
+#ifndef LIBSYS_H
+#define LIBSYS_H
+
+// ---------------------------------------------------------
+// Types
+// ---------------------------------------------------------
+#define INT8    char
+#define INT16   short
+#define INT32   long
+#define UINT8   unsigned char
+#define UINT16  unsigned short
+#define UINT32  unsigned long
+#define INT     int
+#define UINT    unsigned int
+#define FLOAT32 float
+#define FLOAT64 double
+
+
+#define	sys_gpio0		0xA0000000
+#define	sys_gpio1		0xA0000004
+#define	sys_led_port	sys_gpio0
+#define	sys_usb_ctrl	sys_gpio1
+#define	sys_timer_usec	0xA0000008
+#define	sys_timer_sec	0xA000000C
+#define	sys_uart_data	0xA0010000
+#define	sys_uart_stat	0xA0010004
+#define	sys_uart_baud	0xA0010008
+#define	sys_usb_data	0xA0020000
+#define	sys_usb_mbx		0xA0020004
+#define	sys_usb_addr	0xA0020008
+#define	sys_usb_status	0xA002000C
+#define	sys_flash_io	0xA4000000
+
+// MIPS specific
+UINT32 CP0_SR_read(void);
+void CP0_SR_write(UINT32 val);
+UINT32 CP0_CR_read(void);
+void CP0_CR_write(UINT32 val);
+UINT32 CP0_PRID_read(void);
+
+// General
+char readchar(void);
+void writechar(char c);
+int write(int file, char *ptr, int len);
+int sputs(char *pStr);
+void print_byte(char byte);
+void print_word(int word);
+
+#endif // LIBSYS_H
+

lib/CPUs/MIPS/bsp/examples/bootloader/startup_boot.S

@@ -0,0 +1,25 @@
+		.file	"startup.S"
+	
+		.section .stext,"ax"
+		.extern _init
+		.align	2
+	
+_start:
+		.set	noreorder
+
+		# Set Kernel mode
+		li		$26, 0x1040000C
+		mtc0	$26, $12
+		li		$26, 0x00000000
+		mtc0	$26, $13
+
+		mfc0	$26, $15
+		nop
+		mtc0	$26, $31
+
+		# jump init
+		la $26, _init
+		jr $26
+		nop
+	
+		.set	reorder

lib/CPUs/MIPS/bsp/examples/cfiflash.c

@@ -0,0 +1,253 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include "libsys.h"
+#include "cfiflash.h"
+
+UINT32 cfi_get_status(flash_t *pObj)
+{
+	volatile UINT32 *pF;
+	UINT32 status;
+
+	pF = (UINT32*)pObj->pBase;
+
+	*pF = 0x00700070;
+
+	status = *pF;
+
+	*pF = 0x00FF00FF;
+
+	return status;
+
+}
+
+void cfi_init(flash_t *pObj, UINT32 base_addr)
+{
+	int i;
+	UINT8 *pInfo;
+
+	pObj->pBase = (void*)base_addr;
+
+	pInfo = (UINT8*)&pObj->info;
+	for (i=0; i < sizeof(flash_info_t); i++)
+	{
+		pInfo[i] = 0;
+	}
+}
+
+UINT32 cfi_find(flash_t *pObj)
+{
+	int i;
+	volatile UINT32 *pF;
+	volatile UINT16 *pF16;
+	UINT8 qry_ref[12] = {0x51, 0x00, 0x51, 0x00, 0x52, 0x00, 0x52, 0x00, 0x59, 0x00, 0x59, 0x00};
+	UINT32 size;
+
+	pF = (UINT32*)pObj->pBase;
+	pF16 = (UINT16*)pObj->pBase;
+
+	// Look for flash
+	*pF = 0x00980098;
+	for (i=0; i < sizeof(qry_ref); i++)
+		if (((UINT8*)(&pF[0x10]))[i] != qry_ref[i])
+			return (UINT32)-1;
+
+	*pF = 0x00FF00FF;
+	*pF = 0x00900090;
+
+/*
+	printf("ManID             : %8.8X\n", (UINT32)pF[0]);
+	printf("Device code       : %8.8X\n", (UINT32)pF[1]);
+	printf("Block info        : %8.8X\n", (UINT32)pF[2]);
+
+	printf("VCC(min)          : %8.8X\n", (UINT32)pF[0x1B]);
+	printf("VCC(max)          : %8.8X\n", (UINT32)pF[0x1C]);
+	printf("VPP(min)          : %8.8X\n", (UINT32)pF[0x1D]);
+	printf("VPP(max)          : %8.8X\n", (UINT32)pF[0x1E]);
+	printf("Device Layout     : %8.8X\n", (UINT32)pF[0x27]);
+	printf("Interface type    : %8.8X %8.8X\n", (UINT32)pF[0x28], (UINT32)pF[0x29]);
+	printf("Write buffer size : %8.8X %8.8X\n", (UINT32)pF[0x2A], (UINT32)pF[0x2B]);
+	printf("Num. erase blocks : %8.8X\n", (UINT32)pF[0x2C]);
+	printf("Erase block info  : %8.8X %8.8X %8.8X %8.8X\n", (UINT32)pF[0x2D], (UINT32)pF[0x2E], (UINT32)pF[0x2F], (UINT32)pF[0x30]);
+*/
+	pObj->info.num_flash = 2;
+	pObj->info.if_width = 32;
+	size = (UINT32)pF16[2*0x27];
+	pObj->info.flashsize = pObj->info.num_flash;
+	for (i=0; i < size; i++)
+		pObj->info.flashsize *= 2;
+
+	size = (UINT32)(pF16[2*0x2B] << 8 | pF16[2*0x2A]);
+	pObj->info.wbuf_size = pObj->info.num_flash;
+	for (i=0; i < size; i++)
+		pObj->info.wbuf_size *= 2;
+
+	pObj->info.nblocks = pObj->info.num_flash * ((UINT32)(pF16[2*0x2E] << 8 | pF16[2*0x2D]) + 1);
+	pObj->info.blocksize = pObj->info.num_flash * ((UINT32)(pF16[2*0x30] << 8 | pF16[2*0x2F]) * 256);
+
+	*pF = 0x00FF00FF;
+
+	return 0;
+}
+
+UINT32 cfi_block_erase(flash_t *pObj, UINT32 word_index)
+{
+	volatile UINT32 *pF;
+	UINT32 status, block_index, block_mask;
+
+	pF = (UINT32*)pObj->pBase;
+
+	if (word_index >= (pObj->info.flashsize/4))
+		return -1;
+
+	block_mask = ((pObj->info.nblocks-1) << 16);
+	block_index = word_index & block_mask;
+
+	pF[block_index] = 0x00200020;
+	pF[block_index] = 0x00D000D0;
+
+	do
+	{
+		status = pF[block_index];
+
+	} while((status & SR_BIT_ISMS) != SR_BIT_ISMS);
+
+	pF[block_index] = 0x00FF00FF;
+
+	return 0;
+}
+
+UINT32 cfi_program_single(flash_t *pObj, UINT32 word_index, UINT32 word)
+{
+	volatile UINT32 *pF;
+	UINT32 status;
+
+	pF = (UINT32*)pObj->pBase;
+
+	if (word_index >= (pObj->info.flashsize/4))
+		return -1;
+
+	pF[word_index] = 0x00400040;
+	pF[word_index] = word;
+
+	do
+	{
+		status = pF[word_index];
+
+	} while((status & SR_BIT_ISMS) != SR_BIT_ISMS);
+
+	pF[word_index] = 0x00FF00FF;
+
+	return 0;
+
+}
+
+UINT32 cfi_program_multi(flash_t *pObj, UINT32 word_index, UINT32 *pWords, UINT32 num_words)
+{
+	int i, j, k;
+	volatile UINT32 *pF;
+	UINT32 status, bcurr, bnext, block_mask, nblock_write, nbuf_write;
+
+	pF = (UINT32*)pObj->pBase;
+
+	if (word_index >= (pObj->info.flashsize/4))
+		return -1;
+
+	block_mask = ((pObj->info.nblocks-1) << 16);
+
+	k = 0;
+	while(num_words)
+	{
+
+		bcurr = word_index & block_mask;
+		bnext = bcurr + (1 << 16);
+		nblock_write = bnext - word_index;
+		if (nblock_write > num_words)
+			nblock_write = num_words;
+
+//		printf("bcurr        : %8.8X\n", bcurr);
+//		printf("bnext        : %8.8X\n", bnext);
+//		printf("windex       : %8.8X\n", word_index);
+//		printf("num_words    : %d\n", num_words);
+//		printf("nblock_write : %d\n", nblock_write);
+
+		while(nblock_write)
+		{
+			pF[bcurr] = 0x00E800E8;
+			do
+			{
+				status = pF[bcurr];
+//				printf("status       : %8.8X\n", status);
+
+			} while((status & SR_BIT_ISMS) != SR_BIT_ISMS);
+
+			nbuf_write = nblock_write;
+			if (nblock_write > pObj->info.wbuf_size/4)
+				nbuf_write = pObj->info.wbuf_size/4;
+
+//			printf("nbuf_write   : %d\n", nbuf_write);
+
+			pF[bcurr] = (nbuf_write-1) << 16 | (nbuf_write-1);
+
+			for (j=0; j < nbuf_write; j++)
+				pF[word_index+j] = pWords[k++];
+
+			word_index += j;
+			nblock_write -= j;
+			num_words -= j;
+
+			pF[bcurr] = 0x00D000D0;
+			do
+			{
+				status = pF[bcurr];
+//				printf("status       : %8.8X\n", status);
+
+			} while((status & SR_BIT_ISMS) != SR_BIT_ISMS);
+
+			pF[bcurr] = 0x00FF00FF;
+		}
+		bcurr = bnext;
+	}
+
+	return 0;
+
+}
+
+UINT32 flash_find(flash_t *pObj, UINT32 base_addr)
+{
+	cfi_init(pObj, base_addr);
+	return cfi_find(pObj);
+}
+
+UINT32 flash_erase(flash_t *pObj, UINT32 offset, UINT32 size)
+{
+	int i;
+	UINT32 offset_end;
+
+	offset_end = offset + size;
+
+	for (i=offset; i < offset_end; i += pObj->info.blocksize)
+		if (cfi_block_erase(pObj, i/4) < 0)
+			return -1;
+
+	return 0;
+
+}
+
+UINT32 flash_program(flash_t *pObj, UINT32 offset, UINT8 *pData, UINT32 size)
+{
+	return cfi_program_multi(pObj, offset/4, (UINT32*)pData, size/4);
+}
+
+UINT32 flash_verify(flash_t *pObj, UINT32 offset, UINT8 *pData, UINT32 size)
+{
+	int i;
+	UINT8 *pF;
+
+	pF = (UINT8*)(pObj->pBase + offset);
+
+	for (i=0; i < size; i++)
+		if (pF[i] != pData[i])
+			return -1;
+
+	return 0;
+}

lib/CPUs/MIPS/bsp/examples/cfiflash.h

@@ -0,0 +1,44 @@
+/************************************************************************/
+#ifndef CFIFLASH_H
+#define CFIFLASH_H
+
+#include "libsys.h"
+
+#define	SR_BIT_DPS		0x00020002
+#define	SR_BIT_PSS		0x00040004
+#define	SR_BIT_VPENS	0x00080008
+#define	SR_BIT_PSLBS	0x00100010
+#define	SR_BIT_ECLBS	0x00200020
+#define	SR_BIT_ESS		0x00400040
+#define	SR_BIT_ISMS		0x00800080
+
+typedef struct _sflash_info_t
+{
+	UINT32 flashsize;
+	UINT32 blocksize;
+	UINT32 nblocks;
+	UINT32 wbuf_size;
+	UINT32 if_width;
+	UINT32 num_flash;
+
+} flash_info_t;
+
+typedef struct _sflash_t
+{
+	void *pBase;
+	flash_info_t info;
+
+} flash_t;
+
+void cfi_init(flash_t *pObj, UINT32 base_addr);
+UINT32 cfi_find(flash_t *pObj);
+UINT32 cfi_block_erase(flash_t *pObj, UINT32 word_index);
+UINT32 cfi_program_single(flash_t *pObj, UINT32 word_index, UINT32 word);
+UINT32 cfi_program_multi(flash_t *pObj, UINT32 word_index, UINT32 *pWords, UINT32 num_words);
+
+UINT32 flash_find(flash_t *pObj, UINT32 base_addr);
+UINT32 flash_erase(flash_t *pObj, UINT32 offset, UINT32 size);
+UINT32 flash_program(flash_t *pObj, UINT32 offset, UINT8 *pData, UINT32 size);
+UINT32 flash_verify(flash_t *pObj, UINT32 offset, UINT8 *pData, UINT32 size);
+
+#endif // CFIFLASH_H

lib/CPUs/MIPS/bsp/examples/dhry.h

@@ -0,0 +1,430 @@
+/*
+ ****************************************************************************
+ *
+ *                   "DHRYSTONE" Benchmark Program
+ *                   -----------------------------
+ *                                                                            
+ *  Version:    C, Version 2.1
+ *                                                                            
+ *  File:       dhry.h (part 1 of 3)
+ *
+ *  Date:       May 25, 1988
+ *
+ *  Author:     Reinhold P. Weicker
+ *                      Siemens AG, E STE 35
+ *                      Postfach 3240
+ *                      8520 Erlangen
+ *                      Germany (West)
+ *                              Phone:  [xxx-49]-9131-7-20330
+ *                                      (8-17 Central European Time)
+ *                              Usenet: ..!mcvax!unido!estevax!weicker
+ *
+ *              Original Version (in Ada) published in
+ *              "Communications of the ACM" vol. 27., no. 10 (Oct. 1984),
+ *              pp. 1013 - 1030, together with the statistics
+ *              on which the distribution of statements etc. is based.
+ *
+ *              In this C version, the following C library functions are used:
+ *              - strcpy, strcmp (inside the measurement loop)
+ *              - printf, scanf (outside the measurement loop)
+ *              In addition, Berkeley UNIX system calls "times ()" or "time ()"
+ *              are used for execution time measurement. For measurements
+ *              on other systems, these calls have to be changed.
+ *
+ *  Collection of Results:
+ *              Reinhold Weicker (address see above) and
+ *              
+ *              Rick Richardson
+ *              PC Research. Inc.
+ *              94 Apple Orchard Drive
+ *              Tinton Falls, NJ 07724
+ *                      Phone:  (201) 389-8963 (9-17 EST)               
+ *                      Usenet: ...!uunet!pcrat!rick
+ *
+ *      Please send results to Rick Richardson and/or Reinhold Weicker.
+ *      Complete information should be given on hardware and software used.
+ *      Hardware information includes: Machine type, CPU, type and size
+ *      of caches; for microprocessors: clock frequency, memory speed
+ *      (number of wait states).
+ *      Software information includes: Compiler (and runtime library)
+ *      manufacturer and version, compilation switches, OS version.
+ *      The Operating System version may give an indication about the
+ *      compiler; Dhrystone itself performs no OS calls in the measurement loop.
+ *
+ *      The complete output generated by the program should be mailed
+ *      such that at least some checks for correctness can be made.
+ *
+ ***************************************************************************
+ *
+ *  History:    This version C/2.1 has been made for two reasons:
+ *
+ *              1) There is an obvious need for a common C version of
+ *              Dhrystone, since C is at present the most popular system
+ *              programming language for the class of processors
+ *              (microcomputers, minicomputers) where Dhrystone is used most.
+ *              There should be, as far as possible, only one C version of
+ *              Dhrystone such that results can be compared without
+ *              restrictions. In the past, the C versions distributed
+ *              by Rick Richardson (Version 1.1) and by Reinhold Weicker
+ *              had small (though not significant) differences.
+ *
+ *              2) As far as it is possible without changes to the Dhrystone
+ *              statistics, optimizing compilers should be prevented from
+ *              removing significant statements.
+ *
+ *              This C version has been developed in cooperation with
+ *              Rick Richardson (Tinton Falls, NJ), it incorporates many
+ *              ideas from the "Version 1.1" distributed previously by
+ *              him over the UNIX network Usenet.
+ *              I also thank Chaim Benedelac (National Semiconductor),
+ *              David Ditzel (SUN), Earl Killian and John Mashey (MIPS),
+ *              Alan Smith and Rafael Saavedra-Barrera (UC at Berkeley)
+ *              for their help with comments on earlier versions of the
+ *              benchmark.
+ *
+ *  Changes:    In the initialization part, this version follows mostly
+ *              Rick Richardson's version distributed via Usenet, not the
+ *              version distributed earlier via floppy disk by Reinhold Weicker.
+ *              As a concession to older compilers, names have been made
+ *              unique within the first 8 characters.
+ *              Inside the measurement loop, this version follows the
+ *              version previously distributed by Reinhold Weicker.
+ *
+ *              At several places in the benchmark, code has been added,
+ *              but within the measurement loop only in branches that 
+ *              are not executed. The intention is that optimizing compilers
+ *              should be prevented from moving code out of the measurement
+ *              loop, or from removing code altogether. Since the statements
+ *              that are executed within the measurement loop have NOT been
+ *              changed, the numbers defining the "Dhrystone distribution"
+ *              (distribution of statements, operand types and locality)
+ *              still hold. Except for sophisticated optimizing compilers,
+ *              execution times for this version should be the same as
+ *              for previous versions.
+ *              
+ *              Since it has proven difficult to subtract the time for the
+ *              measurement loop overhead in a correct way, the loop check
+ *              has been made a part of the benchmark. This does have
+ *              an impact - though a very minor one - on the distribution
+ *              statistics which have been updated for this version.
+ *
+ *              All changes within the measurement loop are described
+ *              and discussed in the companion paper "Rationale for
+ *              Dhrystone version 2".
+ *
+ *              Because of the self-imposed limitation that the order and
+ *              distribution of the executed statements should not be
+ *              changed, there are still cases where optimizing compilers
+ *              may not generate code for some statements. To a certain
+ *              degree, this is unavoidable for small synthetic benchmarks.
+ *              Users of the benchmark are advised to check code listings
+ *              whether code is generated for all statements of Dhrystone.
+ *
+ *              Version 2.1 is identical to version 2.0 distributed via
+ *              the UNIX network Usenet in March 1988 except that it corrects
+ *              some minor deficiencies that were found by users of version 2.0.
+ *              The only change within the measurement loop is that a
+ *              non-executed "else" part was added to the "if" statement in
+ *              Func_3, and a non-executed "else" part removed from Proc_3.
+ *
+ ***************************************************************************
+ *
+ * Defines:     The following "Defines" are possible:
+ *              -DREG=register          (default: Not defined)
+ *                      As an approximation to what an average C programmer
+ *                      might do, the "register" storage class is applied
+ *                      (if enabled by -DREG=register)
+ *                      - for local variables, if they are used (dynamically)
+ *                        five or more times
+ *                      - for parameters if they are used (dynamically)
+ *                        six or more times
+ *                      Note that an optimal "register" strategy is
+ *                      compiler-dependent, and that "register" declarations
+ *                      do not necessarily lead to faster execution.
+ *              -DNOSTRUCTASSIGN        (default: Not defined)
+ *                      Define if the C compiler does not support
+ *                      assignment of structures.
+ *              -DNOENUMS               (default: Not defined)
+ *                      Define if the C compiler does not support
+ *                      enumeration types.
+ *              -DTIMES                 (default)
+ *              -DTIME
+ *                      The "times" function of UNIX (returning process times)
+ *                      or the "time" function (returning wallclock time)
+ *                      is used for measurement. 
+ *                      For single user machines, "time ()" is adequate. For
+ *                      multi-user machines where you cannot get single-user
+ *                      access, use the "times ()" function. If you have
+ *                      neither, use a stopwatch in the dead of night.
+ *                      "printf"s are provided marking the points "Start Timer"
+ *                      and "Stop Timer". DO NOT use the UNIX "time(1)"
+ *                      command, as this will measure the total time to
+ *                      run this program, which will (erroneously) include
+ *                      the time to allocate storage (malloc) and to perform
+ *                      the initialization.
+ *              -DHZ=nnn
+ *                      In Berkeley UNIX, the function "times" returns process
+ *                      time in 1/HZ seconds, with HZ = 60 for most systems.
+ *                      CHECK YOUR SYSTEM DESCRIPTION BEFORE YOU JUST APPLY
+ *                      A VALUE.
+ *
+ ***************************************************************************
+ *
+ *  Compilation model and measurement (IMPORTANT):
+ *
+ *  This C version of Dhrystone consists of three files:
+ *  - dhry.h (this file, containing global definitions and comments)
+ *  - dhry_1.c (containing the code corresponding to Ada package Pack_1)
+ *  - dhry_2.c (containing the code corresponding to Ada package Pack_2)
+ *
+ *  The following "ground rules" apply for measurements:
+ *  - Separate compilation
+ *  - No procedure merging
+ *  - Otherwise, compiler optimizations are allowed but should be indicated
+ *  - Default results are those without register declarations
+ *  See the companion paper "Rationale for Dhrystone Version 2" for a more
+ *  detailed discussion of these ground rules.
+ *
+ *  For 16-Bit processors (e.g. 80186, 80286), times for all compilation
+ *  models ("small", "medium", "large" etc.) should be given if possible,
+ *  together with a definition of these models for the compiler system used.
+ *
+ **************************************************************************
+ *
+ *  Dhrystone (C version) statistics:
+ *
+ *  [Comment from the first distribution, updated for version 2.
+ *   Note that because of language differences, the numbers are slightly
+ *   different from the Ada version.]
+ *
+ *  The following program contains statements of a high level programming
+ *  language (here: C) in a distribution considered representative:           
+ *
+ *    assignments                  52 (51.0 %)
+ *    control statements           33 (32.4 %)
+ *    procedure, function calls    17 (16.7 %)
+ *
+ *  103 statements are dynamically executed. The program is balanced with
+ *  respect to the three aspects:                                             
+ *
+ *    - statement type
+ *    - operand type
+ *    - operand locality
+ *         operand global, local, parameter, or constant.                     
+ *
+ *  The combination of these three aspects is balanced only approximately.    
+ *
+ *  1. Statement Type:                                                        
+ *  -----------------             number
+ *
+ *     V1 = V2                     9
+ *       (incl. V1 = F(..)
+ *     V = Constant               12
+ *     Assignment,                 7
+ *       with array element
+ *     Assignment,                 6
+ *       with record component
+ *                                --
+ *                                34       34
+ *
+ *     X = Y +|-|"&&"|"|" Z        5
+ *     X = Y +|-|"==" Constant     6
+ *     X = X +|- 1                 3
+ *     X = Y *|/ Z                 2
+ *     X = Expression,             1
+ *           two operators
+ *     X = Expression,             1
+ *           three operators
+ *                                --
+ *                                18       18
+ *
+ *     if ....                    14
+ *       with "else"      7
+ *       without "else"   7
+ *           executed        3
+ *           not executed    4
+ *     for ...                     7  |  counted every time
+ *     while ...                   4  |  the loop condition
+ *     do ... while                1  |  is evaluated
+ *     switch ...                  1
+ *     break                       1
+ *     declaration with            1
+ *       initialization
+ *                                --
+ *                                34       34
+ *
+ *     P (...)  procedure call    11
+ *       user procedure      10
+ *       library procedure    1
+ *     X = F (...)
+ *             function  call      6
+ *       user function        5                                         
+ *       library function     1                                               
+ *                                --                                          
+ *                                17       17
+ *                                        ---
+ *                                        103
+ *
+ *    The average number of parameters in procedure or function calls
+ *    is 1.82 (not counting the function values aX *
+ *
+ *  2. Operators
+ *  ------------
+ *                          number    approximate
+ *                                    percentage
+ *
+ *    Arithmetic             32          50.8                                 
+ *
+ *       +                     21          33.3                              
+ *       -                      7          11.1                              
+ *       *                      3           4.8
+ *       / (int div)            1           1.6
+ *
+ *    Comparison             27           42.8
+ *
+ *       ==                     9           14.3
+ *       /=                     4            6.3
+ *       >                      1            1.6
+ *       <                      3            4.8
+ *       >=                     1            1.6
+ *       <=                     9           14.3
+ *
+ *    Logic                   4            6.3
+ *
+ *       && (AND-THEN)          1            1.6
+ *       |  (OR)                1            1.6
+ *       !  (NOT)               2            3.2
+ * 
+ *                           --          -----
+ *                           63          100.1
+ *
+ *
+ *  3. Operand Type (counted once per operand reference):
+ *  ---------------
+ *                          number    approximate
+ *                                    percentage
+ *
+ *     Integer               175        72.3 %
+ *     Character              45        18.6 %
+ *     Pointer                12         5.0 %
+ *     String30                6         2.5 %
+ *     Array                   2         0.8 %
+ *     Record                  2         0.8 %
+ *                           ---       -------
+ *                           242       100.0 %
+ *
+ *  When there is an access path leading to the final operand (e.g. a record
+ *  component), only the final data type on the access path is counted.       
+ *
+ *
+ *  4. Operand Locality:                                                      
+ *  -------------------
+ *                                number    approximate
+ *                                          percentage
+ *
+ *     local variable              114        47.1 %
+ *     global variable              22         9.1 %
+ *     parameter                    45        18.6 %
+ *        value                        23         9.5 %
+ *        reference                    22         9.1 %
+ *     function result               6         2.5 %
+ *     constant                     55        22.7 %
+ *                                 ---       -------
+ *                                 242       100.0 %
+ *
+ *
+ *  The program does not compute anything meaningful, but it is syntactically
+ *  and semantically correct. All variables have a value assigned to them
+ *  before they are used as a source operand.
+ *
+ *  There has been no explicit effort to account for the effects of a
+ *  cache, or to balance the use of long or short displacements for code or
+ *  data.
+ *
+ ***************************************************************************
+ */
+
+/* Compiler and system dependent definitions: */
+
+#ifndef TIME
+#undef TIMES
+#define TIMES
+#endif
+                /* Use times(2) time function unless    */
+                /* explicitly defined otherwise         */
+#ifdef MSC_CLOCK
+#undef HZ
+#undef TIMES
+#include <time.h>
+#define HZ	CLK_TCK
+#endif
+		/* Use Microsoft C hi-res clock */
+
+#ifdef TIMES
+#include <sys/types.h>
+#include <sys/times.h>
+                /* for "times" */
+#endif
+
+#define Mic_secs_Per_Second     1000000.0
+                /* Berkeley UNIX C returns process times in seconds/HZ */
+
+#ifdef  NOSTRUCTASSIGN
+#define structassign(d, s)      memcpy(&(d), &(s), sizeof(d))
+#else
+#define structassign(d, s)      d = s
+#endif
+
+#ifdef  NOENUM
+#define Ident_1 0
+#define Ident_2 1
+#define Ident_3 2
+#define Ident_4 3
+#define Ident_5 4
+  typedef int   Enumeration;
+#else
+  typedef       enum    {Ident_1, Ident_2, Ident_3, Ident_4, Ident_5}
+                Enumeration;
+#endif
+        /* for boolean and enumeration types in Ada, Pascal */
+
+/* General definitions: */
+
+#include <stdio.h>
+                /* for strcpy, strcmp */
+
+#define Null 0 
+                /* Value of a Null pointer */
+#define true  1
+#define false 0
+
+typedef int     One_Thirty;
+typedef int     One_Fifty;
+typedef char    Capital_Letter;
+typedef int     Boolean;
+typedef char    Str_30 [31];
+typedef int     Arr_1_Dim [50];
+typedef int     Arr_2_Dim [50] [50];
+
+typedef struct record 
+    {
+    struct record *Ptr_Comp;
+    Enumeration    Discr;
+    union {
+          struct {
+                  Enumeration Enum_Comp;
+                  int         Int_Comp;
+                  char        Str_Comp [31];
+                  } var_1;
+          struct {
+                  Enumeration E_Comp_2;
+                  char        Str_2_Comp [31];
+                  } var_2;
+          struct {
+                  char        Ch_1_Comp;
+                  char        Ch_2_Comp;
+                  } var_3;
+          } variant;
+      } Rec_Type, *Rec_Pointer;
+
+

lib/CPUs/MIPS/bsp/examples/dhry_1.c

@@ -0,0 +1,402 @@
+/*
+ ****************************************************************************
+ *
+ *                   "DHRYSTONE" Benchmark Program
+ *                   -----------------------------
+ *
+ *  Version:    C, Version 2.1
+ *
+ *  File:       dhry_1.c (part 2 of 3)
+ *
+ *  Date:       May 25, 1988
+ *
+ *  Author:     Reinhold P. Weicker
+ *
+ ****************************************************************************
+ */
+
+#include "dhry.h"
+
+/* Global Variables: */
+
+Rec_Pointer     Ptr_Glob,
+                Next_Ptr_Glob;
+int             Int_Glob;
+Boolean         Bool_Glob;
+char            Ch_1_Glob,
+                Ch_2_Glob;
+int             Arr_1_Glob [50];
+int             Arr_2_Glob [50] [50];
+
+extern char     *malloc ();
+Enumeration     Func_1 ();
+  /* forward declaration necessary since Enumeration may not simply be int */
+
+#ifndef REG
+        Boolean Reg = false;
+#define REG
+        /* REG becomes defined as empty */
+        /* i.e. no register variables   */
+#else
+        Boolean Reg = true;
+#endif
+
+/* variables for time measurement: */
+
+#ifdef TIMES
+struct tms      time_info;
+                /* see library function "times" */
+#define Too_Small_Time (2*HZ)
+                /* Measurements should last at least about 2 seconds */
+#endif
+#ifdef TIME
+extern long     time();
+                /* see library function "time"  */
+#define Too_Small_Time 2
+                /* Measurements should last at least 2 seconds */
+#endif
+#ifdef MSC_CLOCK
+extern clock_t	clock();
+#define Too_Small_Time (2*HZ)
+#endif
+
+long            Begin_Time,
+                End_Time,
+                User_Time;
+float           Microseconds,
+                Dhrystones_Per_Second;
+
+/* end of variables for time measurement */
+
+
+main ()
+/*****/
+
+  /* main program, corresponds to procedures        */
+  /* Main and Proc_0 in the Ada version             */
+{
+        One_Fifty       Int_1_Loc;
+  REG   One_Fifty       Int_2_Loc;
+        One_Fifty       Int_3_Loc;
+  REG   char            Ch_Index;
+        Enumeration     Enum_Loc;
+        Str_30          Str_1_Loc;
+        Str_30          Str_2_Loc;
+  REG   int             Run_Index;
+  REG   int             Number_Of_Runs;
+
+  /* Initializations */
+
+  Next_Ptr_Glob = (Rec_Pointer) malloc (sizeof (Rec_Type));
+  Ptr_Glob = (Rec_Pointer) malloc (sizeof (Rec_Type));
+
+  Ptr_Glob->Ptr_Comp                    = Next_Ptr_Glob;
+  Ptr_Glob->Discr                       = Ident_1;
+  Ptr_Glob->variant.var_1.Enum_Comp     = Ident_3;
+  Ptr_Glob->variant.var_1.Int_Comp      = 40;
+  strcpy (Ptr_Glob->variant.var_1.Str_Comp,
+          "DHRYSTONE PROGRAM, SOME STRING");
+  strcpy (Str_1_Loc, "DHRYSTONE PROGRAM, 1'ST STRING");
+
+  Arr_2_Glob [8][7] = 10;
+        /* Was missing in published program. Without this statement,    */
+        /* Arr_2_Glob [8][7] would have an undefined value.             */
+        /* Warning: With 16-Bit processors and Number_Of_Runs > 32000,  */
+        /* overflow may occur for this array element.                   */
+
+  /*
+  printf ("\n");
+  printf ("Dhrystone Benchmark, Version 2.1 (Language: C)\n");
+  printf ("\n");
+  if (Reg)
+  {
+    printf ("Program compiled with 'register' attribute\n");
+    printf ("\n");
+  }
+  else
+  {
+    printf ("Program compiled without 'register' attribute\n");
+    printf ("\n");
+  }
+  printf ("Please give the number of runs through the benchmark: ");
+  {
+    int n;
+    scanf ("%d", &n);
+    Number_Of_Runs = n;
+  }
+  printf ("\n");
+  */
+#ifdef NRUNS
+    Number_Of_Runs = NRUNS;
+#else
+    Number_Of_Runs = 2000000;
+#endif
+  printf ("Execution starts, %d runs through Dhrystone\n", Number_Of_Runs);
+
+  /***************/
+  /* Start timer */
+  /***************/
+
+#ifdef TIMES
+  times (&time_info);
+  Begin_Time = (long) time_info.tms_utime;
+#endif
+#ifdef TIME
+  Begin_Time = time ( (long *) 0);
+#endif
+#ifdef MSC_CLOCK
+  Begin_Time = clock();
+#endif
+
+  for (Run_Index = 1; Run_Index <= Number_Of_Runs; ++Run_Index)
+  {
+
+    Proc_5();
+    Proc_4();
+      /* Ch_1_Glob == 'A', Ch_2_Glob == 'B', Bool_Glob == true */
+    Int_1_Loc = 2;
+    Int_2_Loc = 3;
+    strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 2'ND STRING");
+    Enum_Loc = Ident_2;
+    Bool_Glob = ! Func_2 (Str_1_Loc, Str_2_Loc);
+      /* Bool_Glob == 1 */
+    while (Int_1_Loc < Int_2_Loc)  /* loop body executed once */
+    {
+      Int_3_Loc = 5 * Int_1_Loc - Int_2_Loc;
+        /* Int_3_Loc == 7 */
+      Proc_7 (Int_1_Loc, Int_2_Loc, &Int_3_Loc);
+        /* Int_3_Loc == 7 */
+      Int_1_Loc += 1;
+    } /* while */
+      /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */
+    Proc_8 (Arr_1_Glob, Arr_2_Glob, Int_1_Loc, Int_3_Loc);
+      /* Int_Glob == 5 */
+    Proc_1 (Ptr_Glob);
+    for (Ch_Index = 'A'; Ch_Index <= Ch_2_Glob; ++Ch_Index)
+                             /* loop body executed twice */
+    {
+      if (Enum_Loc == Func_1 (Ch_Index, 'C'))
+          /* then, not executed */
+        {
+        Proc_6 (Ident_1, &Enum_Loc);
+        strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 3'RD STRING");
+        Int_2_Loc = Run_Index;
+        Int_Glob = Run_Index;
+        }
+    }
+      /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */
+    Int_2_Loc = Int_2_Loc * Int_1_Loc;
+    Int_1_Loc = Int_2_Loc / Int_3_Loc;
+    Int_2_Loc = 7 * (Int_2_Loc - Int_3_Loc) - Int_1_Loc;
+      /* Int_1_Loc == 1, Int_2_Loc == 13, Int_3_Loc == 7 */
+    Proc_2 (&Int_1_Loc);
+      /* Int_1_Loc == 5 */
+
+  } /* loop "for Run_Index" */
+
+  /**************/
+  /* Stop timer */
+  /**************/
+
+#ifdef TIMES
+  times (&time_info);
+  End_Time = (long) time_info.tms_utime;
+#endif
+#ifdef TIME
+  End_Time = time ( (long *) 0);
+#endif
+#ifdef MSC_CLOCK
+  End_Time = clock();
+#endif
+  /*
+  printf ("Execution ends\n");
+  printf ("\n");
+  printf ("Final values of the variables used in the benchmark:\n");
+  printf ("\n");
+  printf ("Int_Glob:            %d\n", Int_Glob);
+  printf ("        should be:   %d\n", 5);
+  printf ("Bool_Glob:           %d\n", Bool_Glob);
+  printf ("        should be:   %d\n", 1);
+  printf ("Ch_1_Glob:           %c\n", Ch_1_Glob);
+  printf ("        should be:   %c\n", 'A');
+  printf ("Ch_2_Glob:           %c\n", Ch_2_Glob);
+  printf ("        should be:   %c\n", 'B');
+  printf ("Arr_1_Glob[8]:       %d\n", Arr_1_Glob[8]);
+  printf ("        should be:   %d\n", 7);
+  printf ("Arr_2_Glob[8][7]:    %d\n", Arr_2_Glob[8][7]);
+  printf ("        should be:   Number_Of_Runs + 10\n");
+  printf ("Ptr_Glob->\n");
+  printf ("  Ptr_Comp:          %d\n", (int) Ptr_Glob->Ptr_Comp);
+  printf ("        should be:   (implementation-dependent)\n");
+  printf ("  Discr:             %d\n", Ptr_Glob->Discr);
+  printf ("        should be:   %d\n", 0);
+  printf ("  Enum_Comp:         %d\n", Ptr_Glob->variant.var_1.Enum_Comp);
+  printf ("        should be:   %d\n", 2);
+  printf ("  Int_Comp:          %d\n", Ptr_Glob->variant.var_1.Int_Comp);
+  printf ("        should be:   %d\n", 17);
+  printf ("  Str_Comp:          %s\n", Ptr_Glob->variant.var_1.Str_Comp);
+  printf ("        should be:   DHRYSTONE PROGRAM, SOME STRING\n");
+  printf ("Next_Ptr_Glob->\n");
+  printf ("  Ptr_Comp:          %d\n", (int) Next_Ptr_Glob->Ptr_Comp);
+  printf ("        should be:   (implementation-dependent), same as above\n");
+  printf ("  Discr:             %d\n", Next_Ptr_Glob->Discr);
+  printf ("        should be:   %d\n", 0);
+  printf ("  Enum_Comp:         %d\n", Next_Ptr_Glob->variant.var_1.Enum_Comp);
+  printf ("        should be:   %d\n", 1);
+  printf ("  Int_Comp:          %d\n", Next_Ptr_Glob->variant.var_1.Int_Comp);
+  printf ("        should be:   %d\n", 18);
+  printf ("  Str_Comp:          %s\n",
+                                Next_Ptr_Glob->variant.var_1.Str_Comp);
+  printf ("        should be:   DHRYSTONE PROGRAM, SOME STRING\n");
+  printf ("Int_1_Loc:           %d\n", Int_1_Loc);
+  printf ("        should be:   %d\n", 5);
+  printf ("Int_2_Loc:           %d\n", Int_2_Loc);
+  printf ("        should be:   %d\n", 13);
+  printf ("Int_3_Loc:           %d\n", Int_3_Loc);
+  printf ("        should be:   %d\n", 7);
+  printf ("Enum_Loc:            %d\n", Enum_Loc);
+  printf ("        should be:   %d\n", 1);
+  printf ("Str_1_Loc:           %s\n", Str_1_Loc);
+  printf ("        should be:   DHRYSTONE PROGRAM, 1'ST STRING\n");
+  printf ("Str_2_Loc:           %s\n", Str_2_Loc);
+  printf ("        should be:   DHRYSTONE PROGRAM, 2'ND STRING\n");
+  printf ("\n");
+
+*/
+  User_Time = End_Time - Begin_Time;
+
+  if (User_Time < Too_Small_Time)
+  {
+    printf ("Measured time too small to obtain meaningful results\n");
+    printf ("Please increase number of runs\n");
+    printf ("\n");
+  }
+  else
+  {
+#ifdef TIME
+    Microseconds = (float) User_Time * Mic_secs_Per_Second
+                        / (float) Number_Of_Runs;
+    Dhrystones_Per_Second = (float) Number_Of_Runs / (float) User_Time;
+#else
+    Microseconds = (float) User_Time * Mic_secs_Per_Second
+                        / ((float) HZ * ((float) Number_Of_Runs));
+    Dhrystones_Per_Second = ((float) HZ * (float) Number_Of_Runs)
+                        / (float) User_Time;
+#endif
+    printf ("Microseconds for one run through Dhrystone: ");
+    printf ("%6.1f \n", Microseconds);
+    printf ("Dhrystones per Second:                      ");
+    printf ("%6.1f \n", Dhrystones_Per_Second);
+    printf ("\n");
+    printf ("This equals to %6.1f DMIPS\n", Dhrystones_Per_Second/1757);
+  }
+
+}
+
+
+Proc_1 (Ptr_Val_Par)
+/******************/
+
+REG Rec_Pointer Ptr_Val_Par;
+    /* executed once */
+{
+  REG Rec_Pointer Next_Record = Ptr_Val_Par->Ptr_Comp;
+                                        /* == Ptr_Glob_Next */
+  /* Local variable, initialized with Ptr_Val_Par->Ptr_Comp,    */
+  /* corresponds to "rename" in Ada, "with" in Pascal           */
+
+  structassign (*Ptr_Val_Par->Ptr_Comp, *Ptr_Glob);
+  Ptr_Val_Par->variant.var_1.Int_Comp = 5;
+  Next_Record->variant.var_1.Int_Comp
+        = Ptr_Val_Par->variant.var_1.Int_Comp;
+  Next_Record->Ptr_Comp = Ptr_Val_Par->Ptr_Comp;
+  Proc_3 (&Next_Record->Ptr_Comp);
+    /* Ptr_Val_Par->Ptr_Comp->Ptr_Comp
+                        == Ptr_Glob->Ptr_Comp */
+  if (Next_Record->Discr == Ident_1)
+    /* then, executed */
+  {
+    Next_Record->variant.var_1.Int_Comp = 6;
+    Proc_6 (Ptr_Val_Par->variant.var_1.Enum_Comp,
+           &Next_Record->variant.var_1.Enum_Comp);
+    Next_Record->Ptr_Comp = Ptr_Glob->Ptr_Comp;
+    Proc_7 (Next_Record->variant.var_1.Int_Comp, 10,
+           &Next_Record->variant.var_1.Int_Comp);
+  }
+  else /* not executed */
+    structassign (*Ptr_Val_Par, *Ptr_Val_Par->Ptr_Comp);
+} /* Proc_1 */
+
+
+Proc_2 (Int_Par_Ref)
+/******************/
+    /* executed once */
+    /* *Int_Par_Ref == 1, becomes 4 */
+
+One_Fifty   *Int_Par_Ref;
+{
+  One_Fifty  Int_Loc;
+  Enumeration   Enum_Loc;
+
+  Int_Loc = *Int_Par_Ref + 10;
+  do /* executed once */
+    if (Ch_1_Glob == 'A')
+      /* then, executed */
+    {
+      Int_Loc -= 1;
+      *Int_Par_Ref = Int_Loc - Int_Glob;
+      Enum_Loc = Ident_1;
+    } /* if */
+  while (Enum_Loc != Ident_1); /* true */
+} /* Proc_2 */
+
+
+Proc_3 (Ptr_Ref_Par)
+/******************/
+    /* executed once */
+    /* Ptr_Ref_Par becomes Ptr_Glob */
+
+Rec_Pointer *Ptr_Ref_Par;
+
+{
+  if (Ptr_Glob != Null)
+    /* then, executed */
+    *Ptr_Ref_Par = Ptr_Glob->Ptr_Comp;
+  Proc_7 (10, Int_Glob, &Ptr_Glob->variant.var_1.Int_Comp);
+} /* Proc_3 */
+
+
+Proc_4 () /* without parameters */
+/*******/
+    /* executed once */
+{
+  Boolean Bool_Loc;
+
+  Bool_Loc = Ch_1_Glob == 'A';
+  Bool_Glob = Bool_Loc | Bool_Glob;
+  Ch_2_Glob = 'B';
+} /* Proc_4 */
+
+
+Proc_5 () /* without parameters */
+/*******/
+    /* executed once */
+{
+  Ch_1_Glob = 'A';
+  Bool_Glob = false;
+} /* Proc_5 */
+
+
+        /* Procedure for the assignment of structures,          */
+        /* if the C compiler doesn't support this feature       */
+#ifdef  NOSTRUCTASSIGN
+memcpy (d, s, l)
+register char   *d;
+register char   *s;
+register int    l;
+{
+        while (l--) *d++ = *s++;
+}
+#endif
+
+

lib/CPUs/MIPS/bsp/examples/dhry_2.c

@@ -0,0 +1,192 @@
+/*
+ ****************************************************************************
+ *
+ *                   "DHRYSTONE" Benchmark Program
+ *                   -----------------------------
+ *                                                                            
+ *  Version:    C, Version 2.1
+ *                                                                            
+ *  File:       dhry_2.c (part 3 of 3)
+ *
+ *  Date:       May 25, 1988
+ *
+ *  Author:     Reinhold P. Weicker
+ *
+ ****************************************************************************
+ */
+
+#include "dhry.h"
+
+#ifndef REG
+#define REG
+        /* REG becomes defined as empty */
+        /* i.e. no register variables   */
+#endif
+
+extern  int     Int_Glob;
+extern  char    Ch_1_Glob;
+
+
+Proc_6 (Enum_Val_Par, Enum_Ref_Par)
+/*********************************/
+    /* executed once */
+    /* Enum_Val_Par == Ident_3, Enum_Ref_Par becomes Ident_2 */
+
+Enumeration  Enum_Val_Par;
+Enumeration *Enum_Ref_Par;
+{
+  *Enum_Ref_Par = Enum_Val_Par;
+  if (! Func_3 (Enum_Val_Par))
+    /* then, not executed */
+    *Enum_Ref_Par = Ident_4;
+  switch (Enum_Val_Par)
+  {
+    case Ident_1: 
+      *Enum_Ref_Par = Ident_1;
+      break;
+    case Ident_2: 
+      if (Int_Glob > 100)
+        /* then */
+      *Enum_Ref_Par = Ident_1;
+      else *Enum_Ref_Par = Ident_4;
+      break;
+    case Ident_3: /* executed */
+      *Enum_Ref_Par = Ident_2;
+      break;
+    case Ident_4: break;
+    case Ident_5: 
+      *Enum_Ref_Par = Ident_3;
+      break;
+  } /* switch */
+} /* Proc_6 */
+
+
+Proc_7 (Int_1_Par_Val, Int_2_Par_Val, Int_Par_Ref)
+/**********************************************/
+    /* executed three times                                      */ 
+    /* first call:      Int_1_Par_Val == 2, Int_2_Par_Val == 3,  */
+    /*                  Int_Par_Ref becomes 7                    */
+    /* second call:     Int_1_Par_Val == 10, Int_2_Par_Val == 5, */
+    /*                  Int_Par_Ref becomes 17                   */
+    /* third call:      Int_1_Par_Val == 6, Int_2_Par_Val == 10, */
+    /*                  Int_Par_Ref becomes 18                   */
+One_Fifty       Int_1_Par_Val;
+One_Fifty       Int_2_Par_Val;
+One_Fifty      *Int_Par_Ref;
+{
+  One_Fifty Int_Loc;
+
+  Int_Loc = Int_1_Par_Val + 2;
+  *Int_Par_Ref = Int_2_Par_Val + Int_Loc;
+} /* Proc_7 */
+
+
+Proc_8 (Arr_1_Par_Ref, Arr_2_Par_Ref, Int_1_Par_Val, Int_2_Par_Val)
+/*********************************************************************/
+    /* executed once      */
+    /* Int_Par_Val_1 == 3 */
+    /* Int_Par_Val_2 == 7 */
+Arr_1_Dim       Arr_1_Par_Ref;
+Arr_2_Dim       Arr_2_Par_Ref;
+int             Int_1_Par_Val;
+int             Int_2_Par_Val;
+{
+  REG One_Fifty Int_Index;
+  REG One_Fifty Int_Loc;
+
+  Int_Loc = Int_1_Par_Val + 5;
+  Arr_1_Par_Ref [Int_Loc] = Int_2_Par_Val;
+  Arr_1_Par_Ref [Int_Loc+1] = Arr_1_Par_Ref [Int_Loc];
+  Arr_1_Par_Ref [Int_Loc+30] = Int_Loc;
+  for (Int_Index = Int_Loc; Int_Index <= Int_Loc+1; ++Int_Index)
+    Arr_2_Par_Ref [Int_Loc] [Int_Index] = Int_Loc;
+  Arr_2_Par_Ref [Int_Loc] [Int_Loc-1] += 1;
+  Arr_2_Par_Ref [Int_Loc+20] [Int_Loc] = Arr_1_Par_Ref [Int_Loc];
+  Int_Glob = 5;
+} /* Proc_8 */
+
+
+Enumeration Func_1 (Ch_1_Par_Val, Ch_2_Par_Val)
+/*************************************************/
+    /* executed three times                                         */
+    /* first call:      Ch_1_Par_Val == 'H', Ch_2_Par_Val == 'R'    */
+    /* second call:     Ch_1_Par_Val == 'A', Ch_2_Par_Val == 'C'    */
+    /* third call:      Ch_1_Par_Val == 'B', Ch_2_Par_Val == 'C'    */
+
+Capital_Letter   Ch_1_Par_Val;
+Capital_Letter   Ch_2_Par_Val;
+{
+  Capital_Letter        Ch_1_Loc;
+  Capital_Letter        Ch_2_Loc;
+
+  Ch_1_Loc = Ch_1_Par_Val;
+  Ch_2_Loc = Ch_1_Loc;
+  if (Ch_2_Loc != Ch_2_Par_Val)
+    /* then, executed */
+    return (Ident_1);
+  else  /* not executed */
+  {
+    Ch_1_Glob = Ch_1_Loc;
+    return (Ident_2);
+   }
+} /* Func_1 */
+
+
+Boolean Func_2 (Str_1_Par_Ref, Str_2_Par_Ref)
+/*************************************************/
+    /* executed once */
+    /* Str_1_Par_Ref == "DHRYSTONE PROGRAM, 1'ST STRING" */
+    /* Str_2_Par_Ref == "DHRYSTONE PROGRAM, 2'ND STRING" */
+
+Str_30  Str_1_Par_Ref;
+Str_30  Str_2_Par_Ref;
+{
+  REG One_Thirty        Int_Loc;
+      Capital_Letter    Ch_Loc;
+
+  Int_Loc = 2;
+  while (Int_Loc <= 2) /* loop body executed once */
+    if (Func_1 (Str_1_Par_Ref[Int_Loc],
+                Str_2_Par_Ref[Int_Loc+1]) == Ident_1)
+      /* then, executed */
+    {
+      Ch_Loc = 'A';
+      Int_Loc += 1;
+    } /* if, while */
+  if (Ch_Loc >= 'W' && Ch_Loc < 'Z')
+    /* then, not executed */
+    Int_Loc = 7;
+  if (Ch_Loc == 'R')
+    /* then, not executed */
+    return (true);
+  else /* executed */
+  {
+    if (strcmp (Str_1_Par_Ref, Str_2_Par_Ref) > 0)
+      /* then, not executed */
+    {
+      Int_Loc += 7;
+      Int_Glob = Int_Loc;
+      return (true);
+    }
+    else /* executed */
+      return (false);
+  } /* if Ch_Loc */
+} /* Func_2 */
+
+
+Boolean Func_3 (Enum_Par_Val)
+/***************************/
+    /* executed once        */
+    /* Enum_Par_Val == Ident_3 */
+Enumeration Enum_Par_Val;
+{
+  Enumeration Enum_Loc;
+
+  Enum_Loc = Enum_Par_Val;
+  if (Enum_Loc == Ident_3)
+    /* then, executed */
+    return (true);
+  else /* not executed */
+    return (false);
+} /* Func_3 */
+

lib/CPUs/MIPS/bsp/examples/dttl.c

@@ -0,0 +1,261 @@
+/* dttl.c -- simulation of Cassini/Huygens symbol synchronizer loop
+ *
+ * Author:           Lorenzo Simone's (matlab script)
+ * Modifications by: Jon Hamkins (conversion to C, support routines,
+ *                   memory requirement reductions)
+ * Last Revised:     Wed Jan 31 10:47:52 PST 2001
+ */
+#define	M_PI	3.1415926535897932384626433832795
+
+#include <math.h>
+#include <stdio.h>
+#include "random.h"
+
+/* global variables */
+int delay,
+   L;  /* samples per symbol */
+double Pt, /* transition density */
+   sigma;  /* noise standard deviation */
+long seed=-123;
+
+/* This function simulates a large 1-dimensional array without requiring
+ * storage for the whole array.  This is possible because the array is
+ * accessed in roughly increasing indices.  Thus, we only need to
+ * store a few symbols worth of samples in the array, and we can reuse
+ * the array indices as time goes on. */
+int drint(double v)
+{
+	return (int)(v+0.5);
+}
+
+double
+rec(int idx)
+{
+   static int firsttime = 1,
+      max,                  /* maximum index containing data */
+      mod,                  /* length of ring buffer */
+      b;                    /* value of last transmitted bit */
+   static double r[2000];   /* need several symbols worth of samples */
+   int i,j,k;
+
+   /* First time, store samples for random delay and first few symbols */
+   if (firsttime==1) {
+      firsttime=0;
+      for (i=0; i<delay; i++) r[i] = 0;  /* random delay */
+      b = (ran1(&seed)>0.5) ? 1 : -1; /* first random symbol */
+      for (j=0; j<3; j++) { /* 3 binary symbols with transition Pt */
+         b = (ran1(&seed)>Pt) ? b : -b;  /* next symbol value */
+         for (k=0; k<L; k++) r[i++] = b + sigma*gaussian(&seed);
+      }
+      max = i-1;
+      mod = i;
+   }
+   if (idx>max)  /* check if we need to create another sample */
+   {
+      b = (ran1(&seed)>Pt) ? b : -b;  /* next symbol value */
+      /* generate samples for one symbol and store in ring buffer */
+      for (i=1; i<=L; i++) r[(int)(fmod(max+i,mod))] = b+sigma*gaussian(&seed);
+      max += L;  /* maximum index for which samples exist */
+   }
+   /* return appropriate sample from ring buffer */
+   return(r[(int)(fmod(idx,mod))]);
+}
+
+main()
+{
+   double
+      detout,            /* detector output */
+      I, old_I,          /* in-phase accumulations */
+      Q, old_Q,          /* quadrature accumulations */
+      T,                 /* transition detection */
+      theta,             /* baseband NCO output (radians) */
+      lambda,            /* normalized timing error (symbols) */
+      A, alfa, Ampl, Bl, Df,
+      DR, Es_No, Es_No_lin, Fc1, Fc2, Fvco, Fs, Kd, Kv,
+      lambda_ss_sim = 0., lambda_ss_th, No, P, P_No,
+      sigma_lambda_sim = 0., sigma_lambda_th, SNR_sim, SNR_th, tau, Tc1, Tc2,
+      time, Ts, x1, Y, bit_I, bit_Q, bit;
+   int i, j, k, N, offset, k1, k2, EOB;
+   FILE *p1, *p2, *p3, *p4, *p5;
+
+   /* Data settings */
+   Fc1 = 48000;        /* sample rate at DTTL input (F1/2 = 8.215MHz/2) */
+   Tc1 = 1./Fc1;
+
+   DR = 4800;           /* data rate (symb/sec)  */
+
+   Fc2 = DR;             /* sampling rate pre-detection */
+   Tc2 = 1./Fc2;
+
+   L = drint(Tc2/Tc1);    /* samples per symbol in the arm filters */
+   offset = drint(L/2.);
+
+   Es_No = 600.;                    /* dB */
+   P_No = Es_No+10.*log10(DR);     /* data power-over-noise spectral density */
+                                   /* ratio (dBHz) */
+
+   N = 2500;                       /* number of symbols to simulate */
+   Pt=.5;                          /* Transition density */
+
+   Bl=0.01*DR;                     /* loop bandwidth (Hz)  */
+   Df=0.001*DR;                      /* frequency offset */
+   Fvco=DR+Df;
+
+   tau=ran1(&seed)-.5;             /* set symbol timing offset, -.5 to .5 */
+   delay=drint(2.*L+tau*L+1);       /* channel delay */
+
+   P=1.;                           /* data power */
+   Ampl=sqrt(P);
+
+   No=10.*log10(P*Tc2)-Es_No;      /* noise spectral density (dBW/Hz)  */
+   sigma=sqrt(pow(10.,0.1*No)/(2.*Tc1));
+   printf("sigma=%f\n",sigma);
+
+   /* DPLL settings */
+   Fs=DR;                           /* loop sampling frequency (Hz) */
+   Ts=1./Fs;                        /* loop sampling time (s) */
+
+   /* Loop gain */
+   Kd=2.*Ampl*Pt;                   /* phase detector gain (quants/rad) */
+                                    /* @ high Es/No */
+   Kv=1.;                           /* VCO gain (rad/quants) */
+
+   /* Analog loop filter components */
+   alfa=4.*Bl/(Kd*Kv);
+
+   /* Digital loop filter components */
+   A=alfa*Ts;
+
+   /* Initial condition */
+   theta = 0;
+   old_I=1;
+   old_Q=1;
+   x1=0;
+   Y=0;
+
+   /* Plot data files */
+//   p1 = fopen("plot1.dat","w");  /* theta */
+//   p2 = fopen("plot2.dat","w");  /* lambda */
+//   p3 = fopen("plot3.dat","w");  /* detout */
+//   p4 = fopen("plot4.dat","w");  /* I-Data */
+//   p5 = fopen("plot5.dat","w");  /* Q-Data */
+
+   k1 = drint(0.5*N);
+   k2 = N;
+
+   printf("Data rate: %.0f symbols/sec\n",DR);
+   printf("Sample rate at DTTL input: %.0f samples/sec\n",Fc1);
+   printf("Samples per symbol: %d\n",L);
+   printf("Random delay set to: %f symbols (%d samples)\n",tau,delay);
+   printf("Transition density used in random bit generation: %f\n",Pt);
+   printf("Es/No: %f dB\n",Es_No);
+   printf("Loop bandwidth: %f Hz\n",Bl);
+   printf("Doppler: %f Hz\n",Df);
+   printf("Simulation length: %d symbols (%d samples)\n\n",N,N*L+delay);
+
+   /* Simulation Loop */
+   for (i=2; i<=N; i++)
+   {
+	  /* loop over symbols */
+      /* find start of in-phase integration */
+      for (j=1; j < L; j++)
+	  {
+         if (fmod(theta + 2*M_PI * Fvco*(j+1+(i-1)*(Fc1/DR))/Fc1, 2*M_PI)
+		   < fmod(theta + 2*M_PI * Fvco*(j  +(i-1)*(Fc1/DR))/Fc1, 2*M_PI))
+           break;
+		/* one could replace loop above with a direct calculation such as: */
+		/* j=ceil((1.-modulo(theta/(2*M_PI),1.))/(Fvco*Tc1))-1.; */
+		/* j+1 is the first index in the block */
+		EOB=j+(i-1)*L;  /* End of Block */
+	  }
+      /* In-phase integrator */
+      bit_I = 0.;
+	  printf("Symbol # %d\n", i);
+	  printf("I[%d:%d] :\n", EOB-L+1, EOB);
+      for (j=EOB-L+1; j<=EOB; j++)
+	  {
+		  bit = rec(j);
+		  if (bit > 0)
+			  printf("-");
+		  else
+			  printf("_");
+
+		  bit_I += bit;
+	  }
+	  printf("\n");
+  	  I = bit_I;
+
+      /* Mid-Phase integrator */
+      bit_Q = 0.;
+	  printf("Q[%d:%d] :\n", EOB-L+offset+1, EOB+offset);
+      for (j=EOB-L+offset+1; j<=EOB+offset; j++)
+	  {
+		  bit = rec(j);
+		  if (bit > 0)
+			  printf("-");
+		  else
+			  printf("_");
+
+		  bit_Q += bit;
+	  }
+	  printf("\n\n");
+	  Q = bit_Q;
+
+      Q *= 2.*M_PI/(Tc2/Tc1);
+
+      /* Transition Detector */
+      I = (I > 0) ? 1. : -1.;  /* hard limiter */
+      T = 0.5*(I - old_I);
+
+      /* Detector Output */
+      detout = fmod(old_Q*T,2*M_PI);
+
+      /* Save accumulations for next time through loop */
+      old_I = I;
+      old_Q = Q;
+      if (fabs(detout)>M_PI)
+         detout = -detout+2*M_PI*((detout>0) ? 1. : -1.);
+
+      /* NCO */
+      Y += detout*A; /* Loop filter */
+      theta=Kv*Y;  /* phase */
+//      lambda = theta/(2.*M_PI)+(i*Tc2*Df+tau);  /* normalized error */
+      lambda = theta/(2.*M_PI)+(i*(Fvco/DR -1) + tau);  /* normalized error */
+
+     /* error mean and variance calculation */
+      lambda_ss_sim += lambda;  /* partial sum */
+      sigma_lambda_sim += lambda*lambda; /* partial sum of squares */
+
+      /* store phase and normalized error to data files */
+//      fprintf(p1,"%f %f\n",(double)i,theta);
+//      fprintf(p2,"%f %f\n",(double)i,lambda);
+//      fprintf(p3,"%f %f\n",(double)i,detout);
+//      fprintf(p4,"%f %f\n",(double)i,I);
+//      fprintf(p5,"%f %f\n",(double)i,Q);
+   }
+//   fclose(p1);
+//   fclose(p2);
+//   fclose(p3);
+//   fclose(p4);
+//   fclose(p5);
+
+   /* Statistics Analysis */
+   /* ------------------- */
+   /* complete the mean and variance calculation */
+   lambda_ss_sim /= N;
+   sigma_lambda_sim = sigma_lambda_sim/N - lambda_ss_sim*lambda_ss_sim;
+   Es_No_lin = pow(10.,0.1*Es_No);
+//   sigma_lambda_th = Bl*Tc2/(4.*Pt*Es_No_lin*pow(erf(sqrt(Es_No_lin)),2.));
+   sigma_lambda_th = Bl*Tc2/(4.*Pt*Es_No_lin*Es_No_lin);
+   SNR_sim = -10*log10(sigma_lambda_sim);
+   SNR_th = -10*log10(sigma_lambda_th);
+   /* Steady-State error */
+   lambda_ss_th=Df/(4.*Bl);
+   printf("Simulation: var: %f rad^2  loop SNR: %f dB ss error: %f%%\n",
+         sigma_lambda_sim, SNR_sim, 100.*lambda_ss_sim);
+   printf("Theory:     var: %f rad^2  loop SNR: %f dB ss error: %f%%\n",
+         sigma_lambda_th, SNR_th, 100.*lambda_ss_th);
+//   system("gnuplot < plot1.gp");
+//   system("gnuplot < plot2.gp");
+      printf("Done.\n");
+}

lib/CPUs/MIPS/bsp/examples/hello.c

@@ -0,0 +1,18 @@
+#include "libsys.h"
+
+
+int main (void)
+{
+	UINT32 *pGPIO0 = (UINT32*)sys_gpio0;
+	UINT32 *pGPIO1 = (UINT32*)sys_gpio1;
+
+	*pGPIO0 = 0x55555555;
+	*pGPIO1 = 0x55555555;
+
+	sputs("Hello world!");
+
+	*pGPIO0 = 0xAAAAAAAA;
+	*pGPIO1 = 0xAAAAAAAA;
+	return 0;
+}
+

lib/CPUs/MIPS/bsp/examples/init.S

@@ -0,0 +1,45 @@
+		.file	"init.S"
+	
+		.text
+		.align	2
+		.globl _init
+		.extern end
+	
+_init:
+		.set	noreorder
+
+		# set uart
+		la	$8, sys_uart_baud
+		addiu	$9, $0, baudrate
+		sb	$9, 0($8)
+		
+		# set stack pointer 
+		la $sp, stack_ptr
+		la $gp, _gp
+		
+		# zero bss
+		la $8, __bss_start
+		la $9, end
+$zeroise:		
+		sw $0, 0($8)
+		bne $8, $9, $zeroise
+		addiu	$8, 4
+		
+		# zero sbss
+#		la $8, __sbss_start
+#		la $9, __sbss_end
+#$szeroise:		
+#		sw $0, 0($8)
+#		bne $8, $9, $szeroise
+#		addiu	$8, 4
+
+		# jump main
+		la $8, main
+		jalr $8
+
+_terminate:
+		nop
+		j		_terminate
+		nop
+		
+		.set	reorder

lib/CPUs/MIPS/bsp/examples/irq.c

@@ -0,0 +1,91 @@
+#include <sys/times.h>
+#include <sys/time.h>
+#include <sys/stat.h>
+#include <errno.h>
+#include <stdlib.h>
+#include "libsys.h"
+#include "regdef.h"
+#include "xcpt.h"
+#include "irq.h"
+
+static fp_t g_irq_handler[MAX_NUM_IRQ] = {NULL};
+
+int _irq_dispatch(struct xcptcontext * xcp)
+{
+	int i, ip;
+
+	ip =  (xcp->cr >> 8) & 0xFF;
+
+	for (i=0; i < MAX_NUM_IRQ; i++)
+	{
+		if (ip & 1)
+			if (g_irq_handler[i])
+				(g_irq_handler[i])();
+
+		ip >>= 1;
+	}
+
+	return 0;
+}
+
+void interrupt_register(int irq_num, fp_t fp)
+{
+	if ((irq_num >= 0) && (irq_num < MAX_NUM_IRQ))
+		g_irq_handler[irq_num] = fp;
+
+}
+
+void interrupt_enable(int irq_num)
+{
+	reg_t reg, im;
+
+	if ((irq_num >= 0) && (irq_num < MAX_NUM_IRQ))
+	{
+		im = 1 << irq_num;
+		reg = CP0_SR_read();
+		reg |= (SR_MASK_IM & (im << 8));
+		CP0_SR_write(reg);
+	}
+
+}
+
+void interrupt_disable(int irq_num)
+{
+	reg_t reg, im;
+
+	if ((irq_num >= 0) && (irq_num < MAX_NUM_IRQ))
+	{
+		im = 1 << irq_num;
+		reg = CP0_SR_read();
+		reg &= ~(SR_MASK_IM & (im << 8));
+		CP0_SR_write(reg);
+	}
+}
+
+void interrupt_set(int irq_num)
+{
+	reg_t reg, ip;
+
+	if ((irq_num >= 0) && (irq_num < MAX_NUM_IRQ))
+	{
+		ip = 1 << irq_num;
+		reg = CP0_CR_read();
+		reg |= (CR_MASK_IP & (ip << 8));
+		CP0_CR_write(reg);
+	}
+}
+
+void interrupt_clr(int irq_num)
+{
+	reg_t reg, ip;
+
+	if ((irq_num >= 0) && (irq_num < MAX_NUM_IRQ))
+	{
+		ip = 1 << irq_num;
+		reg = CP0_CR_read();
+		reg &= ~(CR_MASK_IP & (ip << 8));
+		CP0_CR_write(reg);
+	}
+}
+
+

lib/CPUs/MIPS/bsp/examples/irq.h

@@ -0,0 +1,15 @@
+#ifndef IRQ_H
+#define IRQ_H
+
+#include "xcpt.h"
+
+#define MAX_NUM_IRQ				8
+
+typedef void (*fp_t)(void);
+
+int _irq_dispatch(struct xcptcontext * xcp);
+void interrupt_register(int irq_num, fp_t fp);
+void interrupt_enable(int irq_num);
+void interrupt_disable(int irq_num);
+
+#endif // IRQ_H

lib/CPUs/MIPS/bsp/examples/kernel.S

@@ -0,0 +1,180 @@
+#include <regdef.h>
+#include <xcpt_asm.h>
+
+		.section .ktext,"ax"
+
+LEAF(xcptlow_handler)
+		.set noreorder
+		.set noat
+		/* Note: exceptions do not save and restore registers k0 and k1.
+		* on entry, k1 = exception class.
+		*/
+		
+		/* allocate exception stack frame (on 8-byte boundary) */
+		subu k1, sp, XCP_SIZE
+		srl k1, 3 	/* shift right/left -> alligned on boundary */
+		sll k1, 3
+
+		/* save enough registers to get by */
+		sw AT, XCP_AT(k1)
+		sw v0, XCP_V0(k1)
+		sw v1, XCP_V1(k1)
+		sw a0, XCP_A0(k1)
+		sw a1, XCP_A1(k1)
+		sw a2, XCP_A2(k1)
+		sw a3, XCP_A3(k1)
+		sw sp, XCP_SP(k1)
+		sw ra, XCP_RA(k1)
+		
+		/* get coprocessor 0 exception state */
+		mfc0 a0, CP0_CR
+		mfc0 a1, CP0_SR
+		mfc0 a2, CP0_BADDR
+		mfc0 a3, CP0_EPC
+
+		/* we can safely use AT now */
+		.set at
+
+		/* switch to using sp to point at exception frame */
+		move sp, k1
+		
+		/* nothing sensible to store for k0/k1, store zero */
+		sw zero, XCP_K0(sp)
+		sw zero, XCP_K1(sp)		
+
+		/* we are now interruptible: dump all remaining state
+		* into the exception stack frame.
+		*/
+		/* coprocessor exception state */
+		sw a0, XCP_CR(sp)
+		sw a1, XCP_SR(sp)
+		sw a2, XCP_BADDR(sp)
+		sw a3, XCP_EPC(sp)
+
+		/* mdhi and mdlo */
+		mfhi v0
+		mflo v1
+		sw v0, XCP_MDHI(sp)
+		sw v1, XCP_MDLO(sp)
+
+		/* Save all the other general registers.
+		* We save zero, s0-s7 and s8 as well, as instruction emulators (e.g. FP
+		* operations) and debuggers rely on all registers stored together in
+		* well-defined structure.
+		*/
+		sw zero, XCP_ZERO(sp)
+		sw t0, XCP_T0(sp)
+		sw t1, XCP_T1(sp)
+		sw t2, XCP_T2(sp)
+		sw t3, XCP_T3(sp)
+		sw t4, XCP_T4(sp)
+		sw t5, XCP_T5(sp)
+		sw t6, XCP_T6(sp)
+		sw t7, XCP_T7(sp)
+		sw s0, XCP_S0(sp)
+		sw s1, XCP_S1(sp)
+		sw s2, XCP_S2(sp)
+		sw s3, XCP_S3(sp)
+		sw s4, XCP_S4(sp)
+		sw s5, XCP_S5(sp)
+		sw s6, XCP_S6(sp)
+		sw s7, XCP_S7(sp)
+		sw t8, XCP_T8(sp)
+		sw t9, XCP_T9(sp)
+		sw gp, XCP_GP(sp)
+		sw s8, XCP_S8(sp)
+
+		/* I don't know what the following does. [rb] */
+		/* load our _gp pointer */
+#		la gp, _gp
+
+		/* and call the C exception handler */
+		move a0, sp	# arg1 = &xcp
+		subu sp, 16	# (arg save area)
+		j _xcptcall
+		move ra, zero	# fake return address
+		
+		/* This strange call to _xcptcall with zero return address is to
+		* help exception-aware debuggers to trace back over the exception event.
+		* We are basically interposing a bogus stackframe (with a zero return
+		* address) between the C exception handler and the actual machine
+		* exception.
+		*/
+xcptrest:
+		.set noat
+		add AT, sp, 16
+		
+		/* at points to exception frame */
+xcptrestother:
+		/* restore all state */
+		/* restore most general registers */
+		lw t0, XCP_T0(AT)
+		lw t1, XCP_T1(AT)
+		lw t2, XCP_T2(AT)
+		lw t3, XCP_T3(AT)
+		lw t4, XCP_T4(AT)
+		lw t5, XCP_T5(AT)
+		lw t6, XCP_T6(AT)
+		lw t7, XCP_T7(AT)
+		lw s0, XCP_S0(AT)
+		lw s1, XCP_S1(AT)
+		lw s2, XCP_S2(AT)
+		lw s3, XCP_S3(AT)
+		lw s4, XCP_S4(AT)
+		lw s5, XCP_S5(AT)
+		lw s6, XCP_S6(AT)
+		lw s7, XCP_S7(AT)
+		lw t8, XCP_T8(AT)
+		lw t9, XCP_T9(AT)
+		lw gp, XCP_GP(AT)
+		lw s8, XCP_S8(AT)
+
+		/* mdhi and mdlo */
+		lw v0, XCP_MDHI(AT)
+		lw v1, XCP_MDLO(AT)
+		mthi v0
+		mtlo v1
+
+		/* remaining general registers */
+		lw a0, XCP_A0(AT)
+		lw a1, XCP_A1(AT)
+		lw a2, XCP_A2(AT)
+		lw a3, XCP_A3(AT)
+		lw ra, XCP_RA(AT)
+
+		/* restore the exception-time status register */
+		.set noreorder
+		lw v0, XCP_SR(AT)
+		nop			
+		mtc0 v0, CP0_SR
+		lw v1, XCP_V1(AT)
+		lw v0, XCP_V0(AT)
+		lw sp, XCP_SP(AT)
+
+		/* we are not uninterruptible and can use k1 safely */
+		lw k1, XCP_EPC(AT)
+		lw AT, XCP_AT(AT)
+		mtc0 k1, CP0_EPC
+		j	k1
+		rfe
+
+		.set reorder
+		.set at
+END(xcptlow_handler)
+		
+
+LEAF(_xcptcall)
+		/* on entry: a0 == &xcp */
+		subu sp, 24
+		sw ra, 16(sp)
+		
+		/* punt out to _xcpt_deliver */
+		jal _xcpt_deliver
+		nop
+		lw ra, 16(sp)
+		addu sp, 24
+		beqz ra, xcptrest
+		nop
+		j ra
+		nop
+END(_xcptcall)	

lib/CPUs/MIPS/bsp/examples/kernel_sim.S

@@ -0,0 +1,260 @@
+		.file	"kernel.s"
+
+		.equ	stack_ptr,		0x7FFFEFFC
+		.equ	baudrate,		0x0D
+		.equ	sys_led_port,	0xA0000000
+		.equ	sys_uart_baud,	0xA0000009
+		.equ	sys_uart_stat,	0xA0000008
+		.equ	sys_uart_data,	0xA0000004
+		.equ	sys_timer_sec,	0xA0000014
+		.equ	sys_timer_usec,	0xA0000010
+
+		.section .kdata,"a"
+		.align	2
+_k_stack:	.space	256, 0
+_k_msg1:	.asciiz	"Exception at "
+_k_msg2:	.asciiz	"EPC      : "
+_k_msg3:	.asciiz	"Cause    : "
+_k_msg4:	.asciiz	"Status   : "
+_k_msg5:	.asciiz	"BadVAddr : "
+_k_crlf:	.asciiz	"\r\n"
+_k_hextbl:	.ascii "0123456789ABCDEF"
+
+		.section .ktext,"ax"
+		.align	2
+		.globl _kputs
+
+		.macro kpush reg
+		addiu	$sp, 4
+		sw		\reg, 0($sp)
+		.endm
+		
+		.macro kpop reg
+		lw		\reg, 0($sp)
+		addiu	$sp, -4
+		.endm
+
+_exc_handler:
+
+		sw		$sp, _k_stack
+		la		$sp, _k_stack
+		kpush	$8
+		kpush	$9
+		kpush	$10
+		kpush	$11
+		kpush	$12
+		kpush	$31
+
+		.set	noreorder
+#		# Get BadVAddr
+#		mfc0	$10, $8
+#		kpush	$10
+#		# Get Status
+#		mfc0	$10, $12
+#		kpush	$10
+#		# Get Cause
+#		mfc0	$10, $13
+#		kpush	$10
+#		srl		$10, 29
+#		andi	$11, $10, 4
+#		# Get EPC
+#		mfc0	$10, $14
+#		kpush	$10
+#
+#		# Get real EPC
+#		addu	$10, $11
+#		kpush	$10
+#		
+#		# set uart
+#		la	$26, sys_uart_baud
+#		addiu	$27, $0, baudrate
+#		sb	$27, 0($26)
+#
+#		# Print CRLF
+#		la		$11, _k_crlf
+#		jal		_kputs
+#		nop
+#
+#		# Print real EPC
+#		la		$11, _k_msg1
+#		jal		_kputs
+#		nop
+#		kpop	$10
+#		jal		_kprint_word		
+#		nop
+#		la		$11, _k_crlf
+#		jal		_kputs
+#		nop
+#		
+#		# Print EPC
+#		la		$11, _k_msg2
+#		jal		_kputs
+#		nop
+#		kpop	$10
+#		jal		_kprint_word		
+#		nop
+#		la		$11, _k_crlf
+#		jal		_kputs
+#		nop
+#		
+#		# Print Cause
+#		la		$11, _k_msg3
+#		jal		_kputs
+#		nop
+#		kpop	$10
+#		jal		_kprint_word		
+#		nop
+#		la		$11, _k_crlf
+#		jal		_kputs
+#		nop
+#		
+#		# Print Status
+#		la		$11, _k_msg4
+#		jal		_kputs
+#		nop
+#		kpop	$10
+#		jal		_kprint_word		
+#		nop
+#		la		$11, _k_crlf
+#		jal		_kputs
+#		nop
+#		
+#		# Print BadVAddr
+#		la		$11, _k_msg5
+#		jal		_kputs
+#		nop
+#		kpop	$10
+#		jal		_kprint_word		
+#		nop
+#		la		$11, _k_crlf
+#		jal		_kputs
+#		nop
+#		
+		# Set Error LED and ExcCode LEDs
+		# Get Cause
+#		mfc0	$26, $13
+#		la 		$27, sys_led_port
+#		srl		$26, 2
+#		andi	$26, 0x000F
+#		or 		$26, $27
+#		sw 		$26, 0($27)
+
+		# wait for all interrupts = 0
+#$w4x:	mfc0	$26, $13
+#		mfc0	$27, $12
+#		srl		$26, 8
+#		srl		$27, 8
+#		and		$26, $27
+#		bnez	$26, $w4x
+		
+		# Get return address
+		mfc0	$26, $14
+
+$no_int:	kpop	$31
+		kpop	$12
+		kpop	$11
+		kpop	$10
+		kpop	$9
+		kpop	$8
+		lw		$sp, _k_stack
+
+		# Return
+		jr	$26
+		rfe
+		.set	reorder
+
+# word = $10
+_kprint_word:
+		.set	noreorder
+		kpush	$31
+		kpush	$10
+		srl		$10, 16
+		jal		_kprint_halfword
+		nop
+		kpop	$10
+		jal		_kprint_halfword
+		nop
+		kpop	$31
+		jr		$31
+		nop
+		.set	noreorder
+		
+# halfword = $10
+_kprint_halfword:
+		.set	noreorder
+		kpush	$31
+		kpush	$10
+		srl		$10, 8
+		jal		_kprint_byte
+		nop
+		kpop	$10
+		jal		_kprint_byte
+		nop
+		kpop	$31
+		jr		$31
+		nop
+		.set	noreorder
+		
+# byte = $10
+_kprint_byte:
+		.set	noreorder
+		kpush	$31
+		kpush	$10
+		srl		$10, 4
+		jal		_kprint_nibble
+		nop
+		kpop	$10
+		jal		_kprint_nibble
+		nop
+		kpop	$31
+		jr		$31
+		nop
+		.set	noreorder
+		
+_kprint_nibble:
+		.set	noreorder
+		kpush	$31
+		kpush	$10
+		la		$12, _k_hextbl
+		andi	$10, 0xF
+		addu	$12, $10
+		lbu		$10, 0($12)
+		jal		_ksaus
+		nop
+		kpop	$10
+		kpop	$31
+		jr		$31
+		nop
+		.set	noreorder
+		
+# char = $10
+_ksaus:
+		.set	noreorder
+		la		$8, sys_uart_stat
+		lbu		$8, 0($8)
+		la		$9, sys_uart_data
+		andi	$8, 0x02
+		bnez	$8, _ksaus
+		nop
+		j		$31
+		sb		$10, 0($9)
+		.set	reorder
+	
+_kputs:
+		.set	noreorder
+		kpush	$11
+		kpush	$31
+$kpl:	lbu		$10, 0($11)
+		addiu	$11, 1
+		blez	$10, $kpex
+		nop
+		jal		_ksaus
+		nop
+		j		$kpl
+		nop
+$kpex:	kpop	$31
+		kpop	$11
+		jr		$31
+		nop		
+		.set	reorder
+