jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
67 Commits 7 Branches 23 Tags
8a8adce98efcd458b35c6e7e5245bec033e2df75
T
Clone
Open with VS Code Open with VSCodium Open with Intellij IDEA
Download ZIP Download TAR.GZ Download BUNDLE
jens 8a8adce98e - using now 64-bit SDR interface (2 SDRAMS) 
git-svn-id: http://moon:8086/svn/vhdl/trunk@74 cc03376c-175c-47c8-b038-4cd826a8556b
2008-10-18 13:31:15 +00:00
lib
- using now 64-bit SDR interface (2 SDRAMS)
2008-10-18 13:31:15 +00:00
projects/mips_sys
- Added VGA master/slave
2008-10-16 23:12:14 +00:00
S
Description
No description provided
23 MiB
Languages
VHDL 90.1%
Verilog 4.2%
Tcl 2.5%
SystemVerilog 0.8%
IGOR Pro 0.5%
Other 1.5%