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- more tests
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git-svn-id: http://moon:8086/svn/vhdl/trunk@602 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-11-04 19:28:52 +00:00
parent 6e1e0e1cd2
commit 7a4dff1301
2 changed files with 220 additions and 20 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/VGA_ctrl/src/tb_vga_frontend.vhd
+110 -10
View File
@@ -173,33 +173,62 @@ STIMULUS: process
RST_O <= '0';
wait for 60*CLK_PERIOD;
-- 8 single cycles
-- Enable master
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"0000_0001";
ADDR_O <= X"0000_0100";
SDAT_O <= X"0000_0002";
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- Read status
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"0000_0000";
WE_O <= '0';
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- Read resolution X
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0018";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- Read resolution Y
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_001C";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- Read Cursor X
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0008";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- Read Cursor Y
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"0000_0000";
ADDR_O <= X"0000_0010";
WE_O <= '0';
ADDR_O <= X"0000_000C";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- Write char 1
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
@@ -208,11 +237,82 @@ STIMULUS: process
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- Read char 1
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0004";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- Write char 2
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"0000_0035";
ADDR_O <= X"0000_0020";
SDAT_O <= X"0000_0045";
ADDR_O <= X"0000_0004";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- Read char 2
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0004";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- Read Cursor X
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0008";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- Read Cursor Y
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_000C";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- Set Cursor X
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"0000_0012";
ADDR_O <= X"0000_0008";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- Set Cursor Y
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"0000_0014";
ADDR_O <= X"0000_000C";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- Read Cursor X
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0008";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- Read Cursor Y
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_000C";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
lib/VGA_ctrl/src/tb_vga_frontend64.vhd
+110 -10
View File
@@ -173,33 +173,62 @@ STIMULUS: process
RST_O <= '0';
wait for 60*CLK_PERIOD;
-- 8 single cycles
-- Enable master
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"0000_0001";
ADDR_O <= X"0000_0100";
SDAT_O <= X"0000_0002";
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- Read status
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"0000_0000";
WE_O <= '0';
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- Read resolution X
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0018";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- Read resolution Y
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_001C";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- Read Cursor X
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0008";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- Read Cursor Y
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"0000_0000";
ADDR_O <= X"0000_0010";
WE_O <= '0';
ADDR_O <= X"0000_000C";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- Write char 1
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
@@ -208,11 +237,82 @@ STIMULUS: process
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- Read char 1
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0004";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- Write char 2
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"0000_0035";
ADDR_O <= X"0000_0020";
SDAT_O <= X"0000_0045";
ADDR_O <= X"0000_0004";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- Read char 2
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0004";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- Read Cursor X
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0008";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- Read Cursor Y
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_000C";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- Set Cursor X
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"0000_0012";
ADDR_O <= X"0000_0008";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- Set Cursor Y
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"0000_0014";
ADDR_O <= X"0000_000C";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- Read Cursor X
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0008";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- Read Cursor Y
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_000C";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';