jens
e8deef86a6
- simplified design Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@853 cc03376c-175c-47c8-b038-4cd826a8556b
443 lines
10 KiB
VHDL
443 lines
10 KiB
VHDL
LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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USE IEEE.MATH_REAL.ALL;
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use std.textio.all; -- Imports the standard textio package.
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use work.emac_types.all;
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use work.utils_pkg.all;
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ENTITY pkt_gen IS
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Generic
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(
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f_sysclk : real := 100.0;
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PKT_DLY_MIN : real := 1.0E-6;
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PKT_DLY_MAX : real := 100.0E-6;
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PKT_SIZE_MIN : natural := 64;
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PKT_SIZE_MAX : natural := 1518
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);
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Port
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(
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clk : in STD_LOGIC;
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rst : in STD_LOGIC;
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mii_tx_clk : in STD_LOGIC;
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mii_tx_en : out STD_LOGIC;
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mii_tx_er : out STD_LOGIC;
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mii_tx : out unsigned(7 downto 0)
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);
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END pkt_gen;
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ARCHITECTURE behavior OF pkt_gen IS
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subtype word_ptr_t is unsigned(15 downto 0);
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signal pkt_data : unsigned(31 downto 0);
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signal pkt_nbytes : word_ptr_t := X"0040";
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signal pkt_nwords : word_ptr_t := X"0010";
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signal pkt_delay : natural := natural(1.0*f_sysclk);
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signal tx_packets : natural;
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signal tx_bytes : natural;
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signal mii_fifo_din : unsigned(35 downto 0);
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signal mii_fifo_dout : unsigned(35 downto 0);
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signal mii_fifo_we : std_logic;
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signal mii_fifo_re : std_logic;
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signal mii_fifo_empty : std_logic;
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signal mii_fifo_full : std_logic;
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signal xfer_size : word_ptr_t;
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signal xfer_ptr : word_ptr_t;
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signal xfer_cnt : word_ptr_t;
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signal xfer_set : std_logic;
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signal xfer_en : std_logic;
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signal xfer_sync : unsigned(1 downto 0);
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signal xfer_cnt_en : std_logic;
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signal xfer_bsy : std_logic;
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signal xfer_pre_rdy : std_logic;
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signal uncommit_en : std_logic;
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signal piso8_din : unsigned(31 downto 0);
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signal piso8_din_be : unsigned(3 downto 0);
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signal piso8_din_rdy : std_logic;
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signal piso8_din_vld : std_logic;
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signal piso8_dout : unsigned(7 downto 0);
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signal piso8_dout_vld : std_logic;
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signal piso8_dout_en : std_logic;
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signal piso4_din_rdy : std_logic;
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signal tx_en : std_logic;
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subtype ifg_cnt_t is natural range 0 to 23; -- 10/100 mbps
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-- subtype ifg_cnt_t is natural range 0 to 11; -- 1000 mbps
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signal ifg_cnt : ifg_cnt_t;
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signal ifg_idle : std_logic;
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type xfer_state_t is (xfer_init, xfer_idle, xfer_setup, xfer_arm, xfer_active, xfer_uncommit, xfer_free);
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signal xfer_s, xfer_sn : xfer_state_t;
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type stream_state_t is (stream_init, stream_idle, stream_start, stream_preamble0, stream_preamble1, stream_active, stream_crc, stream_stop, stream_finish);
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signal stream_s, stream_sn : stream_state_t;
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type piso_byte_mask_array_t is array (0 to 3) of unsigned (3 downto 0);
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constant piso_byte_mask_rom : piso_byte_mask_array_t :=
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(
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"1111",
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"1000",
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"1100",
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"1110"
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);
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signal preamble_en : std_logic;
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signal preamble_addr : natural range 0 to 1;
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type preamble_t is array (0 to 1) of unsigned(31 downto 0);
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constant preamble : preamble_t :=
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(
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X"55555555",
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X"555555D5"
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);
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begin
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mii_tx_er <= '0';
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piso8_din <= preamble(preamble_addr) when preamble_en = '1' else mii_fifo_dout(31 downto 0);
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piso8_din_be <= "1111" when preamble_en = '1' else mii_fifo_dout(35 downto 32);
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mii_fifo_we <= xfer_bsy;
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xfer_cnt_en <= xfer_bsy and not mii_fifo_full;
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mii_fifo_din(35 downto 32) <= piso_byte_mask_rom(to_integer(pkt_nbytes(1 downto 0))) when xfer_pre_rdy = '1' else "1111";
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mii_fifo_din(31 downto 0) <= pkt_data;
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------------------------------------------------------------------
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-- Transfer stuff
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------------------------------------------------------------------
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xfer_state_next:
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process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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xfer_s <= xfer_init;
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else
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xfer_s <= xfer_sn;
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end if;
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end if;
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end process;
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xfer_state:
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process(xfer_s, xfer_bsy, xfer_sync)
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begin
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uncommit_en <= '0';
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xfer_set <= '0';
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xfer_en <= '0';
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xfer_sn <= xfer_s;
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case xfer_s is
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when xfer_init =>
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xfer_sn <= xfer_idle;
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when xfer_idle =>
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xfer_sn <= xfer_setup;
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when xfer_setup =>
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xfer_set <= '1';
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xfer_sn <= xfer_arm;
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when xfer_arm =>
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xfer_en <= '1';
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xfer_sn <= xfer_active;
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when xfer_active =>
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xfer_en <= '1';
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if xfer_bsy = '0' then
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xfer_sn <= xfer_uncommit;
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end if;
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when xfer_uncommit =>
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uncommit_en <= '1';
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xfer_sn <= xfer_free;
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when xfer_free =>
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if xfer_sync(1) = '1' then
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xfer_sn <= xfer_idle;
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end if;
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when others =>
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xfer_sn <= xfer_idle;
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end case;
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end process;
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------------------------------------------------------------------
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interframe_gap_ready:
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process(clk)
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begin
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if rising_edge(clk) then
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xfer_sync(1) <= xfer_sync(0);
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xfer_sync(0) <= mii_fifo_empty;
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end if;
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end process;
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------------------------------------------------------------------
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interframe_gap_counter:
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process(mii_tx_clk)
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begin
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if rising_edge(mii_tx_clk) then
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ifg_idle <= '0';
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if rst = '1' or piso8_dout_vld = '1' then
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ifg_cnt <= ifg_cnt_t'high;
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ifg_idle <= '1';
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elsif ifg_cnt /= 0 then
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ifg_cnt <= ifg_cnt - 1;
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else
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ifg_idle <= '1';
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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pkt_params:
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process(clk)
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variable size : word_ptr_t;
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variable delay : natural;
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variable krand : real;
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variable seed1 : integer;
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variable seed2 : integer;
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begin
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if rising_edge(clk) then
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if rst = '1' then
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size := to_unsigned(PKT_SIZE_MIN, word_ptr_t'length);
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delay := natural(1.0E6*PKT_DLY_MIN*f_sysclk);
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seed1 := 31101970;
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seed2 := 12586901;
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tx_packets <= 0;
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tx_bytes <= 0;
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elsif uncommit_en = '1' then
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uniform(seed1, seed2, krand);
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size := to_unsigned(PKT_SIZE_MIN + natural(real(PKT_SIZE_MAX-PKT_SIZE_MIN)*krand), word_ptr_t'length);
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delay := natural(1.0E6*f_sysclk*(PKT_DLY_MIN + (PKT_DLY_MAX-PKT_DLY_MIN)*krand));
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tx_packets <= tx_packets + 1;
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tx_bytes <= tx_bytes + to_integer(pkt_nbytes);
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end if;
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pkt_delay <= delay;
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pkt_nbytes <= size;
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if size(1 downto 0) = 0 then
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pkt_nwords <= "00" & size(word_ptr_t'left downto 2);
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else
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pkt_nwords <= "00" & size(word_ptr_t'left downto 2) + 1;
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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xfer_counter:
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process(clk)
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begin
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if rising_edge(clk) then
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if xfer_set = '1' then
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xfer_cnt <= pkt_nwords;
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xfer_size <= (others => '0');
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xfer_bsy <= '0';
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xfer_pre_rdy <= '0';
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elsif xfer_en = '1' then
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xfer_bsy <= '1';
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if xfer_cnt_en = '1' or xfer_bsy = '0' then
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if xfer_cnt /= 1 then
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xfer_cnt <= xfer_cnt - 1;
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xfer_size <= xfer_size + 1;
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else
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xfer_pre_rdy <= '1';
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end if;
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if xfer_pre_rdy = '1' then
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xfer_bsy <= '0';
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end if;
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end if;
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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pkt_data_gen:
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process(clk)
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variable data : unsigned(7 downto 0);
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begin
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if rising_edge(clk) then
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if xfer_set = '1' then
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data := (others => '0');
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elsif xfer_cnt_en = '1' or xfer_bsy = '0' then
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pkt_data(7 downto 0) <= data;
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data := data + 1;
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pkt_data(15 downto 8) <= data;
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data := data + 1;
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pkt_data(23 downto 16) <= data;
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data := data + 1;
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pkt_data(31 downto 24) <= data;
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data := data + 1;
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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stream_state_next:
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process(mii_tx_clk)
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begin
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if rising_edge(mii_tx_clk) then
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if rst = '1' then
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stream_s <= stream_init;
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else
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stream_s <= stream_sn;
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end if;
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end if;
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end process;
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stream_state:
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process(stream_s, ifg_idle, mii_fifo_empty, piso8_din_rdy, piso8_dout_vld)
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begin
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piso8_din_vld <= '0';
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mii_fifo_re <= '0';
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preamble_en <= '0';
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preamble_addr <= 0;
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stream_sn <= stream_s;
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case stream_s is
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when stream_init =>
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if mii_fifo_empty = '1' then
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stream_sn <= stream_idle;
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end if;
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when stream_idle =>
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if mii_fifo_empty = '0' and piso8_din_rdy = '1' then
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stream_sn <= stream_start;
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end if;
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when stream_start =>
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stream_sn <= stream_preamble0;
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when stream_preamble0 =>
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preamble_addr <= 0;
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preamble_en <= '1';
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piso8_din_vld <= '1';
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if piso8_din_rdy = '1' then
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stream_sn <= stream_preamble1;
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end if;
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when stream_preamble1 =>
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preamble_addr <= 1;
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preamble_en <= '1';
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piso8_din_vld <= '1';
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if piso8_din_rdy = '1' then
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stream_sn <= stream_active;
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end if;
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when stream_active =>
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piso8_din_vld <= not mii_fifo_empty;
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mii_fifo_re <= piso8_din_rdy;
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if mii_fifo_empty = '1' then
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stream_sn <= stream_crc;
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end if;
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when stream_crc =>
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stream_sn <= stream_stop;
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when stream_stop =>
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if piso8_dout_vld = '0' then
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stream_sn <= stream_finish;
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end if;
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when stream_finish =>
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if ifg_idle = '0' then
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stream_sn <= stream_idle;
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end if;
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when others =>
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stream_sn <= stream_idle;
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end case;
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end process;
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------------------------------------------------------------------
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-- Instantiate synchronous FIFO
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inst_mii_fifo: entity work.fifo_async
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GENERIC MAP
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(
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addr_width => 4,
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data_width => mii_fifo_din'length,
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do_last_read_update => true
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)
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PORT MAP
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(
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rst => rst,
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clk_w => clk,
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clk_r => mii_tx_clk,
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we => mii_fifo_we,
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re => mii_fifo_re,
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fifo_full => mii_fifo_full,
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fifo_empty => mii_fifo_empty,
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fifo_afull => open,
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fifo_aempty => open,
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data_w => mii_fifo_din,
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data_r => mii_fifo_dout
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);
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inst_piso : entity work.piso
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GENERIC MAP
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(
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data_width_in => 32,
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data_width_out => 8,
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msb_first => true
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)
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PORT MAP
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(
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rst => rst,
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clk => mii_tx_clk,
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din_vld => piso8_din_vld,
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din_rdy => piso8_din_rdy,
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din_be => piso8_din_be,
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din => piso8_din,
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dout_vld => piso8_dout_vld,
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dout_en => piso8_dout_en,
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dout => piso8_dout
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);
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piso8_dout_en <= piso4_din_rdy and ifg_idle;
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inst_piso_10mbps : entity work.piso
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GENERIC MAP
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(
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data_width_in => 8,
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data_width_out => 4,
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msb_first => false
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)
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PORT MAP
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(
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rst => rst,
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clk => mii_tx_clk,
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din_vld => piso8_dout_vld,
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din_rdy => piso4_din_rdy,
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din_be => "11",
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din => piso8_dout,
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dout_vld => tx_en,
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dout_en => '1',
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dout => mii_tx(3 downto 0)
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);
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mii_tx_en <= tx_en;
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mii_tx(7 downto 4) <= "0000";
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end behavior;
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