- Reset vector is now injected during reset like an ordinary exception.
This minimizes pc.nxt MUX (Better timing) Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@475 cc03376c-175c-47c8-b038-4cd826a8556b
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@@ -79,6 +79,8 @@ architecture Behavioral of cop is
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signal dcache_info : unsigned(7 downto 0);
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signal reg_rptr : reg_ptr_t;
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signal reg_wptr : reg_ptr_t;
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signal inject_exc : STD_LOGIC;
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signal inject_rst : STD_LOGIC;
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type cop_pipe_t is record
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opc : opcode_t;
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@@ -128,7 +130,7 @@ begin
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cop_pipe_ID.RFE <= cop_pipe_ID.cs when (cop_pipe_ID.CO = '1' and cop_pipe_ID.func = "010000") else '0';
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ctrl_out.EB <= EB_reg xor (status(25) and status(1));
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ctrl_out.user_mode <= status(1);
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ctrl_out.exc_inject <= inject_exc or inject_rst;
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cop_pipe_ID.reg_ptr <= cop_pipe_ID.rd when cop_pipe_ID.opc = "010000" else cop_pipe_ID.rt;
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im <= status(15 downto 8);
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@@ -148,7 +150,6 @@ exception_state:
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process(exc_state, ctrl_in, cop_pipe_ID)
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begin
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ctrl_out.exc_inject <= '0';
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ctrl_out.exc_commit <= '0';
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ctrl_out.exc_pending <= '0';
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ctrl_out.exc_exit <= '0';
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@@ -156,6 +157,7 @@ exception_state:
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code_reg_we <= '0';
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status_save <= '0';
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status_rest <= '0';
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inject_exc <= '0';
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imem_addr_we <= '0';
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exc_staten <= exc_state;
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@@ -165,8 +167,8 @@ exception_state:
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when exc_idle =>
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if cop_pipe_ID.RFE = '1' then
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exc_staten <= exc_leave;
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ctrl_out.exc_exit <= '1';
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ctrl_out.exc_commit <= '1';
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ctrl_out.exc_exit <= '1';
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ctrl_out.exc_commit <= '1';
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elsif ctrl_in.exc_req = '1' then
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exc_staten <= exc_pipe_flush;
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imem_addr_we <= '1';
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@@ -188,11 +190,11 @@ exception_state:
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when exc_inject =>
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ctrl_out.exc_pending <= '1';
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ctrl_out.exc_inject <= '1';
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ctrl_out.exc_commit <= '1';
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code_reg_we <= '1';
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status_save <= '1';
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epc_reg_we <= '1';
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inject_exc <= '1';
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exc_staten <= exc_enter;
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when exc_enter =>
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@@ -349,9 +351,15 @@ cop_exc_vector:
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process(clk)
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begin
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if rising_edge(clk) then
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ctrl_out.exc_vec <= X"80000080";
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if status(22) = '1' then
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ctrl_out.exc_vec <= X"BFC00180";
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if rst = '1' then
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inject_rst <= '1';
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ctrl_out.exc_vec <= X"BFC00000";
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else
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inject_rst <= '0';
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ctrl_out.exc_vec <= X"80000080";
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if status(22) = '1' then
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ctrl_out.exc_vec <= X"BFC00180";
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end if;
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end if;
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end if;
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end process;
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@@ -409,9 +417,6 @@ cop_register_read:
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end process;
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-- 18296365000 ps
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-- 20158175000 ps
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cop_we_gen:
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process(clk)
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begin
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@@ -144,8 +144,6 @@ architecture Behavioral of pipeline is
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END COMPONENT;
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--------------------------------------------------------------------------
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constant RESET_VECTOR : word_t := X"BFC00000";
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signal ID_stage : ID_t;
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signal EX_stage : EX_t;
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signal MEM_stage : MEM_t;
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@@ -173,11 +171,6 @@ architecture Behavioral of pipeline is
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signal stage_rst : unsigned(3 downto 0);
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signal pipe_rst : STD_LOGIC;
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attribute ram_style : string;
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attribute ram_style of reg_a: signal is "distributed";
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attribute ram_style of reg_b: signal is "distributed";
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signal pc : pc_t;
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--------------------------------------------------------------------------
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@@ -279,28 +272,35 @@ proc_stage_pc_branch:
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end if;
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end process;
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proc_stage_pc_next:
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proc_stage_branch_ce:
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process(clk_1)
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begin
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if rising_edge(clk_1) then
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if pipe_rst = '1' then
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pc.nxt <= RESET_VECTOR;
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pc.last <= RESET_VECTOR;
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branch_ce <= '1';
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else
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branch_ce <= c0_ctrl_in.exc_pending;
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if c0_ctrl_in.exc_inject = '1' then
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pc.nxt <= c0_ctrl_in.exc_vec;
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elsif sdu.ID_stall = '0' then
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if sdu.ID_stall = '0' then
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branch_ce <= '1';
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pc.last <= pc.curr;
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if ID_stage.ctrl.jump = '1' then
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pc.nxt <= ID_stage.jimm32;
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elsif ID_stage.ctrl.jump_long = '1' then
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pc.nxt <= ID_stage.reg_a;
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else
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pc.nxt <= pc.curr + 4;
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end if;
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end if;
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end if;
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end if;
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end process;
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proc_stage_pc_next:
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process(clk_1)
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begin
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if rising_edge(clk_1) then
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if c0_ctrl_in.exc_inject = '1' then
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pc.nxt <= c0_ctrl_in.exc_vec;
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elsif sdu.ID_stall = '0' then
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pc.last <= pc.curr;
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if ID_stage.ctrl.jump = '1' then
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pc.nxt <= ID_stage.jimm32;
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elsif ID_stage.ctrl.jump_long = '1' then
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pc.nxt <= ID_stage.reg_a;
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else
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pc.nxt <= pc.curr + 4;
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end if;
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end if;
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end if;
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