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- removed BUFG for clk_out. It's now in clkgen

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git-svn-id: http://moon:8086/svn/vhdl/trunk@598 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-11-04 10:39:59 +00:00
parent 05a24f5fda
commit 57efb02eb6
1 changed files with 3 additions and 11 deletions
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projects/mips_sys/src/mips_sys.vhd
+3 -11
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@@ -319,7 +319,6 @@ ARCHITECTURE behavior OF mips_sys IS
signal sdram_clk270 : std_logic;
signal sdram_clk270var : std_logic;
signal vga_clk : std_logic;
signal vga_clk_prebuf : std_logic;
signal vga_clk_lock : std_logic;
signal rst_in : std_logic;
signal int_timer : std_logic;
@@ -342,8 +341,8 @@ ARCHITECTURE behavior OF mips_sys IS
signal arb_gnt : unsigned (ARB_MAX_MASTER-1 downto 0);
-- J-Bus signals
signal CLK_O : std_logic;
signal RST_O : std_logic;
signal CLK_O : std_logic;
signal RST_O : std_logic;
signal INT : unsigned(5 downto 0);
signal MDAT_I : word_t;
signal MDAT_O : word_t;
@@ -883,17 +882,10 @@ inst_clkgen: entity work.clkgen
(
rst => rst_in,
clk_in => CLK_O,
clk_out => vga_clk_prebuf,
clk_out => vga_clk,
locked => vga_clk_lock
);
BUFG_out_clk : BUFG
port map
(
O => vga_clk, -- Clock buffer output
I => vga_clk_prebuf -- Clock buffer input
);
inst_vga_frontend : vga_frontend64
GENERIC MAP
(