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git-svn-id: http://moon:8086/svn/vhdl/trunk@42 cc03376c-175c-47c8-b038-4cd826a8556b
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-----------------------------------------------------------------------
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-- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port.vhd,v 1.2 2008-10-10 21:25:17 Jens Exp $
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-----------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use work.sys_types.all;
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------------------------------------------------------------------
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entity async_port is
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Generic
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(
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addr_width : natural := 32;
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data_width : natural := 32;
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async_timespec : async_timespec_t
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);
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Port
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(
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rst : in std_logic;
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clk : in std_logic;
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cpu_en : in std_logic;
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cpu_re : in std_logic;
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cpu_addr : in unsigned(addr_width-1 downto 0);
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cpu_din : out unsigned(data_width-1 downto 0);
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cpu_dout : in unsigned(data_width-1 downto 0);
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cpu_bsy : out std_logic;
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cpu_vld : out std_logic;
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async_a : out unsigned(addr_width-1 downto 0);
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async_d : inout unsigned(data_width-1 downto 0);
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async_cs : out std_logic;
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async_wr : out std_logic;
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async_rd : out std_logic;
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async_rst : out std_logic
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);
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end async_port;
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architecture Behavioral of async_port is
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type async_t is record
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cs : std_logic;
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wr : std_logic;
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rd : std_logic;
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rst : std_logic;
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drive_d : std_logic;
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end record;
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type async_state_t is (start, reset, rdy, leadin_rd, read, leadin_wr, write, leadout_rd, leadout_wr, release);
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signal s, sn : async_state_t;
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signal as : async_t;
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signal cc_rst : std_logic;
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signal cycle_cnt : natural range 0 to 15;
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signal cycle_reload : natural range 0 to 15;
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------------------------------------------------------------------
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begin
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proc_cycle_counter:
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process(clk)
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begin
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if rising_edge(clk) then
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if cc_rst = '1' then
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cycle_cnt <= cycle_reload;
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elsif cycle_cnt /= 0 then
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cycle_cnt <= cycle_cnt - 1;
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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proc_state_next:
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process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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s <= start;
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else
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s <= sn;
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end if;
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end if;
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end process;
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proc_state:
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process(s, cycle_cnt, cpu_en)
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begin
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cycle_reload <= async_timespec.ncyc_pulse_rst;
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cc_rst <= '0';
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as.rst <= '0';
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as.cs <= '0';
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as.wr <= '0';
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as.rd <= '0';
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as.drive_d <= '0';
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cpu_bsy <= '1';
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cpu_vld <= '0';
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sn <= s;
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case s is
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when start =>
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cc_rst <= '1';
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sn <= reset;
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when reset =>
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as.rst <= '1';
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if cycle_cnt = 0 then
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sn <= rdy;
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end if;
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when rdy =>
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cpu_bsy <= '0';
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if cpu_en = '1' then
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as.cs <= '1';
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cc_rst <= '1';
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cycle_reload <= async_timespec.ncyc_access-1;
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if cpu_re = '1' then
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sn <= leadin_rd;
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else
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sn <= leadin_wr;
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end if;
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end if;
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when leadin_rd =>
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as.cs <= '1';
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if cycle_cnt = 0 then
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cc_rst <= '1';
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cycle_reload <= async_timespec.ncyc_pulse_rd-1;
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as.rd <= '1';
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sn <= read;
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end if;
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when leadin_wr =>
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as.cs <= '1';
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if cycle_cnt = 0 then
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cc_rst <= '1';
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cycle_reload <= async_timespec.ncyc_pulse_wr-1;
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as.wr <= '1';
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as.drive_d <= '1';
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sn <= write;
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end if;
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when read =>
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as.cs <= '1';
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as.rd <= '1';
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if cycle_cnt = 0 then
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cc_rst <= '1';
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cycle_reload <= async_timespec.ncyc_cs_hold-1;
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as.rd <= '0';
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sn <= leadout_rd;
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cpu_vld <= '1';
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end if;
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when write =>
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as.drive_d <= '1';
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as.cs <= '1';
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as.wr <= '1';
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if cycle_cnt = 0 then
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as.wr <= '0';
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cc_rst <= '1';
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cycle_reload <= async_timespec.ncyc_cs_hold-1;
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sn <= leadout_wr;
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cpu_vld <= '1';
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end if;
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when leadout_rd =>
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as.cs <= '1';
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if cycle_cnt = 0 then
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cc_rst <= '1';
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cycle_reload <= async_timespec.ncyc_release-1;
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sn <= release;
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as.cs <= '0';
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end if;
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when leadout_wr =>
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as.cs <= '1';
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as.drive_d <= '1';
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if cycle_cnt = 0 then
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cc_rst <= '1';
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cycle_reload <= async_timespec.ncyc_release-1;
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sn <= release;
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as.cs <= '0';
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end if;
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when release =>
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if cycle_cnt = 0 then
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sn <= rdy;
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end if;
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when others =>
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sn <= rdy;
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end case;
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end process;
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------------------------------------------------------------------
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output_ctrl:
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process(clk)
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begin
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if rising_edge(clk) then
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async_cs <= (not async_timespec.pol_cs) xor as.cs;
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async_wr <= (not async_timespec.pol_we) xor as.wr;
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async_rd <= (not async_timespec.pol_oe) xor as.rd;
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async_rst <= (not async_timespec.pol_rst) xor as.rst;
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end if;
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end process;
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------------------------------------------------------------------
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din_register:
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process(clk)
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begin
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if rising_edge(clk) then
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if as.rd = '1' then
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cpu_din <= async_d;
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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output_addr:
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process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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async_a <= (others => '0');
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elsif cpu_en = '1' then
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async_a <= cpu_addr;
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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output_data:
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process(clk)
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begin
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if rising_edge(clk) then
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async_d <= (others => 'Z');
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if as.drive_d = '1' then
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async_d <= cpu_dout;
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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end Behavioral;
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@@ -1,77 +0,0 @@
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-----------------------------------------------------------------------
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-- $Header: /tmp/cvsroot/VHDL/lib/misc/hpi_port.vhd,v 1.1 2008-09-04 17:48:15 Jens Exp $
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-----------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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------------------------------------------------------------------
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entity hpi_port is
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Port (
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rst : in std_logic;
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clk : in std_logic;
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we : in std_logic;
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din : in unsigned(31 downto 0);
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dout : out unsigned(31 downto 0);
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hpi_d : inout unsigned(15 downto 0);
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hpi_a : out unsigned(1 downto 0);
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hpi_csn : out std_logic;
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hpi_wrn : out std_logic;
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hpi_rdn : out std_logic
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);
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end hpi_port;
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architecture Behavioral of hpi_port is
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type hpi_t is record
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d : unsigned(15 downto 0);
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a : unsigned(1 downto 0);
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cs : std_logic;
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wr : std_logic;
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rd : std_logic;
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drive_d : std_logic;
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end record;
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------------------------------------------------------------------
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begin
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proc_lcd_port:
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process(rst, clk)
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variable vhpi : hpi_t;
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begin
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if (rst = '1') then
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dout <= (others => '0');
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vhpi.d := (others => '0');
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vhpi.a := (others => '0');
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vhpi.cs := '0';
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vhpi.wr := '0';
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vhpi.rd := '0';
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vhpi.drive_d := '0';
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elsif rising_edge(clk) then
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dout <= X"0000" & hpi_d;
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if we = '1' then
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vhpi.d := din(15 downto 0);
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vhpi.a := din(17 downto 16);
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vhpi.cs := din(18);
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vhpi.wr := din(19);
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vhpi.rd := din(20);
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vhpi.drive_d := din(21);
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end if;
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end if;
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if vhpi.cs = '1' then
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hpi_a <= vhpi.a;
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else
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hpi_a <= (others => 'Z');
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end if;
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if vhpi.drive_d = '1' and vhpi.rd = '0' then
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hpi_d <= vhpi.d;
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else
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hpi_d <= (others => 'Z');
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end if;
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hpi_csn <= not vhpi.cs;
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hpi_wrn <= not vhpi.wr;
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hpi_rdn <= not vhpi.rd;
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end process;
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------------------------------------------------------------------
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end Behavioral;
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