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- added f_syscll_hz generic

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git-svn-id: http://moon:8086/svn/vhdl/trunk@732 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-02-08 07:08:32 +00:00
parent 06c9683eea
commit f6be505eba
1 changed files with 6 additions and 1 deletions
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lib/misc/gpio_wb.vhd
+6 -1
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@@ -3,6 +3,10 @@ USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY gpio_wb IS
Generic
(
f_sysclk_hz : natural := 100E6
);
Port
(
CLK_I : in STD_LOGIC;
@@ -30,13 +34,14 @@ END gpio_wb;
ARCHITECTURE behavior OF gpio_wb IS
constant num_timers : natural := 2;
constant ncycles_usec : natural := f_sysclk_hz/1E6;
signal gpo0_reg : unsigned(31 downto 0);
signal gpo1_reg : unsigned(31 downto 0);
signal gpi0_reg : unsigned(31 downto 0);
signal gpi1_reg : unsigned(31 downto 0);
-- Signals to form an timer generating an interrupt every microsecond
subtype tick_usec_t is natural range 0 to 99;
subtype tick_usec_t is natural range 0 to ncycles_usec-1;
signal tick_usec : tick_usec_t;
signal cnt_usec : unsigned(31 downto 0);
signal cnt_sec : unsigned(31 downto 0);