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- uses ieee_proposed.fixed_pkg

Browse Source 
- din scaled to more fraction precision at integrator input.
  Number of integer bits are the same as din
- min_gain intrduced (reduces complexity of barrel shifter).
 Din always constant scaled by min_gain.


git-svn-id: http://moon:8086/svn/vhdl/trunk@172 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2008-12-30 06:03:56 +00:00
parent 75f8ddd340
commit 61d5c40cd2
5 changed files with 119 additions and 94 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/radio/ddc/src/ddc.vhd
+18 -15
View File
@@ -16,8 +16,11 @@ use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
USE ieee.numeric_std.ALL;
library ieee_proposed;
use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all;
library work;
use work.fixed_pkg.all;
use work.fixed_util_pkg.all;
ENTITY ddc IS
@@ -32,8 +35,8 @@ ENTITY ddc IS
cic_nstages : integer := 3;
cic_max_ratio : integer := 4096;
cic_max_diff_delay : integer := 2;
cic_max_width : integer := 32;
cic_max_width_frac : integer := 20
cic_scale_nbits_min : integer := 9;
cic_scale_nbits_max : integer := 32
);
PORT
(
@@ -45,7 +48,7 @@ ENTITY ddc IS
lo_phase_in : in unsigned(lo_nbits_phase-1 downto 0);
cic_ratio : in natural range 1 to cic_max_ratio;
cic_diff_delay : in natural range 1 to cic_max_diff_delay;
cic_shift_in : in natural range 0 to cic_max_width-1;
cic_shift_in : in natural range 0 to cic_scale_nbits_max;
din_i : in sfixed;
din_q : in sfixed;
dout_i : out sfixed;
@@ -89,10 +92,10 @@ ARCHITECTURE behavior OF ddc IS
GENERIC
(
nstages : integer;
max_ratio : integer;
ratio_max : integer;
scale_nbits_min : integer;
scale_nbits_max : integer;
max_diff_delay : integer;
max_width : integer;
max_width_frac : integer;
in_width : integer;
in_width_frac : integer;
out_width : integer;
@@ -103,9 +106,9 @@ ARCHITECTURE behavior OF ddc IS
clk : in std_logic;
rst : in std_logic;
vld_in : in std_logic;
ratio : in natural range 1 to max_ratio;
ratio : in natural range 1 to ratio_max;
diff_delay : in natural range 1 to max_diff_delay;
shift_in : in natural range 0 to max_width-1;
shift_in : in natural range 0 to scale_nbits_max;
din : in sfixed;
dout : out sfixed;
vld_out : out std_logic
@@ -168,10 +171,10 @@ BEGIN
GENERIC MAP
(
nstages => cic_nstages,
max_ratio => cic_max_ratio,
ratio_max => cic_max_ratio,
scale_nbits_min => cic_scale_nbits_min,
scale_nbits_max => cic_scale_nbits_max,
max_diff_delay => cic_max_diff_delay,
max_width => cic_max_width,
max_width_frac => cic_max_width_frac,
in_width => cic_nbits_in,
in_width_frac => cic_nbits_in_frac,
out_width => cic_nbits_out,
@@ -194,10 +197,10 @@ BEGIN
GENERIC MAP
(
nstages => cic_nstages,
max_ratio => cic_max_ratio,
ratio_max => cic_max_ratio,
scale_nbits_min => cic_scale_nbits_min,
scale_nbits_max => cic_scale_nbits_max,
max_diff_delay => cic_max_diff_delay,
max_width => cic_max_width,
max_width_frac => cic_max_width_frac,
in_width => cic_nbits_in,
in_width_frac => cic_nbits_in_frac,
out_width => cic_nbits_out,
lib/radio/ddc/src/syn_ddc.vhd
+12 -9
View File
@@ -16,8 +16,11 @@ use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
USE ieee.numeric_std.ALL;
library ieee_proposed;
use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all;
library work;
use work.fixed_pkg.all;
use work.fixed_util_pkg.all;
use work.cordic_pkg.all;
@@ -33,8 +36,8 @@ use work.cordic_pkg.all;
cic_nstages : integer := 3;
cic_max_ratio : integer := 1024;
cic_max_diff_delay : integer := 2;
cic_max_width : integer := 48;
cic_max_width_frac : integer := 16
cic_scale_nbits_min : integer := 9;
cic_scale_nbits_max : integer := 32
);
PORT
(
@@ -46,7 +49,7 @@ use work.cordic_pkg.all;
lo_phase_in : in unsigned(lo_nbits_phase-1 downto 0);
cic_ratio : in natural range 1 to cic_max_ratio;
cic_diff_delay : in natural range 1 to cic_max_diff_delay;
cic_shift_in : in natural range 0 to cic_max_width-1;
cic_shift_in : in natural range 0 to cic_scale_nbits_max;
din_i : in signed(nbits_in-1 downto 0);
din_q : in signed(nbits_in-1 downto 0);
dout_i : out signed(nbits_out-1 downto 0);
@@ -71,8 +74,8 @@ ARCHITECTURE behavior OF syn_ddc IS
cic_nstages : integer;
cic_max_ratio : integer;
cic_max_diff_delay : integer;
cic_max_width : integer;
cic_max_width_frac : integer
cic_scale_nbits_min : integer;
cic_scale_nbits_max : integer
);
PORT
(
@@ -84,7 +87,7 @@ ARCHITECTURE behavior OF syn_ddc IS
lo_phase_in : in unsigned(lo_nbits_phase-1 downto 0);
cic_ratio : in natural range 1 to cic_max_ratio;
cic_diff_delay : in natural range 1 to cic_max_diff_delay;
cic_shift_in : in natural range 0 to cic_max_width-1;
cic_shift_in : in natural range 0 to cic_scale_nbits_max;
din_i : in sfixed;
din_q : in sfixed;
dout_i : out sfixed;
@@ -115,8 +118,8 @@ BEGIN
cic_nstages => cic_nstages,
cic_max_ratio => cic_max_ratio,
cic_max_diff_delay => cic_max_diff_delay,
cic_max_width => cic_max_width,
cic_max_width_frac => cic_max_width_frac
cic_scale_nbits_min => cic_scale_nbits_min,
cic_scale_nbits_max => cic_scale_nbits_max
)
PORT MAP
(
lib/radio/ddc/src/tb_ddc.vhd
+12 -9
View File
@@ -17,8 +17,11 @@ use IEEE.MATH_REAL.ALL;
USE ieee.numeric_std.ALL;
use std.textio.all; -- Imports the standard textio package.
library ieee_proposed;
use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all;
library work;
use work.fixed_pkg.all;
use work.fixed_util_pkg.all;
use work.cordic_pkg.all;
use work.PCK_FIO.all;
@@ -35,8 +38,8 @@ ENTITY tb_ddc IS
cic_nstages : integer := 3;
cic_max_ratio : integer := 4096;
cic_max_diff_delay : integer := 1;
cic_max_width : integer := 36;
cic_max_width_frac : integer := 16;
cic_scale_nbits_min : integer := 9;
cic_scale_nbits_max : integer := 32;
rfgen_nbits_phase : integer := 20;
rfgen_nbits_freq : integer := 20
);
@@ -57,8 +60,8 @@ ARCHITECTURE behavior OF tb_ddc IS
cic_nstages : integer;
cic_max_ratio : integer;
cic_max_diff_delay : integer;
cic_max_width : integer;
cic_max_width_frac : integer
cic_scale_nbits_min : integer;
cic_scale_nbits_max : integer
);
PORT
(
@@ -70,7 +73,7 @@ ARCHITECTURE behavior OF tb_ddc IS
lo_phase_in : in unsigned(lo_nbits_phase-1 downto 0);
cic_ratio : in natural range 1 to cic_max_ratio;
cic_diff_delay : in natural range 1 to cic_max_diff_delay;
cic_shift_in : in natural range 0 to cic_max_width-1;
cic_shift_in : in natural range 0 to cic_scale_nbits_max;
din_i : in sfixed;
din_q : in sfixed;
dout_i : out sfixed;
@@ -130,7 +133,7 @@ ARCHITECTURE behavior OF tb_ddc IS
SIGNAL ddc_phase_in : unsigned(lo_nbits_phase-1 downto 0) := (others => '0');
SIGNAL ddc_diff_delay : natural := 1;
SIGNAL ddc_ratio : natural := 64;
SIGNAL ddc_shift_in : natural := 18;
SIGNAL ddc_shift_in : natural := 18-cic_scale_nbits_min;
--Outputs
SIGNAL ddc_din_i : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
@@ -187,8 +190,8 @@ BEGIN
cic_nstages => cic_nstages,
cic_max_ratio => cic_max_ratio,
cic_max_diff_delay => cic_max_diff_delay,
cic_max_width => cic_max_width,
cic_max_width_frac => cic_max_width_frac
cic_scale_nbits_min => cic_scale_nbits_min,
cic_scale_nbits_max => cic_scale_nbits_max
)
PORT MAP
(
lib/radio/decimator/CIC/src/cic_decim_pipe.vhd
+57 -44
View File
@@ -16,18 +16,22 @@ use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
USE ieee.numeric_std.ALL;
library ieee_proposed;
use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all;
library work;
use work.fixed_pkg.all;
use work.fixed_util_pkg.all;
use work.utils_pkg.all;
ENTITY cic_decim_pipe IS
Generic
(
nstages : integer := 3;
max_ratio : integer := 64;
max_diff_delay : integer := 2;
max_width : integer := 32;
max_width_frac : integer := 20;
ratio_max : integer := 64;
scale_nbits_min : integer := 9;
scale_nbits_max : integer := 24;
in_width : integer := 32;
in_width_frac : integer := 20;
out_width : integer := 32;
@@ -38,9 +42,9 @@ ENTITY cic_decim_pipe IS
clk : in std_logic;
rst : in std_logic;
vld_in : in std_logic;
ratio : in natural range 1 to max_ratio;
ratio : in natural range 1 to ratio_max;
diff_delay : in natural range 1 to max_diff_delay;
shift_in : in natural range 0 to max_width-1;
shift_in : in natural range 0 to scale_nbits_max;
din : in sfixed;
dout : out sfixed;
vld_out : out std_logic
@@ -53,11 +57,7 @@ ARCHITECTURE behavior OF cic_decim_pipe IS
GENERIC
(
max_width : integer;
max_width_frac : integer;
in_width : integer;
in_width_frac : integer;
out_width : integer;
out_width_frac : integer
max_width_frac : integer
);
PORT
(
@@ -75,11 +75,7 @@ ARCHITECTURE behavior OF cic_decim_pipe IS
(
max_diff_delay : integer;
max_width : integer;
max_width_frac : integer;
in_width : integer;
in_width_frac : integer;
out_width : integer;
out_width_frac : integer
max_width_frac : integer
);
PORT
(
@@ -93,41 +89,70 @@ ARCHITECTURE behavior OF cic_decim_pipe IS
);
END COMPONENT;
subtype word_i_t is sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
constant min_gain_bits : natural := scale_nbits_min;
constant max_gain_bits : natural := natural(NextExpBaseTwo(real(ratio_max)**real(nstages)));
constant integ_nbits : natural := in_width + max_gain_bits;
constant integ_nbits_frac : natural := integ_nbits - (in_width - in_width_frac);
constant comb_nbits : natural := out_width + 1;
constant comb_nbits_frac : natural := out_width_frac + 1;
subtype word_i_t is sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac));
type word_i_pipe_t is array (0 to nstages) of word_i_t;
signal word_i_pipe : word_i_pipe_t;
signal vld_i_pipe : unsigned (0 to nstages);
signal vld_i : std_logic;
subtype word_c_t is sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
subtype word_c_t is sfixed(shi(comb_nbits, comb_nbits_frac) downto slo(comb_nbits, comb_nbits_frac));
type word_c_pipe_t is array (0 to nstages) of word_c_t;
signal word_c_pipe : word_c_pipe_t;
signal vld_c_pipe : unsigned (0 to nstages);
signal vld_c : std_logic;
signal resample_cnt : natural range 1 to max_ratio;
signal resample_cnt : natural range 1 to ratio_max;
signal resample_vld : std_logic;
signal x : sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac));
signal xs : sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac));
signal xsi : sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac));
BEGIN
word_i_pipe(0) <= resize(din, shi(max_width, max_width_frac), slo(max_width, max_width_frac));
vld_i_pipe(0) <= vld_in;
assert false report "min_gain_bits = " & natural'image(min_gain_bits) & "." severity note;
assert false report "max_gain_bits = " & natural'image(max_gain_bits) & "." severity note;
assert false report "integ. prec. = " & natural'image(integ_nbits) & ":" & natural'image(integ_nbits_frac) & "." severity note;
assert false report "comb prec. = " & natural'image(comb_nbits) & ":" & natural'image(comb_nbits_frac) & "." severity note;
vld_i <= vld_i_pipe(nstages);
x <= resize(din, x);
xs <= x sra min_gain_bits;
xsi <= xs sra shift_in;
word_i_pipe(0) <= xsi;
vld_i_pipe(0) <= vld_in;
-- input_scale:
-- process(clk)
-- variable x : sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac));
-- variable xs : sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac));
-- variable xsi : sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac));
-- begin
-- if rising_edge(clk) then
-- end if;
-- end process;
gen_i_stages:
for i in 1 to nstages generate
begin
inst_cic_i_pipe: cic_i_pipe
GENERIC MAP
(
max_width => max_width,
max_width_frac => max_width_frac,
in_width => max_width,
in_width_frac => max_width_frac,
out_width => max_width,
out_width_frac => max_width_frac
max_width => integ_nbits,
max_width_frac => integ_nbits_frac
)
PORT MAP
(
@@ -140,7 +165,7 @@ BEGIN
);
end generate;
word_c_pipe(0) <= word_i_pipe(nstages);
word_c_pipe(0) <= resize(word_i_pipe(nstages), word_c_pipe(0));
vld_c_pipe(0) <= resample_vld;
vld_c <= vld_c_pipe(nstages);
@@ -153,12 +178,8 @@ BEGIN
GENERIC MAP
(
max_diff_delay => max_diff_delay,
max_width => max_width,
max_width_frac => max_width_frac,
in_width => max_width,
in_width_frac => max_width_frac,
out_width => max_width,
out_width_frac => max_width_frac
max_width => comb_nbits,
max_width_frac => comb_nbits_frac
)
PORT MAP
(
@@ -190,14 +211,6 @@ resampler_proc:
end if;
end process;
dout_registers:
process(clk)
variable y : sfixed(shi(out_width, out_width_frac) downto slo(out_width, out_width_frac));
begin
if rising_edge(clk) then
y := resize(word_c_pipe(nstages) sra shift_in, y);
dout <= y;
end if;
end process;
dout <= resize(word_c_pipe(nstages), shi(out_width, out_width_frac), slo(out_width, out_width_frac));
END;
lib/radio/decimator/CIC/src/tb_cic_decim_pipe.vhd
+20 -17
View File
@@ -17,19 +17,22 @@ use IEEE.MATH_REAL.ALL;
USE ieee.numeric_std.ALL;
use std.textio.all; -- Imports the standard textio package.
library ieee_proposed;
use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all;
library work;
use work.PCK_FIO.all;
use work.fixed_pkg.all;
use work.fixed_util_pkg.all;
ENTITY tb_cic_decim_pipe IS
Generic
(
nstages : integer := 3;
max_ratio : integer := 4096;
ratio_max : integer := 1024;
scale_nbits_min : integer := 9;
scale_nbits_max : integer := 32;
max_diff_delay : integer := 2;
max_width : integer := 36;
max_width_frac : integer := 16;
in_width : integer := 18;
in_width_frac : integer := 16;
out_width : integer := 18;
@@ -44,10 +47,10 @@ ARCHITECTURE behavior OF tb_cic_decim_pipe IS
GENERIC
(
nstages : integer;
max_ratio : integer;
ratio_max : integer;
scale_nbits_min : integer;
scale_nbits_max : integer;
max_diff_delay : integer;
max_width : integer;
max_width_frac : integer;
in_width : integer;
in_width_frac : integer;
out_width : integer;
@@ -58,9 +61,9 @@ ARCHITECTURE behavior OF tb_cic_decim_pipe IS
clk : in std_logic;
rst : in std_logic;
vld_in : in std_logic;
ratio : in natural range 1 to max_ratio;
ratio : in natural range 1 to ratio_max;
diff_delay : in natural range 1 to max_diff_delay;
shift_in : in natural range 0 to max_width-1;
shift_in : in natural range 0 to scale_nbits_max;
din : in sfixed;
dout : out sfixed;
vld_out : out std_logic
@@ -78,7 +81,7 @@ ARCHITECTURE behavior OF tb_cic_decim_pipe IS
SIGNAL din : sfixed(shi(in_width, in_width_frac) downto slo(in_width, in_width_frac));
SIGNAL diff_delay : natural := 1;
SIGNAL ratio : natural := 64;
SIGNAL shift_in : natural := 18;
SIGNAL shift_in : natural := 18-scale_nbits_min;
--Outputs
SIGNAL dout : sfixed(shi(out_width, out_width_frac) downto slo(out_width, out_width_frac));
@@ -98,10 +101,10 @@ BEGIN
GENERIC MAP
(
nstages => nstages,
max_ratio => max_ratio,
ratio_max => ratio_max,
scale_nbits_min => scale_nbits_min,
scale_nbits_max => scale_nbits_max,
max_diff_delay => max_diff_delay,
max_width => max_width,
max_width_frac => max_width_frac,
in_width => in_width,
in_width_frac => in_width_frac,
out_width => out_width,
@@ -137,23 +140,23 @@ BEGIN
------------------------------------------
wait for 2*PERIOD;
wait until rising_edge(clk);
din <= to_sfixed(0.0, din, false, true);
din <= to_sfixed(0.0, din);
vld_in <= '1';
wait for 49*PERIOD;
wait until rising_edge(clk);
din <= to_sfixed(0.5, din, false, true);
din <= to_sfixed(0.5, din);
wait for 4999*PERIOD;
wait until rising_edge(clk);
din <= to_sfixed(-0.5, din, false, true);
din <= to_sfixed(-0.5, din);
wait for 99*PERIOD;
wait until rising_edge(clk);
din <= to_sfixed(0.0, din, false, true);
din <= to_sfixed(0.0, din);
wait for 499*PERIOD;
wait until rising_edge(clk);