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- changed read, write order (should have no effect)

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git-svn-id: http://moon:8086/svn/vhdl/trunk@243 cc03376c-175c-47c8-b038-4cd826a8556b
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jens
2009-01-14 20:26:29 +00:00
parent 9163ced247
commit c882f1d469
1 changed files with 3 additions and 3 deletions
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lib/misc/dpram_2w2r.vhd
+3 -3
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@@ -21,7 +21,7 @@
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_2w2r.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_2w2r.vhd,v 1.2 2009-01-14 20:26:29 Jens Exp $
-----------------------------------------------------------------------
library IEEE;
@@ -63,10 +63,10 @@ process (clk_a)
begin
if clk_a'event and clk_a = '1' then
if en_a = '1' then
dout_a <= RAM(to_integer(addr_a));
if we_a = '1' then
RAM(to_integer(addr_a)) := din_a;
end if;
dout_a <= RAM(to_integer(addr_a));
end if;
end if;
end process;
@@ -75,10 +75,10 @@ process (clk_b)
begin
if clk_b'event and clk_b = '1' then
if en_b = '1' then
dout_b <= RAM(to_integer(addr_b));
if we_b = '1' then
RAM(to_integer(addr_b)) := din_b;
end if;
dout_b <= RAM(to_integer(addr_b));
end if;
end if;
end process;