jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

- bugfix: added 'bufchg_irq_en' to registers

Browse Source 
Committed on the Free edition of March Hare Software CVSNT Server.
Upgrade to CVS Suite for more features and support:
http://march-hare.com/cvsnt/


git-svn-id: http://moon:8086/svn/vhdl/trunk@643 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-11-08 21:50:03 +00:00
parent 618e8b54b0
commit 444e7530e1
1 changed files with 23 additions and 21 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/VGA_ctrl/src/vga_frontend64.vhd
+23 -21
View File
@@ -124,10 +124,10 @@ architecture Behavioral of vga_frontend64 is
-- Bus master signals
constant MAX_REQUEST_CNT : natural := tsvga.ts_h.ncyc_scan*tsvga.ts_v.ncyc_scan;
signal buf_chg : std_logic;
signal buf_chg_irq_en : std_logic;
signal buf_chg_irq : std_logic;
signal buf_chg_irq_ack : std_logic;
signal bufchg : std_logic;
signal bufchg_irq_en : std_logic;
signal bufchg_flag : std_logic;
signal bufchg_flag_ack : std_logic;
signal vga_mem_off_last : unsigned(31 downto 0);
signal vga_mem_off_curr : unsigned(31 downto 0);
signal vga_mem_off_0 : unsigned(31 downto 0);
@@ -148,17 +148,17 @@ architecture Behavioral of vga_frontend64 is
begin
INT_O <= buf_chg_irq;
proc_buf_chg_irq:
proc_bufchg_irq:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' or buf_chg_irq_ack = '1' then
buf_chg_irq <= '0';
elsif buf_chg = '1' then
buf_chg_irq <= buf_chg_irq_en and vga_master_en;
if RST_I = '1' or bufchg_flag_ack = '1' then
bufchg_flag <= '0';
elsif bufchg = '1' then
bufchg_flag <= vga_master_en;
end if;
INT_O <= bufchg_flag and bufchg_irq_en;
end if;
end process;
@@ -352,7 +352,7 @@ pixel_counter:
variable last : unsigned(31 downto 0);
begin
if rising_edge(CLK_I) then
buf_chg <= '0';
bufchg <= '0';
if pixel_cnt_rst = '1' then
pixel_cnt := 0;
curr := vga_mem_off_0;
@@ -364,7 +364,7 @@ pixel_counter:
pixel_cnt := 0;
curr := vga_mem_off_last;
last := vga_mem_off_curr;
buf_chg <= '1';
bufchg <= '1';
end if;
end if;
vga_mem_off_curr <= curr;
@@ -429,7 +429,8 @@ registers_read:
when "0000" =>
SDAT_O(0) <= cg_rdy;
SDAT_O(1) <= vga_master_en;
SDAT_O(2) <= buf_chg_irq;
SDAT_O(2) <= bufchg_irq_en;
SDAT_O(3) <= bufchg_flag;
-- sys_vga_ascii 4
when "0001" =>
@@ -478,16 +479,16 @@ registers_write:
process(CLK_I)
begin
if rising_edge(CLK_I) then
cg_ascii_we <= '0';
cg_posy_we <= '0';
cg_posx_we <= '0';
cg_clr_screen <= '0';
cg_clr_line <= '0';
buf_chg_irq_ack <= '0';
cg_ascii_we <= '0';
cg_posy_we <= '0';
cg_posx_we <= '0';
cg_clr_screen <= '0';
cg_clr_line <= '0';
bufchg_flag_ack <= '0';
if RST_I = '1' then
cg_din <= (others => '0');
vga_master_en <= '0';
buf_chg_irq_en <= '0';
bufchg_irq_en <= '0';
vga_mem_off_0 <= X"40000000";
vga_mem_off_1 <= X"40004000";
cg_color <= (X"FF", X"FF", X"FF", X"FF");
@@ -497,7 +498,8 @@ registers_write:
-- sys_vga_ctrl 0
when "0000" =>
vga_master_en <= SDAT_I(1);
buf_chg_irq_ack <= SDAT_I(2);
bufchg_irq_en <= SDAT_I(2);
bufchg_flag_ack <= SDAT_I(3);
cg_clr_screen <= SDAT_I(4);
cg_clr_line <= SDAT_I(5);