jens 1493e3e779 - Inhibit RAM write if FIFO is full ...

- Inhibit update of output if last word is read


git-svn-id: http://moon:8086/svn/vhdl/trunk@38 cc03376c-175c-47c8-b038-4cd826a8556b

2008-10-10 21:23:27 +00:00

lib

- Inhibit RAM write if FIFO is full

2008-10-10 21:23:27 +00:00

projects/mips_sys

Ints are registered

2008-10-08 19:34:37 +00:00

S

Description

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23 MiB

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VHDL 90.1%

Verilog 4.2%

Tcl 2.5%

SystemVerilog 0.8%

IGOR Pro 0.5%

Other 1.5%