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git-svn-id: http://moon:8086/svn/vhdl/trunk@139 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2008-12-21 16:18:22 +00:00
parent 8e6affa627
commit 776094e4b2
24 changed files with 4752 additions and 0 deletions
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lib/radio/cordic/eval_cordic.m
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function eval_cordic(Nmax, doplot)
N = 100;
arctan_tbl = (atan(2.^-(0:N-1))/pi)'
%gain_tbl = (1./cumprod(sqrt(1+2.^-(2*(0:N-1)))))'
% Rotation mode
disp('Rotation:')
for i=1:N,
phi(i) = 2*pi*(i-N/2)/N;
[x(i),y(i)] = cordic_rot(0, 1, phi(i), Nmax, 0);
end;
close all;
figure
plot(1:N, x, 1:N, y);
legend('x','y')
grid;
% Vector mode
disp('Magnitude and phase:')
for i=1:N,
[mag(i), phi(i)] = cordic_vec(x(i), y(i), Nmax, 0);
end;
figure
plot(1:N, mag, 1:N, phi);
legend('Magnitude','Phase')
grid;
% ------------------------------------------------------------
function [mag, phi] = cordic_cart2polar(x, y, Nmax, doplot)
[mag, phi] = cordic_vec(x, y, Nmax, doplot);
% ------------------------------------------------------------
function [x, y] = cordic_polar2cart(mag, phi, Nmax, doplot)
[mag, phi] = cordic_vec(x, y, Nmax, doplot);
% ------------------------------------------------------------
function [xout, yout] = cordic_rot(xin, yin, phi, N, doplot)
% Initialize
arctan_tbl = atan(2.^-(0:N-1));
gain_tbl = 1./cumprod(sqrt(1+2.^-(2*(0:N-1))));
coeffs = arctan_tbl';
gains = gain_tbl';
% Calculate initial rotation
if (phi < (-pi/2))
z = phi + pi;
x = -xin;
y = -yin;
else
if (phi > pi/2)
z = phi - pi;
x = -xin;
y = -yin;
else
x = xin;
y = yin;
z = phi;
end;
end;
% Loop
for i=1:N,
xi(i) = x;
yi(i) = y;
zi(i) = z;
S = 2^(-(i-1));
if (z < 0)
t = x + y*S;
y = y - x*S;
z = z + arctan_tbl(i);
x = t;
else
t = x - y*S;
y = y + x*S;
z = z - arctan_tbl(i);
x = t;
end;
end;
% Result
k = gain_tbl(i);
xout = k*x;
yout = k*y;
% Output
if(doplot)
close all;
figure(1);
plot(1:N, xi, 1:N, yi, 1:N, zi)
legend('x','y','z');
title('Convergence');
grid;
figure(2);
plot(xi.*gain_tbl, yi.*gain_tbl, '-x')
title('Polar plot');
grid;
end;
% ------------------------------------------------------------
function [mag, phi] = cordic_vec(xin, yin, N, doplot)
% Initialize
arctan_tbl = atan(2.^-(0:N-1));
gain_tbl = 1./cumprod(sqrt(1+2.^-(2*(0:N-1))));
coeffs = arctan_tbl';
gains = gain_tbl';
% Calculate initial rotation
if (xin < 0)
x = -xin;
y = -yin;
if (yin < 0)
z = -pi;
else
z = pi;
end;
else
x = xin;
y = yin;
z = 0;
end;
% Loop
for i=1:N,
xi(i) = x;
yi(i) = y;
zi(i) = z;
S = 2^(-(i-1));
if (y < 0)
t = x - y*S;
y = y + x*S;
z = z - arctan_tbl(i);
x = t;
else
t = x + y*S;
y = y - x*S;
z = z + arctan_tbl(i);
x = t;
end;
end;
% Result
k = gain_tbl(i);
mag = k*x;
phi = z;
% Output
if(doplot)
close all;
figure(1);
plot(1:N, xi, 1:N, yi, 1:N, zi)
legend('x','y','z');
title('Convergence');
grid;
figure(2);
plot(xi.*gain_tbl, yi.*gain_tbl, '-x')
title('Polar plot');
grid;
end;
lib/radio/cordic/sim/eval_cordic.m
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% function eval_cordic(x0,y0,z0, mode)
function eval_cordic(x0,y0,z0, mode)
if (mode == 'rot')
Xn = x0*cos(z0) - y0*sin(z0)
Yn = y0*cos(z0) + x0*sin(z0)
else
Xn = sqrt(x0^2 + y0^2)
Yn = z0 + atan(y0/x0)
end;
lib/radio/cordic/sim/tb_cordic_pipe_top.fdo
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vlib work
vcom -explicit -93 "../../../fixed/fixed_pkg_c.vhd"
vcom -explicit -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993.vhd"
vcom -explicit -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
vcom -explicit -93 "../src/cordic_pkg.vhd"
vcom -explicit -93 "../src/cordic_pipe_stage.vhd"
vcom -explicit -93 "../src/cordic_pipe_pre.vhd"
vcom -explicit -93 "../src/cordic_pipe_post.vhd"
vcom -explicit -93 "../src/cordic_pipe_top.vhd"
vcom -explicit -93 "../src/tb_cordic_pipe_top.vhd"
vsim -t 1ps -lib work tb_cordic_pipe_top
do {tb_cordic_pipe_top.wdo}
view wave
view structure
view signals
run 2000us
lib/radio/cordic/sim/tb_cordic_pipe_top.wdo
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onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_cordic_pipe_top/clk
add wave -noupdate -format Logic /tb_cordic_pipe_top/rst
add wave -noupdate -format Logic /tb_cordic_pipe_top/vld_in
add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/xin
add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/yin
add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/zin
add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/xout
add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/yout
add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/zout
add wave -noupdate -format Logic /tb_cordic_pipe_top/vld_out
add wave -noupdate -divider {Pre stage}
add wave -noupdate -format Logic /tb_cordic_pipe_top/uut/inst_cordic_pipe_pre/vld_in
add wave -noupdate -format Logic /tb_cordic_pipe_top/uut/inst_cordic_pipe_pre/vld_out
add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/uut/inst_cordic_pipe_pre/xin
add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/uut/inst_cordic_pipe_pre/yin
add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/uut/inst_cordic_pipe_pre/zin
add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/uut/inst_cordic_pipe_pre/xout
add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/uut/inst_cordic_pipe_pre/yout
add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/uut/inst_cordic_pipe_pre/zout
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {10770000 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 100
configure wave -griddelta 40
configure wave -timeline 1
update
WaveRestoreZoom {0 ps} {48466483 ps}
lib/radio/cordic/sim/tb_cordic_top.fdo
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vlib work
vcom -explicit -93 "../../../fixed/fixed_pkg_c.vhd"
vcom -explicit -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993.vhd"
vcom -explicit -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
vcom -explicit -93 "../src/cordic_pkg.vhd"
vcom -explicit -93 "../src/cordic_rom.vhd"
vcom -explicit -93 "../src/cordic_stage.vhd"
vcom -explicit -93 "../src/cordic_stage_pre.vhd"
vcom -explicit -93 "../src/cordic_stage_post.vhd"
vcom -explicit -93 "../src/cordic_top.vhd"
vcom -explicit -93 "../src/tb_cordic_top.vhd"
vsim -t 1ps -lib work tb_cordic_top
do {tb_cordic_top.wdo}
view wave
view structure
view signals
run 2000us
lib/radio/cordic/sim/tb_cordic_top.wdo
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onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider Top
add wave -noupdate -format Literal /tb_cordic_top/uut/cordic_mode
add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/xin
add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/yin
add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/zin
add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/xout
add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/yout
add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/zout
add wave -noupdate -format Logic /tb_cordic_top/ce
add wave -noupdate -format Logic /tb_cordic_top/valid
add wave -noupdate -divider {Pre stage}
add wave -noupdate -format Literal /tb_cordic_top/uut/inst_cordic_stage_pre/cordic_mode
add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_pre/xin
add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_pre/yin
add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_pre/zin
add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_pre/xout
add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_pre/yout
add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_pre/zout
add wave -noupdate -divider {Process stage}
add wave -noupdate -format Literal /tb_cordic_top/uut/count
add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage/coeff
add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage/xin
add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage/yin
add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage/zin
add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage/xout
add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage/yout
add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage/zout
add wave -noupdate -divider {Post stage}
add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_post/xin
add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_post/yin
add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_post/zin
add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_post/xout
add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_post/yout
add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_post/zout
add wave -noupdate -divider Signals
add wave -noupdate -format Logic /tb_cordic_top/uut/ce
add wave -noupdate -format Logic /tb_cordic_top/uut/pre_stage_ready
add wave -noupdate -format Logic /tb_cordic_top/uut/pre_stage_en
add wave -noupdate -format Logic /tb_cordic_top/uut/pre_stage_valid
add wave -noupdate -format Logic /tb_cordic_top/uut/proc_stage_ready
add wave -noupdate -format Logic /tb_cordic_top/uut/proc_stage_en
add wave -noupdate -format Logic /tb_cordic_top/uut/proc_stage_valid
add wave -noupdate -format Logic /tb_cordic_top/uut/post_stage_ready
add wave -noupdate -format Logic /tb_cordic_top/uut/post_stage_en
add wave -noupdate -format Logic /tb_cordic_top/uut/post_stage_valid
add wave -noupdate -format Literal /tb_cordic_top/uut/state
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {1463518 ps} 0}
configure wave -namecolwidth 184
configure wave -valuecolwidth 124
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {655140 ps} {1967644 ps}
lib/radio/cordic/sim/tb_results.m
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% Read data
X = TEXTREAD('x.txt');
Y = TEXTREAD('y.txt');
Z = TEXTREAD('z.txt');
% Output
close all;
plot(0:length(X)-1, X, 0:length(Y)-1, Y, 0:length(Z)-1, Z);
title ('Output');
legend('X','Y','Z');
grid;
W= 2*pi/100;
phi = 0;
xd = -cos(phi+W*(0:length(X)-1))';
yd = -sin(phi+W*(0:length(Y)-1))';
VarErrorX = var(X-xd)
VarErrorY = var(Y-yd)
MeanErrorX = mean(X-xd)
MeanErrorY = mean(Y-yd)
figure;
plot(0:length(X)-1, X-xd, 0:length(Y)-1, Y-yd, 0:length(Z)-1, Z);
title ('Error');
legend('X - X_D','Y - Y_D', 'Z');
grid;
figure;
plot(0:length(X)-1, X, 0:length(Y)-1, Y, 0:length(Z)-1, xd, 0:length(yd)-1, yd);
title ('Output');
legend('X','Y','X_D','Y_D');
grid;
lib/radio/cordic/src/cordic_pipe_post.vhd
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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:16:14 10/02/05
-- Design Name:
-- Module Name: cordic_stage_pre - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
use work.fixed_pkg.all;
use work.cordic_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity cordic_pipe_post is
Generic
(
cordic_mode : cordic_mode_t := cordic_mode_rotate;
nstages : integer := 0;
nbits_x : integer := 8;
nbits_x_frac : integer := 6;
nbits_y : integer := 8;
nbits_y_frac : integer := 6;
nbits_z : integer := 8;
nbits_z_frac : integer := 8
);
Port
(
clk : in std_logic;
rst : in std_logic;
vld_in : in std_logic;
xin : in sfixed;
yin : in sfixed;
zin : in sfixed;
xout : out sfixed;
yout : out sfixed;
zout : out sfixed;
vld_out : out std_logic
);
end cordic_pipe_post;
architecture Behavioral of cordic_pipe_post is
constant gain_x : sfixed := to_sfixed(gain_tbl(nstages), shi(nbits_x, nbits_x_frac), slo(nbits_x, nbits_x_frac), false, true);
constant gain_y : sfixed := to_sfixed(gain_tbl(nstages), shi(nbits_y, nbits_y_frac), slo(nbits_y, nbits_y_frac), false, true);
------------------------------------------------------------
begin
------------------------------------------------------------
cordic_proc_pre_stage:
process(clk)
variable xi, xo : sfixed(shi(nbits_x, nbits_x_frac) downto slo(nbits_x, nbits_x_frac));
variable yi, yo : sfixed(shi(nbits_y, nbits_y_frac) downto slo(nbits_y, nbits_y_frac));
variable zi, zo : sfixed(shi(nbits_z, nbits_z_frac) downto slo(nbits_z, nbits_z_frac));
begin
if rising_edge(clk) then
vld_out <= '0';
if rst = '1' then
xout <= (shi(nbits_x, nbits_x_frac) downto slo(nbits_x, nbits_x_frac) => '0');
yout <= (shi(nbits_y, nbits_y_frac) downto slo(nbits_y, nbits_y_frac) => '0');
zout <= (shi(nbits_z, nbits_z_frac) downto slo(nbits_z, nbits_z_frac) => '0');
elsif vld_in = '1' then
vld_out <= '1';
xi := resize(xin, xi);
yi := resize(yin, yi);
zi := resize(zin, zi);
xo := resize(xi * gain_x, xo, cordic_saturate_mode, cordic_round_mode);
yo := resize(yi * gain_y, yo, cordic_saturate_mode, cordic_round_mode);
zo := zi;
xout <= xo after tpd;
yout <= yo after tpd;
zout <= zo after tpd;
end if;
end if;
end process;
------------------------------------------------------------
end Behavioral;
lib/radio/cordic/src/cordic_pipe_pre.vhd
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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:16:14 10/02/05
-- Design Name:
-- Module Name: cordic_stage_pre - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
use work.fixed_pkg.all;
use work.cordic_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity cordic_pipe_pre is
Generic
(
cordic_mode : cordic_mode_t := cordic_mode_rotate;
z_range : real := pi;
nbits_x : integer := 8;
nbits_x_frac : integer := 6;
nbits_y : integer := 8;
nbits_y_frac : integer := 6;
nbits_z : integer := 8;
nbits_z_frac : integer := 8
);
Port
(
clk : in std_logic;
rst : in std_logic;
vld_in : in std_logic;
xin : in sfixed;
yin : in sfixed;
zin : in sfixed;
xout : out sfixed;
yout : out sfixed;
zout : out sfixed;
vld_out : out std_logic
);
end cordic_pipe_pre;
architecture Behavioral of cordic_pipe_pre is
constant pi_sfix : sfixed := to_sfixed(z_range, sproto(nbits_z, nbits_z_frac), false, true);
constant pi2_sfix : sfixed := to_sfixed(z_range/2.0, sproto(nbits_z, nbits_z_frac), false, true);
------------------------------------------------------------
begin
------------------------------------------------------------
cordic_proc_pre_stage:
process(clk)
variable xi, xo : sfixed(shi(nbits_x, nbits_x_frac) downto slo(nbits_x, nbits_x_frac));
variable yi, yo : sfixed(shi(nbits_y, nbits_y_frac) downto slo(nbits_y, nbits_y_frac));
variable zi, zo : sfixed(shi(nbits_z, nbits_z_frac) downto slo(nbits_z, nbits_z_frac));
begin
if rising_edge(clk) then
vld_out <= '0';
if rst = '1' then
xout <= (shi(nbits_x, nbits_x_frac) downto slo(nbits_x, nbits_x_frac) => '0');
yout <= (shi(nbits_y, nbits_y_frac) downto slo(nbits_y, nbits_y_frac) => '0');
zout <= (shi(nbits_z, nbits_z_frac) downto slo(nbits_z, nbits_z_frac) => '0');
elsif vld_in = '1' then
vld_out <= '1';
xi := xin;
yi := yin;
zi := zin;
xo := xi;
yo := yi;
zo := zi;
if (zi < -pi2_sfix) then
xo := resize(-xi, xo);
yo := resize(-yi, yo);
zo := resize(zi + pi_sfix, zo);
elsif (zi > pi2_sfix) then
xo := resize(-xi, xo);
yo := resize(-yi, yo);
zo := resize(zi - pi_sfix, zo);
end if;
xout <= xo after tpd;
yout <= yo after tpd;
zout <= zo after tpd;
end if;
end if;
end process;
------------------------------------------------------------
end Behavioral;
-- if (y < 0) then
-- x' = -y
-- y' = x
-- z' = z + pi/2;
-- else
-- x' = y
-- y' = -x
-- z' = z - pi/2;
-- end if;
--
-- if (x < 0) then
-- x' = -x;
-- y' = -y;
-- z' = z - pi
-- else
-- x' = x;
-- y' = y;
-- z' = z
-- end if;
lib/radio/cordic/src/cordic_pipe_stage.vhd
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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:16:14 10/02/05
-- Design Name:
-- Module Name: cordic_stage - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
use work.fixed_pkg.all;
use work.cordic_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity cordic_pipe_stage is
Generic
(
cordic_mode : cordic_mode_t := cordic_mode_rotate;
z_range : real := pi;
stage_num : integer := 0;
nbits_x : integer := 8;
nbits_x_frac : integer := 6;
nbits_y : integer := 8;
nbits_y_frac : integer := 6;
nbits_z : integer := 8;
nbits_z_frac : integer := 8
);
Port
(
clk : in std_logic;
rst : in std_logic;
vld_in : in std_logic;
xin : in sfixed;
yin : in sfixed;
zin : in sfixed;
xout : out sfixed;
yout : out sfixed;
zout : out sfixed;
vld_out : out std_logic
);
end cordic_pipe_stage;
architecture Behavioral of cordic_pipe_stage is
constant coeff : sfixed := to_sfixed(arctan_tbl(stage_num)*z_range, shi(nbits_z, nbits_z_frac), slo(nbits_z, nbits_z_frac), false, true);
begin
------------------------------------------------------------
cordic_proc_stage:
process(clk)
variable xi, xt, xo : sfixed(shi(nbits_x, nbits_x_frac) downto slo(nbits_x, nbits_x_frac));
variable yi, yt, yo : sfixed(shi(nbits_y, nbits_y_frac) downto slo(nbits_y, nbits_y_frac));
variable zi, zo : sfixed(shi(nbits_z, nbits_z_frac) downto slo(nbits_z, nbits_z_frac));
begin
if rising_edge(clk) then
vld_out <= '0';
if rst = '1' then
xout <= (shi(nbits_x, nbits_x_frac) downto slo(nbits_x, nbits_x_frac) => '0');
yout <= (shi(nbits_y, nbits_y_frac) downto slo(nbits_y, nbits_y_frac) => '0');
zout <= (shi(nbits_z, nbits_z_frac) downto slo(nbits_z, nbits_z_frac) => '0');
elsif vld_in = '1' then
vld_out <= '1';
xi := xin;
yi := yin;
zi := zin;
xt := xi sra stage_num;
yt := yi sra stage_num;
if zi(zi'high) = '1' then
xo := resize(xi + yt, xo);
yo := resize(yi - xt, yo);
zo := resize(zi + coeff, zo);
else
xo := resize(xi - yt, xo);
yo := resize(yi + xt, yo);
zo := resize(zi - coeff, zo);
end if;
xout <= xo after tpd;
yout <= yo after tpd;
zout <= zo after tpd;
end if;
end if;
end process;
------------------------------------------------------------
end Behavioral;
lib/radio/cordic/src/cordic_pipe_top.vhd
+305
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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:52:30 10/02/05
-- Design Name:
-- Module Name: cordic_top - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
USE ieee.numeric_std.ALL;
use work.fixed_pkg.all;
use work.cordic_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity cordic_pipe_top is
Generic
(
cordic_mode : cordic_mode_t := cordic_mode_rotate;
z_range : real := pi;
gain_corr_mode : gain_corr_mode_t := gain_mode_unity;
nstages : integer := 18;
nbits_x_in : integer := 18;
nbits_y_in : integer := 18;
nbits_z_in : integer := 18;
nbits_frac_x_in : integer := 16;
nbits_frac_y_in : integer := 16;
nbits_frac_z_in : integer := 16;
nbits_x_out : integer := 18;
nbits_y_out : integer := 18;
nbits_z_out : integer := 18;
nbits_frac_x_out : integer := 17;
nbits_frac_y_out : integer := 17;
nbits_frac_z_out : integer := 17
);
Port
(
rst : in std_logic;
clk : in std_logic;
vld_in : in std_logic;
xin : in sfixed(shi(nbits_x_in, nbits_frac_x_in) downto slo(nbits_x_in, nbits_frac_x_in));
yin : in sfixed(shi(nbits_y_in, nbits_frac_y_in) downto slo(nbits_y_in, nbits_frac_y_in));
zin : in sfixed(shi(nbits_z_in, nbits_frac_z_in) downto slo(nbits_z_in, nbits_frac_z_in));
xout : out sfixed(shi(nbits_x_out, nbits_frac_x_out) downto slo(nbits_x_out, nbits_frac_x_out));
yout : out sfixed(shi(nbits_y_out, nbits_frac_y_out) downto slo(nbits_y_out, nbits_frac_y_out));
zout : out sfixed(shi(nbits_z_out, nbits_frac_z_out) downto slo(nbits_z_out, nbits_frac_z_out));
vld_out : out std_logic
);
end cordic_pipe_top;
architecture Behavioral of cordic_pipe_top is
-----------------------------------------------------------------------
COMPONENT cordic_pipe_pre is
GENERIC
(
cordic_mode : cordic_mode_t;
z_range : real;
nbits_x : integer;
nbits_x_frac : integer;
nbits_y : integer;
nbits_y_frac : integer;
nbits_z : integer;
nbits_z_frac : integer
);
PORT(
rst : IN std_logic;
clk : IN std_logic;
vld_in : IN std_logic;
xin : IN sfixed;
yin : IN sfixed;
zin : IN sfixed;
xout : OUT sfixed;
yout : OUT sfixed;
zout : OUT sfixed;
vld_out : out std_logic
);
END COMPONENT;
COMPONENT cordic_pipe_stage
GENERIC
(
cordic_mode : cordic_mode_t;
z_range : real;
stage_num : integer;
nbits_x : integer;
nbits_x_frac : integer;
nbits_y : integer;
nbits_y_frac : integer;
nbits_z : integer;
nbits_z_frac : integer
);
PORT(
rst : IN std_logic;
clk : IN std_logic;
vld_in : IN std_logic;
xin : IN sfixed;
yin : IN sfixed;
zin : IN sfixed;
xout : OUT sfixed;
yout : OUT sfixed;
zout : OUT sfixed;
vld_out : out std_logic
);
END COMPONENT;
COMPONENT cordic_pipe_post is
GENERIC
(
cordic_mode : cordic_mode_t;
nstages : integer;
nbits_x : integer;
nbits_x_frac : integer;
nbits_y : integer;
nbits_y_frac : integer;
nbits_z : integer;
nbits_z_frac : integer
);
PORT(
rst : IN std_logic;
clk : IN std_logic;
vld_in : IN std_logic;
xin : IN sfixed;
yin : IN sfixed;
zin : IN sfixed;
xout : OUT sfixed;
yout : OUT sfixed;
zout : OUT sfixed;
vld_out : out std_logic
);
END COMPONENT;
-----------------------------------------------------------------------
-- Define number of internal stage bits
constant stage_x_nbits : integer := nbits_x_in + integer(log2(real(nbits_x_in))+0.5);
constant stage_x_nbits_frac : integer := nbits_frac_x_in + integer(log2(real(nbits_x_in))+0.5);
constant stage_y_nbits : integer := nbits_y_in + integer(log2(real(nbits_y_in))+0.5);
constant stage_y_nbits_frac : integer := nbits_frac_y_in + integer(log2(real(nbits_y_in))+0.5);
constant stage_z_nbits : integer := nbits_z_in + integer(log2(real(nbits_z_in))+0.5);
constant stage_z_nbits_frac : integer := nbits_frac_z_in + integer(log2(real(nbits_z_in))+0.5);
-- INPUT
-- Input pre stage
signal pre_xin : sfixed(shi(stage_x_nbits, stage_x_nbits_frac) downto slo(stage_x_nbits, stage_x_nbits_frac));
signal pre_yin : sfixed(shi(stage_y_nbits, stage_y_nbits_frac) downto slo(stage_y_nbits, stage_y_nbits_frac));
signal pre_zin : sfixed(shi(stage_z_nbits, stage_z_nbits_frac) downto slo(stage_z_nbits, stage_z_nbits_frac));
signal pre_xout : sfixed(shi(stage_x_nbits, stage_x_nbits_frac) downto slo(stage_x_nbits, stage_x_nbits_frac));
signal pre_yout : sfixed(shi(stage_y_nbits, stage_y_nbits_frac) downto slo(stage_y_nbits, stage_y_nbits_frac));
signal pre_zout : sfixed(shi(stage_z_nbits, stage_z_nbits_frac) downto slo(stage_z_nbits, stage_z_nbits_frac));
-- Input processing stage
subtype stage_x_t is sfixed(shi(stage_x_nbits, stage_x_nbits_frac) downto slo(stage_x_nbits, stage_x_nbits_frac));
subtype stage_y_t is sfixed(shi(stage_y_nbits, stage_y_nbits_frac) downto slo(stage_y_nbits, stage_y_nbits_frac));
subtype stage_z_t is sfixed(shi(stage_z_nbits, stage_z_nbits_frac) downto slo(stage_z_nbits, stage_z_nbits_frac));
type stage_x_array_t is array(0 to nstages) of stage_x_t;
type stage_y_array_t is array(0 to nstages) of stage_y_t;
type stage_z_array_t is array(0 to nstages) of stage_z_t;
signal stage_vld: unsigned(0 to nstages);
signal stage_x : stage_x_array_t;
signal stage_y : stage_y_array_t;
signal stage_z : stage_z_array_t;
-- Output post stage
signal post_xin : sfixed(shi(nbits_x_out, nbits_frac_x_out) downto slo(nbits_x_out, nbits_frac_x_out));
signal post_yin : sfixed(shi(nbits_y_out, nbits_frac_y_out) downto slo(nbits_y_out, nbits_frac_y_out));
signal post_zin : sfixed(shi(nbits_z_out, nbits_frac_z_out) downto slo(nbits_z_out, nbits_frac_z_out));
signal post_xout : sfixed(shi(nbits_x_out, nbits_frac_x_out) downto slo(nbits_x_out, nbits_frac_x_out));
signal post_yout : sfixed(shi(nbits_y_out, nbits_frac_y_out) downto slo(nbits_y_out, nbits_frac_y_out));
signal post_zout : sfixed(shi(nbits_z_out, nbits_frac_z_out) downto slo(nbits_z_out, nbits_frac_z_out));
begin
pre_xin <= resize(xin, pre_xin);
pre_yin <= resize(yin, pre_yin);
pre_zin <= resize(zin, pre_zin);
stage_x(0) <= resize(pre_xout, stage_x(0));
stage_y(0) <= resize(pre_yout, stage_y(0));
stage_z(0) <= resize(pre_zout, stage_z(0));
post_xin <= resize(stage_x(nstages), post_xin, cordic_saturate_mode, cordic_round_mode);
post_yin <= resize(stage_y(nstages), post_yin, cordic_saturate_mode, cordic_round_mode);
post_zin <= resize(stage_z(nstages), post_zin, cordic_saturate_mode, cordic_round_mode);
gen_output_unity:
if gain_corr_mode = gain_mode_unity generate
begin
xout <= post_xout;
yout <= post_yout;
zout <= post_zout;
end generate;
gen_output_disabled:
if gain_corr_mode = gain_mode_disabled generate
begin
xout <= post_xin;
yout <= post_yin;
zout <= post_zin;
end generate;
-----------------------------------------------------------------------
Inst_cordic_pipe_pre: cordic_pipe_pre
GENERIC MAP
(
cordic_mode => cordic_mode_rotate,
z_range => z_range,
nbits_x => stage_x_nbits,
nbits_x_frac => stage_x_nbits_frac,
nbits_y => stage_y_nbits,
nbits_y_frac => stage_y_nbits_frac,
nbits_z => stage_z_nbits,
nbits_z_frac => stage_z_nbits_frac
)
PORT MAP
(
rst => rst,
clk => clk,
vld_in => vld_in,
xin => pre_xin,
yin => pre_yin,
zin => pre_zin,
xout => pre_xout,
yout => pre_yout,
zout => pre_zout,
vld_out => stage_vld(0)
);
gen_pipe:
for i in 1 to nstages generate
Inst_cordic_pipe: cordic_pipe_stage
GENERIC MAP
(
cordic_mode => cordic_mode_rotate,
z_range => z_range,
stage_num => i-1,
nbits_x => stage_x_nbits,
nbits_x_frac => stage_x_nbits_frac,
nbits_y => stage_y_nbits,
nbits_y_frac => stage_y_nbits_frac,
nbits_z => stage_z_nbits,
nbits_z_frac => stage_z_nbits_frac
)
PORT MAP
(
rst => rst,
clk => clk,
vld_in => stage_vld(i-1),
xin => stage_x(i-1),
yin => stage_y(i-1),
zin => stage_z(i-1),
xout => stage_x(i),
yout => stage_y(i),
zout => stage_z(i),
vld_out => stage_vld(i)
);
end generate;
Inst_cordic_pipe_post: cordic_pipe_post
GENERIC MAP
(
cordic_mode => cordic_mode_rotate,
nstages => nstages,
nbits_x => nbits_x_out,
nbits_x_frac => nbits_frac_x_out,
nbits_y => nbits_y_out,
nbits_y_frac => nbits_frac_y_out,
nbits_z => nbits_z_out,
nbits_z_frac => nbits_frac_z_out
)
PORT MAP
(
rst => rst,
clk => clk,
vld_in => stage_vld(nstages),
xin => post_xin,
yin => post_yin,
zin => post_zin,
xout => post_xout,
yout => post_yout,
zout => post_zout,
vld_out => vld_out
);
--------------------------------------------------------------------
end Behavioral;
lib/radio/cordic/src/cordic_pkg.vhd
+245
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@@ -0,0 +1,245 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use work.fixed_pkg.all;
package cordic_pkg is
constant tpd : time := 0 ns;
type cordic_mode_t is (none, cordic_mode_rotate, cordic_mode_vector);
type reg_mode_t is (none, reg_mode_in, reg_mode_out, reg_mode_inout);
type gain_corr_mode_t is (gain_mode_disabled, gain_mode_unity);
-- Global set arithmetic rounding mode
constant cordic_round_mode : boolean := true;
-- Global set arithmetic saturating mode
constant cordic_saturate_mode : boolean := false;
constant max_iteration : integer := 80;
constant pi : real := 3.141592653589793e+000;
constant sqrt2 : real := 1.414213562373095e+000;
constant sqrt2_inv : real := 7.071067811865475e-001;
type real_tbl_t is array (natural range <>) of real;
-- Normalize Arctan table (phase +/- 1.0)
-- MatLab command: arctan_tbl = (atan(2.^-(0:N-1))/pi)'
-- (Print format: long e, compact)
constant arctan_tbl : real_tbl_t (0 to max_iteration-1) :=
(
2.500000000000000e-001,
1.475836176504333e-001,
7.797913037736932e-002,
3.958342416056555e-002,
1.986852430554084e-002,
9.943947823589275e-003,
4.973187278950414e-003,
2.486745393669739e-003,
1.243391668714101e-003,
6.216982059233716e-004,
3.108493994100204e-004,
1.554247367611316e-004,
7.771237301258342e-005,
3.885618708529400e-005,
1.942809361502228e-005,
9.714046816558053e-006,
4.857023409409890e-006,
2.428511704846303e-006,
1.214255852440821e-006,
6.071279262226194e-007,
3.035639631115858e-007,
1.517819815558274e-007,
7.589099077791802e-008,
3.794549538895954e-008,
1.897274769447984e-008,
9.486373847239929e-009,
4.743186923619965e-009,
2.371593461809983e-009,
1.185796730904992e-009,
5.928983654524958e-010,
2.964491827262479e-010,
1.482245913631239e-010,
7.411229568156197e-011,
3.705614784078099e-011,
1.852807392039049e-011,
9.264036960195246e-012,
4.632018480097623e-012,
2.316009240048812e-012,
1.158004620024406e-012,
5.790023100122029e-013,
2.895011550061015e-013,
1.447505775030507e-013,
7.237528875152536e-014,
3.618764437576268e-014,
1.809382218788134e-014,
9.046911093940670e-015,
4.523455546970335e-015,
2.261727773485168e-015,
1.130863886742584e-015,
5.654319433712919e-016,
2.827159716856459e-016,
1.413579858428230e-016,
7.067899292141149e-017,
3.533949646070574e-017,
1.766974823035287e-017,
8.834874115176436e-018,
4.417437057588218e-018,
2.208718528794109e-018,
1.104359264397055e-018,
5.521796321985272e-019,
2.760898160992636e-019,
1.380449080496318e-019,
6.902245402481590e-020,
3.451122701240795e-020,
1.725561350620398e-020,
8.627806753101988e-021,
4.313903376550994e-021,
2.156951688275497e-021,
1.078475844137749e-021,
5.392379220688743e-022,
2.696189610344371e-022,
1.348094805172186e-022,
6.740474025860928e-023,
3.370237012930464e-023,
1.685118506465232e-023,
8.425592532326160e-024,
4.212796266163080e-024,
2.106398133081540e-024,
1.053199066540770e-024,
5.265995332703850e-025
);
-- Gain correction table
-- MatLab command: gain_tbl = (1./cumprod(sqrt(1+2.^-(2*(0:N-1)))))'
-- (Print format: long e, compact)
constant gain_tbl : real_tbl_t (0 to max_iteration-1) :=
(
7.071067811865475e-001,
6.324555320336759e-001,
6.135719910778963e-001,
6.088339125177524e-001,
6.076482562561681e-001,
6.073517701412959e-001,
6.072776440935260e-001,
6.072591122988928e-001,
6.072544793325624e-001,
6.072533210898752e-001,
6.072530315291344e-001,
6.072529591389448e-001,
6.072529410413973e-001,
6.072529365170103e-001,
6.072529353859135e-001,
6.072529351031394e-001,
6.072529350324457e-001,
6.072529350147724e-001,
6.072529350103540e-001,
6.072529350092495e-001,
6.072529350089733e-001,
6.072529350089043e-001,
6.072529350088870e-001,
6.072529350088827e-001,
6.072529350088816e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001,
6.072529350088813e-001
);
-------------------------------------------------------------
-- Constructor helpers
-- Use: variable v8u6 : ufixed_t(ufixed(8,6)'range);
function uproto (nbits : integer; nbits_frac : integer) return ufixed;
-- Use: variable v8s6 : sfixed_t(sfixed(8,6)'range);
function sproto (nbits : integer; nbits_frac : integer) return sfixed;
function shi (nbits : integer; nbits_frac : integer) return integer;
function slo (nbits : integer; nbits_frac : integer) return integer;
end; -- package cordic_pkg;
-------------------------------------------------------------------------------
package body cordic_pkg is
-------------------------------------------------------------
-- Constuctor helpers
function uproto (nbits : integer; nbits_frac : integer) return ufixed is
constant result : ufixed (nbits-nbits_frac-1 downto -nbits_frac) := (others => '0');
begin
return result(nbits-nbits_frac-1 downto -nbits_frac);
end uproto;
-------------------------------------------------------------
function sproto (nbits : integer; nbits_frac : integer) return sfixed is
constant result : sfixed (nbits-nbits_frac downto -nbits_frac+1) := (others => '0');
begin
return result(nbits-nbits_frac downto -nbits_frac+1);
end sproto;
-------------------------------------------------------------
function shi (nbits : integer; nbits_frac : integer) return integer is
begin
return nbits-nbits_frac;
end shi;
-------------------------------------------------------------
function slo (nbits : integer; nbits_frac : integer) return integer is
begin
return -nbits_frac+1;
end slo;
end; -- package body cordic_pkg;
lib/radio/cordic/src/cordic_rom.vhd
+80
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@@ -0,0 +1,80 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:37:26 10/02/05
-- Design Name:
-- Module Name: coeff_rom - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
library work;
use work.fixed_pkg.all;
use work.cordic_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rom_arctan is
Generic
(
nbits : integer := 8;
nbits_frac : integer := 8
);
Port
(
addr : in unsigned(6 downto 0);
dout : out sfixed
);
end rom_arctan;
architecture Behavioral of rom_arctan is
subtype word_t is sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
type rom_t is array (natural range <>) of word_t;
-------------------------------------------------------------------------------
function rom_gen(nstages : integer; round_mode : boolean) return rom_t is
variable rom : rom_t (0 to nstages-1);
variable word : word_t;
begin
for i in 0 to nstages-1 loop
word := to_sfixed(arctan_tbl(i), word, false, round_mode);
rom(i) := word;
end loop;
return rom;
end rom_gen;
-------------------------------------------------------------------------------
-- Create ROM
constant arctan_rom : rom_t (0 to max_iteration-1) := rom_gen(max_iteration, cordic_round_mode);
-------------------------------------------------------------------------------
begin
-- ROM implementation
rom_arctan: process(addr)
begin
dout <= arctan_rom(to_integer(addr));
end process;
-------------------------------------------------------------------------------
end Behavioral;
lib/radio/cordic/src/cordic_stage.vhd
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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:16:14 10/02/05
-- Design Name:
-- Module Name: cordic_stage - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
use work.fixed_pkg.all;
use work.cordic_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity cordic_stage is
Generic
(
nbits : integer := 8;
nbits_frac : integer := 6;
nbits_out : integer := 8;
nbits_frac_out : integer := 6;
reg_mode : reg_mode_t := reg_mode_in
);
Port
(
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
xin : in sfixed;
yin : in sfixed;
zin : in sfixed;
xout : out sfixed;
yout : out sfixed;
zout : out sfixed;
coeff : in sfixed;
dir_cw : in std_logic;
stage_count : in integer;
cordic_mode : in cordic_mode_t;
ready : out std_logic;
valid : out std_logic
);
end cordic_stage;
architecture Behavioral of cordic_stage is
type xyz_in_t is record
x : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
y : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
z : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
end record;
type xyz_out_t is record
x : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
y : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
z : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
end record;
constant zero_in_sfix : sfixed := to_sfixed(0.0, sproto(nbits, nbits_frac)'high, sproto(nbits, nbits_frac)'low);
constant zero_out_sfix : sfixed := to_sfixed(0.0, sproto(nbits_out, nbits_frac_out)'high, sproto(nbits_out, nbits_frac_out)'low);
signal xyz_in : xyz_in_t;
signal xyz_out : xyz_out_t;
signal valid_r, ready_r : std_logic;
begin
------------------------------------------------------------
gen_direct: if reg_mode = none generate
reg_in : process (rst, ce, xin, yin, zin)
begin
if (rst = '1') then
ready_r <= '0';
valid_r <= '0';
xyz_in.x <= zero_in_sfix;
xyz_in.y <= zero_in_sfix;
xyz_in.z <= zero_in_sfix;
else
ready_r <= '1';
valid_r <= ce;
xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
end if;
end process;
reg_out : process (rst, ce, ready_r, valid_r, xyz_out)
begin
if (rst = '1') then
ready <= '0';
valid <= '0';
xout <= zero_out_sfix;
yout <= zero_out_sfix;
zout <= zero_out_sfix;
else
ready <= ready_r;
valid <= valid_r;
xout <= xyz_out.x;
yout <= xyz_out.y;
zout <= xyz_out.z;
end if;
end process;
end generate;
------------------------------------------------------------
gen_reg_in: if (reg_mode = reg_mode_in) generate
reg_in : process (rst, clk, ce, xin, yin, zin)
begin
if (rst = '1') then
ready_r <= '0';
valid_r <= '0';
xyz_in.x <= zero_in_sfix;
xyz_in.y <= zero_in_sfix;
xyz_in.z <= zero_in_sfix;
elsif rising_edge(clk) then
ready_r <= '1';
valid_r <= ce;
if (ce = '1') then
xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
end if;
end if;
end process;
reg_out : process (rst, ready_r, valid_r, xyz_out)
begin
if (rst = '1') then
ready <= '0';
valid <= '0';
xout <= zero_out_sfix;
yout <= zero_out_sfix;
zout <= zero_out_sfix;
else
ready <= ready_r;
valid <= valid_r;
xout <= xyz_out.x;
yout <= xyz_out.y;
zout <= xyz_out.z;
end if;
end process;
end generate;
------------------------------------------------------------
gen_reg_out: if (reg_mode = reg_mode_out) generate
reg_in : process (rst, ce, xin, yin, zin)
begin
if (rst = '1') then
ready_r <= '0';
valid_r <= '0';
xyz_in.x <= zero_in_sfix;
xyz_in.y <= zero_in_sfix;
xyz_in.z <= zero_in_sfix;
else
ready_r <= '1';
valid_r <= ce;
xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
end if;
end process;
reg_out : process (rst, clk, ce, ready_r, valid_r, xyz_out)
begin
if (rst = '1') then
ready <= '0';
valid <= '0';
xout <= zero_out_sfix;
yout <= zero_out_sfix;
zout <= zero_out_sfix;
elsif rising_edge(clk) then
ready <= ready_r;
valid <= valid_r;
if (ce = '1') then
xout <= xyz_out.x;
yout <= xyz_out.y;
zout <= xyz_out.z;
end if;
end if;
end process;
end generate;
------------------------------------------------------------
gen_reg_inout: if (reg_mode = reg_mode_inout) generate
reg_in : process (rst, clk, ce, xin, yin, zin)
begin
if (rst = '1') then
ready_r <= '0';
valid_r <= '0';
xyz_in.x <= zero_in_sfix;
xyz_in.y <= zero_in_sfix;
xyz_in.z <= zero_in_sfix;
elsif rising_edge(clk) then
ready_r <= '1';
valid_r <= ce;
if (ce = '1') then
xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
end if;
end if;
end process;
reg_out : process (rst, clk, ce, ready_r, valid_r, xyz_out)
begin
if (rst = '1') then
ready <= '0';
valid <= '0';
xout <= zero_out_sfix;
yout <= zero_out_sfix;
zout <= zero_out_sfix;
elsif rising_edge(clk) then
ready <= ready_r;
valid <= valid_r;
if (ce = '1') then
xout <= xyz_out.x;
yout <= xyz_out.y;
zout <= xyz_out.z;
end if;
end if;
end process;
end generate;
------------------------------------------------------------
cordic_proc_stage: process(rst, clk, ce, stage_count, coeff, dir_cw, xyz_in)
variable dir_cw_r : std_logic;
variable stage_count_r : integer range 0 to nbits-1;
variable x2, y2 : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
begin
if (rst = '1') then
dir_cw_r := dir_cw;
stage_count_r := 0;
x2 := zero_in_sfix;
y2 := zero_in_sfix;
xyz_out.x <= zero_out_sfix;
xyz_out.y <= zero_out_sfix;
xyz_out.z <= zero_out_sfix;
else
if (clk'event and clk = '1') then
dir_cw_r := dir_cw;
stage_count_r := stage_count;
end if;
x2 := xyz_in.x sra stage_count_r;
y2 := xyz_in.y sra stage_count_r;
if (dir_cw_r = '1') then
xyz_out.x <= resize(xyz_in.x + y2, xyz_out.x'left, xyz_out.x'right) after tpd;
xyz_out.y <= resize(xyz_in.y - x2, xyz_out.y'left, xyz_out.y'right) after tpd;
xyz_out.z <= resize(xyz_in.z + coeff, xyz_out.z'left, xyz_out.z'right) after tpd;
else
xyz_out.x <= resize(xyz_in.x - y2, xyz_out.x'left, xyz_out.x'right) after tpd;
xyz_out.y <= resize(xyz_in.y + x2, xyz_out.y'left, xyz_out.y'right) after tpd;
xyz_out.z <= resize(xyz_in.z - coeff, xyz_out.z'left, xyz_out.z'right) after tpd;
end if;
end if;
end process;
------------------------------------------------------------
end Behavioral;
lib/radio/cordic/src/cordic_stage_post.vhd
+273
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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:16:14 10/02/05
-- Design Name:
-- Module Name: cordic_stage_post - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
use work.fixed_pkg.all;
use work.cordic_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity cordic_stage_post is
Generic
(
nbits : integer := 8;
nbits_frac : integer := 6;
nbits_out : integer := 8;
nbits_frac_out : integer := 6;
reg_mode : reg_mode_t := reg_mode_in
);
Port
(
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
xin : in sfixed;
yin : in sfixed;
zin : in sfixed;
xout : out sfixed;
yout : out sfixed;
zout : out sfixed;
cordic_mode : in cordic_mode_t;
ready : out std_logic;
valid : out std_logic
);
end cordic_stage_post;
architecture Behavioral of cordic_stage_post is
type xyz_in_t is record
x : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
y : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
z : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
end record;
type xyz_out_t is record
x : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
y : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
z : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
end record;
constant zero_in_sfix : sfixed := to_sfixed(0.0, sproto(nbits, nbits_frac)'high, sproto(nbits, nbits_frac)'low);
constant zero_out_sfix : sfixed := to_sfixed(0.0, sproto(nbits_out, nbits_frac_out)'high, sproto(nbits_out, nbits_frac_out)'low);
signal xyz_in : xyz_in_t;
signal xyz_out : xyz_out_t;
signal valid_r, ready_r : std_logic;
------------------------------------------------------------
begin
gen_direct: if reg_mode = none generate
reg_in : process (rst, ce, xin, yin, zin)
begin
if (rst = '1') then
ready_r <= '0';
valid_r <= '0';
xyz_in.x <= zero_in_sfix;
xyz_in.y <= zero_in_sfix;
xyz_in.z <= zero_in_sfix;
else
ready_r <= '1';
valid_r <= ce;
xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
end if;
end process;
reg_out : process (rst, ce, ready_r, valid_r, xyz_out)
begin
if (rst = '1') then
ready <= '0';
valid <= '0';
xout <= zero_out_sfix;
yout <= zero_out_sfix;
zout <= zero_out_sfix;
else
ready <= ready_r;
valid <= valid_r;
xout <= xyz_out.x;
yout <= xyz_out.y;
zout <= xyz_out.z;
end if;
end process;
end generate;
------------------------------------------------------------
gen_reg_in: if (reg_mode = reg_mode_in) generate
reg_in : process (rst, clk, ce, xin, yin, zin)
begin
if (rst = '1') then
ready_r <= '0';
valid_r <= '0';
xyz_in.x <= zero_in_sfix;
xyz_in.y <= zero_in_sfix;
xyz_in.z <= zero_in_sfix;
elsif rising_edge(clk) then
ready_r <= '1';
valid_r <= ce;
if (ce = '1') then
xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
end if;
end if;
end process;
reg_out : process (rst, ready_r, valid_r, xyz_out)
begin
if (rst = '1') then
ready <= '0';
valid <= '0';
xout <= zero_out_sfix;
yout <= zero_out_sfix;
zout <= zero_out_sfix;
else
ready <= ready_r;
valid <= valid_r;
xout <= xyz_out.x;
yout <= xyz_out.y;
zout <= xyz_out.z;
end if;
end process;
end generate;
------------------------------------------------------------
gen_reg_out: if (reg_mode = reg_mode_out) generate
reg_in : process (rst, ce, xin, yin, zin)
begin
if (rst = '1') then
ready_r <= '0';
valid_r <= '0';
xyz_in.x <= zero_in_sfix;
xyz_in.y <= zero_in_sfix;
xyz_in.z <= zero_in_sfix;
else
ready_r <= '1';
valid_r <= ce;
xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
end if;
end process;
reg_out : process (rst, clk, ce, ready_r, valid_r, xyz_out)
begin
if (rst = '1') then
ready <= '0';
valid <= '0';
xout <= zero_out_sfix;
yout <= zero_out_sfix;
zout <= zero_out_sfix;
elsif rising_edge(clk) then
ready <= ready_r;
valid <= valid_r;
if (ce = '1') then
xout <= xyz_out.x;
yout <= xyz_out.y;
zout <= xyz_out.z;
end if;
end if;
end process;
end generate;
------------------------------------------------------------
gen_reg_inout: if (reg_mode = reg_mode_inout) generate
reg_in : process (rst, clk, ce, xin, yin, zin)
begin
if (rst = '1') then
ready_r <= '0';
valid_r <= '0';
xyz_in.x <= zero_in_sfix;
xyz_in.y <= zero_in_sfix;
xyz_in.z <= zero_in_sfix;
elsif rising_edge(clk) then
ready_r <= '1';
valid_r <= ce;
if (ce = '1') then
xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
end if;
end if;
end process;
reg_out : process (rst, clk, ce, ready_r, valid_r, xyz_out)
begin
if (rst = '1') then
ready <= '0';
valid <= '0';
xout <= zero_out_sfix;
yout <= zero_out_sfix;
zout <= zero_out_sfix;
elsif rising_edge(clk) then
ready <= ready_r;
valid <= valid_r;
if (ce = '1') then
xout <= xyz_out.x;
yout <= xyz_out.y;
zout <= xyz_out.z;
end if;
end if;
end process;
end generate;
------------------------------------------------------------
cordic_post_stage: process(xyz_in, cordic_mode)
begin
xyz_out.x <= resize(xyz_in.x, xyz_out.x'left, xyz_out.x'right);
xyz_out.y <= resize(xyz_in.y, xyz_out.y'left, xyz_out.y'right);
xyz_out.z <= resize(xyz_in.z, xyz_out.z'left, xyz_out.z'right);
case cordic_mode is
when cordic_mode_rotate =>
xyz_out.x <= resize(xyz_in.x * to_sfixed(gain_tbl(nbits_out-1), xyz_in.x), xyz_out.x'left, xyz_out.x'right, cordic_round_mode, cordic_saturate_mode);
xyz_out.y <= resize(xyz_in.y * to_sfixed(gain_tbl(nbits_out-1), xyz_in.y), xyz_out.y'left, xyz_out.y'right, cordic_round_mode, cordic_saturate_mode);
xyz_out.z <= resize(xyz_in.z, xyz_out.z'left, xyz_out.z'right, cordic_round_mode, cordic_saturate_mode);
when cordic_mode_vector =>
xyz_out.x <= resize(xyz_in.x * to_sfixed(gain_tbl(nbits_out-1), xyz_in.x), xyz_out.x'left, xyz_out.x'right, cordic_round_mode, cordic_saturate_mode);
xyz_out.y <= resize(xyz_in.y, xyz_out.y'left, xyz_out.y'right, cordic_round_mode, cordic_saturate_mode);
xyz_out.z <= resize(xyz_in.z, xyz_out.z'left, xyz_out.z'right, cordic_round_mode, cordic_saturate_mode);
when others => null;
end case;
end process;
------------------------------------------------------------
end Behavioral;
lib/radio/cordic/src/cordic_stage_pre.vhd
+314
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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:16:14 10/02/05
-- Design Name:
-- Module Name: cordic_stage_pre - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
use work.fixed_pkg.all;
use work.cordic_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity cordic_stage_pre is
Generic
(
nbits : integer := 8;
nbits_frac : integer := 6;
nbits_out : integer := 8;
nbits_frac_out : integer := 6;
reg_mode : reg_mode_t := reg_mode_in
);
Port
(
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
xin : in sfixed;
yin : in sfixed;
zin : in sfixed;
xout : out sfixed;
yout : out sfixed;
zout : out sfixed;
cordic_mode : in cordic_mode_t;
ready : out std_logic;
valid : out std_logic
);
end cordic_stage_pre;
architecture Behavioral of cordic_stage_pre is
type xyz_in_t is record
x : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
y : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
z : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
end record;
type xyz_out_t is record
x : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
y : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
z : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
end record;
constant zero_in_sfix : sfixed := to_sfixed(0.0, sproto(nbits, nbits_frac)'high, sproto(nbits, nbits_frac)'low);
constant zero_out_sfix : sfixed := to_sfixed(0.0, sproto(nbits_out, nbits_frac_out)'high, sproto(nbits_out, nbits_frac_out)'low);
constant pi_out_sfix : sfixed := to_sfixed(pi, sproto(nbits_out, nbits_frac_out)'high, sproto(nbits_out, nbits_frac_out)'low);
constant pi2_out_sfix : sfixed := to_sfixed(pi/2.0, sproto(nbits_out, nbits_frac_out)'high, sproto(nbits_out, nbits_frac_out)'low);
constant pi2_in_sfix : sfixed := to_sfixed(pi/2.0, sproto(nbits, nbits_frac)'high, sproto(nbits, nbits_frac)'low);
signal xyz_in : xyz_in_t;
signal xyz_out : xyz_out_t;
signal valid_r, ready_r : std_logic;
------------------------------------------------------------
begin
gen_direct: if reg_mode = none generate
reg_in : process (rst, ce, xin, yin, zin)
begin
if (rst = '1') then
ready_r <= '0';
valid_r <= '0';
xyz_in.x <= zero_in_sfix;
xyz_in.y <= zero_in_sfix;
xyz_in.z <= zero_in_sfix;
else
ready_r <= '1';
valid_r <= ce;
xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
end if;
end process;
reg_out : process (rst, ce, ready_r, valid_r, xyz_out)
begin
if (rst = '1') then
ready <= '0';
valid <= '0';
xout <= zero_out_sfix;
yout <= zero_out_sfix;
zout <= zero_out_sfix;
else
ready <= ready_r;
valid <= valid_r;
xout <= xyz_out.x;
yout <= xyz_out.y;
zout <= xyz_out.z;
end if;
end process;
end generate;
------------------------------------------------------------
gen_reg_in: if (reg_mode = reg_mode_in) generate
reg_in : process (rst, clk, ce, xin, yin, zin)
begin
if (rst = '1') then
ready_r <= '0';
valid_r <= '0';
xyz_in.x <= zero_in_sfix;
xyz_in.y <= zero_in_sfix;
xyz_in.z <= zero_in_sfix;
elsif rising_edge(clk) then
ready_r <= '1';
valid_r <= ce;
if (ce = '1') then
xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
end if;
end if;
end process;
reg_out : process (rst, ready_r, valid_r, xyz_out)
begin
if (rst = '1') then
ready <= '0';
valid <= '0';
xout <= zero_out_sfix;
yout <= zero_out_sfix;
zout <= zero_out_sfix;
else
ready <= ready_r;
valid <= valid_r;
xout <= xyz_out.x;
yout <= xyz_out.y;
zout <= xyz_out.z;
end if;
end process;
end generate;
------------------------------------------------------------
gen_reg_out: if (reg_mode = reg_mode_out) generate
reg_in : process (rst, ce, xin, yin, zin)
begin
if (rst = '1') then
ready_r <= '0';
valid_r <= '0';
xyz_in.x <= zero_in_sfix;
xyz_in.y <= zero_in_sfix;
xyz_in.z <= zero_in_sfix;
else
ready_r <= '1';
valid_r <= ce;
xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
end if;
end process;
reg_out : process (rst, clk, ce, ready_r, valid_r, xyz_out)
begin
if (rst = '1') then
ready <= '0';
valid <= '0';
xout <= zero_out_sfix;
yout <= zero_out_sfix;
zout <= zero_out_sfix;
elsif rising_edge(clk) then
ready <= ready_r;
valid <= valid_r;
if (ce = '1') then
xout <= xyz_out.x;
yout <= xyz_out.y;
zout <= xyz_out.z;
end if;
end if;
end process;
end generate;
------------------------------------------------------------
gen_reg_inout: if (reg_mode = reg_mode_inout) generate
reg_in : process (rst, clk, ce, xin, yin, zin)
begin
if (rst = '1') then
ready_r <= '0';
valid_r <= '0';
xyz_in.x <= zero_in_sfix;
xyz_in.y <= zero_in_sfix;
xyz_in.z <= zero_in_sfix;
elsif rising_edge(clk) then
ready_r <= '1';
valid_r <= ce;
if (ce = '1') then
xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
end if;
end if;
end process;
reg_out : process (rst, clk, ce, ready_r, valid_r, xyz_out)
begin
if (rst = '1') then
ready <= '0';
valid <= '0';
xout <= zero_out_sfix;
yout <= zero_out_sfix;
zout <= zero_out_sfix;
elsif rising_edge(clk) then
ready <= ready_r;
valid <= valid_r;
if (ce = '1') then
xout <= xyz_out.x;
yout <= xyz_out.y;
zout <= xyz_out.z;
end if;
end if;
end process;
end generate;
------------------------------------------------------------
cordic_proc_pre_stage: process(xyz_in, cordic_mode)
begin
xyz_out.x <= resize(xyz_in.x, xyz_out.x'left, xyz_out.x'right);
xyz_out.y <= resize(xyz_in.y, xyz_out.y'left, xyz_out.y'right);
xyz_out.z <= resize(xyz_in.z, xyz_out.z'left, xyz_out.z'right);
case cordic_mode is
when cordic_mode_rotate =>
if (xyz_in.z < -pi2_in_sfix) then
xyz_out.x <= resize(-xyz_in.x, xyz_out.x'left, xyz_out.x'right);
xyz_out.y <= resize(-xyz_in.y, xyz_out.y'left, xyz_out.y'right);
xyz_out.z <= resize(xyz_in.z + pi_out_sfix, xyz_out.z'left, xyz_out.z'right);
elsif (xyz_in.z > pi2_in_sfix) then
xyz_out.x <= resize(-xyz_in.x, xyz_out.x'left, xyz_out.x'right);
xyz_out.y <= resize(-xyz_in.y, xyz_out.y'left, xyz_out.y'right);
xyz_out.z <= resize(xyz_in.z - pi_out_sfix, xyz_out.z'left, xyz_out.z'right);
end if;
when cordic_mode_vector =>
-- if (xyz_in.x < zero_in_sfix) then
-- xyz_out.x <= resize(-xyz_in.x, xyz_out.x'left, xyz_out.x'right);
-- xyz_out.y <= resize(-xyz_in.y, xyz_out.y'left, xyz_out.y'right);
-- xyz_out.z <= resize(xyz_in.z - pi_out_sfix, xyz_out.z'left, xyz_out.z'right);
-- end if;
if (xyz_in.y < zero_in_sfix) then
xyz_out.x <= resize(-xyz_in.y, xyz_out.x'left, xyz_out.x'right);
xyz_out.y <= resize(xyz_in.x, xyz_out.y'left, xyz_out.y'right);
xyz_out.z <= resize(xyz_in.z + pi2_out_sfix, xyz_out.z'left, xyz_out.z'right);
else
xyz_out.x <= resize(xyz_in.y, xyz_out.x'left, xyz_out.x'right);
xyz_out.y <= resize(-xyz_in.x, xyz_out.y'left, xyz_out.y'right);
xyz_out.z <= resize(xyz_in.z - pi2_out_sfix, xyz_out.z'left, xyz_out.z'right);
end if;
when others => null;
end case;
end process;
------------------------------------------------------------
end Behavioral;
-- if (y < 0) then
-- x' = -y
-- y' = x
-- z' = z + pi/2;
-- else
-- x' = y
-- y' = -x
-- z' = z - pi/2;
-- end if;
--
-- if (x < 0) then
-- x' = -x;
-- y' = -y;
-- z' = z - pi
-- else
-- x' = x;
-- y' = y;
-- z' = z
-- end if;
lib/radio/cordic/src/cordic_top.vhd
+460
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@@ -0,0 +1,460 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:52:30 10/02/05
-- Design Name:
-- Module Name: cordic_top - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
USE ieee.numeric_std.ALL;
use work.fixed_pkg.all;
use work.cordic_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity cordic_top is
Generic
(
nbits : integer := 8;
nbits_frac : integer := 6;
nbits_out : integer := 8;
nbits_frac_out : integer := 6
);
Port (
rst : in std_logic;
clk : in std_logic;
ce : in std_logic;
xin : in sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
yin : in sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
zin : in sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
xout : out sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
yout : out sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
zout : out sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
ready : out std_logic;
valid : out std_logic;
cordic_mode : in cordic_mode_t
);
end cordic_top;
architecture Behavioral of cordic_top is
-----------------------------------------------------------------------
COMPONENT cordic_stage_pre is
GENERIC
(
nbits : integer;
nbits_frac : integer;
nbits_out : integer;
nbits_frac_out : integer;
reg_mode : reg_mode_t
);
PORT
(
rst : in std_logic;
clk : in std_logic;
ce : in std_logic;
xin : in sfixed;
yin : in sfixed;
zin : in sfixed;
xout : out sfixed;
yout : out sfixed;
zout : out sfixed;
cordic_mode : in cordic_mode_t;
ready : OUT std_logic;
valid : out std_logic
);
END COMPONENT;
COMPONENT cordic_stage
GENERIC
(
nbits : integer;
nbits_frac : integer;
nbits_out : integer;
nbits_frac_out : integer;
reg_mode : reg_mode_t
);
PORT(
rst : IN std_logic;
clk : IN std_logic;
ce : IN std_logic;
xin : IN sfixed;
yin : IN sfixed;
zin : IN sfixed;
xout : OUT sfixed;
yout : OUT sfixed;
zout : OUT sfixed;
coeff : in sfixed;
dir_cw : in std_logic;
stage_count : IN integer;
cordic_mode : in cordic_mode_t;
ready : OUT std_logic;
valid : out std_logic
);
END COMPONENT;
COMPONENT cordic_stage_post is
GENERIC
(
nbits : integer;
nbits_frac : integer;
nbits_out : integer;
nbits_frac_out : integer;
reg_mode : reg_mode_t
);
PORT
(
rst : in std_logic;
clk : in std_logic;
ce : in std_logic;
xin : in sfixed;
yin : in sfixed;
zin : in sfixed;
xout : out sfixed;
yout : out sfixed;
zout : out sfixed;
cordic_mode : in cordic_mode_t;
ready : OUT std_logic;
valid : out std_logic
);
END COMPONENT;
COMPONENT rom_arctan is
GENERIC
(
nbits : integer := 8;
nbits_frac : integer := 8
);
PORT
(
addr : in unsigned(6 downto 0);
dout : out sfixed
);
END COMPONENT;
-----------------------------------------------------------------------
type state_type is (st_input, st_ready, st_pre_stage_in, st_pre_stage_out, st_proc_stage_in, st_proc_stage_out, st_post_stage_in, st_post_stage_out);
constant zero_sfix : sfixed := to_sfixed(0.0, sproto(nbits_out, nbits_frac_out)'high, sproto(nbits_out, nbits_frac_out)'low);
-- Define number of LSB guard bits
constant guard_nbits : integer := integer(log2(real(nbits))+0.5);
-- Define number of internal stage bits
constant stage_nbits : integer := nbits + guard_nbits; -- add more internal precision
constant stage_nbits_frac : integer := nbits_frac;
-- Set number of coefficient bits
constant coeff_nbits : integer := nbits;
constant coeff_nbits_frac : integer := nbits; -- coeffs have no integer part
-- Set number of iteration with respect to bit size
constant max_stage_count : integer := stage_nbits;
-- INPUT
-- Input pre stage
signal pre_stage_en : std_logic;
signal xin_pre, yin_pre, zin_pre : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
-- Output pre stage
signal pre_stage_ready, pre_stage_valid : std_logic;
signal xout_pre, yout_pre, zout_pre : sfixed(sproto(stage_nbits, stage_nbits_frac)'high downto sproto(stage_nbits, stage_nbits_frac)'low);
-- Input processing stage
signal proc_stage_en: std_logic;
signal xin_stage, yin_stage, zin_stage : sfixed(sproto(stage_nbits, stage_nbits_frac)'high downto sproto(stage_nbits, stage_nbits_frac)'low);
-- Output processing stage
signal proc_stage_ready, proc_stage_valid : std_logic;
signal xout_stage, yout_stage, zout_stage : sfixed(sproto(stage_nbits, stage_nbits_frac)'high downto sproto(stage_nbits, stage_nbits_frac)'low);
-- Input post stage
signal post_stage_en : std_logic;
signal xin_post, yin_post, zin_post : sfixed(sproto(stage_nbits, stage_nbits_frac)'high downto sproto(stage_nbits, stage_nbits_frac)'low);
-- Output post stage
signal post_stage_ready, post_stage_valid : std_logic;
signal xout_post, yout_post, zout_post : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
-- ROM
signal rom_addr : unsigned (6 downto 0);
signal rom_data : sfixed(sproto(coeff_nbits, coeff_nbits_frac)'high downto sproto(coeff_nbits, coeff_nbits_frac)'low);
-- Misc.
signal state, next_state : state_type;
signal count : integer range 0 to max_stage_count-1 := 0;
signal count_en, dir_cw, valid_s : std_logic;
begin
-----------------------------------------------------------------------
cordic_proc_mode : process(rst, zin_stage, yin_stage, cordic_mode)
begin
if (rst = '1') then
dir_cw <= '0';
else
dir_cw <= '0';
case cordic_mode is
when cordic_mode_rotate =>
if (zin_stage(zin_stage'high) = '1') then
dir_cw <= '1';
end if;
when cordic_mode_vector =>
if (yin_stage(yin_stage'high) = '1') then
dir_cw <= '0';
else
dir_cw <= '1';
end if;
when others => null;
end case;
end if;
end process;
-----------------------------------------------------------------------
counter: process (clk, rst, count, count_en)
begin
if (rst = '1') then
count <= 0;
rom_addr <= (others => '0');
else
if (clk'event and clk = '1') then
rom_addr <= to_unsigned(count, rom_addr'length);
if (count_en = '1' and count < max_stage_count-1) then
count <= count + 1 after tpd;
else
count <= 0;
end if;
end if;
end if;
end process;
-----------------------------------------------------------------------
OUTPUT_PROC: process (clk, rst, state, xout_stage, yout_stage, zout_stage)
begin
if (rst='1') then
valid <= '0';
xout <= zero_sfix after tpd;
yout <= zero_sfix after tpd;
zout <= zero_sfix after tpd;
-- assign other outputs to reset value
elsif (clk'event and clk = '1') then
valid <= '0';
if(post_stage_valid = '1') then
xout <= xout_post;
yout <= yout_post;
zout <= zout_post;
valid <= '1';
end if;
end if;
end process;
-----------------------------------------------------------------------
--Insert the following in the architecture after the begin keyword
FSM_PROC: process (clk, rst, xout_stage, yout_stage, zout_stage)
begin
if (rst='1') then
state <= st_ready;
-- assign other outputs to reset value
elsif (clk'event and clk = '1') then
state <= next_state after tpd;
-- assign other outputs to internal signals
end if;
end process;
--MOORE State Machine - Outputs based on state only
Control_proc: process (state, xin, yin, zin, xout_pre, yout_pre, zout_pre, xout_stage, yout_stage, zout_stage)
begin
--insert statements to decode internal output signals
--below is simple example
ready <= '0';
valid_s <= '0';
count_en <= '0';
pre_stage_en <= '0';
proc_stage_en <= '0';
post_stage_en <= '0';
xin_pre <= xin;
yin_pre <= yin;
zin_pre <= zin;
xin_stage <= xout_stage;
yin_stage <= yout_stage;
zin_stage <= zout_stage;
xin_post <= xout_stage;
yin_post <= yout_stage;
zin_post <= zout_stage;
case (state) is
when st_ready =>
ready <= '1';
when st_pre_stage_in =>
pre_stage_en <= '1';
when st_pre_stage_out =>
count_en <= '1';
proc_stage_en <= '1';
xin_stage <= xout_pre;
yin_stage <= yout_pre;
zin_stage <= zout_pre;
when st_proc_stage_in =>
count_en <= '1';
proc_stage_en <= '1';
when st_post_stage_in =>
post_stage_en <= '1';
when others =>
end case;
end process;
NEXT_STATE_DECODE: process (state, ce, count)
begin
--declare default state for next_state to avoid latches
next_state <= state; --default is to stay in current state
--insert statements to decode next_state
--below is a simple example
case (state) is
when st_ready =>
if ce = '1' then
next_state <= st_input;
end if;
when st_input =>
if ce = '0' then
next_state <= st_pre_stage_in;
end if;
when st_pre_stage_in =>
next_state <= st_pre_stage_out;
when st_pre_stage_out =>
next_state <= st_proc_stage_in;
when st_proc_stage_in =>
if (count = max_stage_count-2) then
next_state <= st_post_stage_in;
end if;
when st_post_stage_in =>
next_state <= st_ready;
when others =>
next_state <= st_ready;
end case;
end process;
-----------------------------------------------------------------------
Inst_cordic_stage_pre: cordic_stage_pre
GENERIC MAP
(
nbits => nbits,
nbits_frac => nbits_frac,
nbits_out => stage_nbits,
nbits_frac_out => stage_nbits_frac,
reg_mode => reg_mode_in
)
PORT MAP
(
rst => rst,
clk => clk,
ce => pre_stage_en,
xin => xin_pre,
yin => yin_pre,
zin => zin_pre,
xout => xout_pre,
yout => yout_pre,
zout => zout_pre,
ready => pre_stage_ready,
valid => pre_stage_valid,
cordic_mode => cordic_mode
);
Inst_cordic_stage: cordic_stage
GENERIC MAP
(
nbits => stage_nbits,
nbits_frac => stage_nbits_frac,
nbits_out => stage_nbits,
nbits_frac_out => stage_nbits_frac,
reg_mode => reg_mode_in
)
PORT MAP
(
rst => rst,
clk => clk,
ce => proc_stage_en,
xin => xin_stage,
yin => yin_stage,
zin => zin_stage,
xout => xout_stage,
yout => yout_stage,
zout => zout_stage,
coeff => rom_data,
dir_cw => dir_cw,
stage_count => count,
ready => proc_stage_ready,
valid => proc_stage_valid,
cordic_mode => cordic_mode
);
Inst_cordic_stage_post: cordic_stage_post
GENERIC MAP
(
nbits => stage_nbits,
nbits_frac => stage_nbits_frac,
nbits_out => nbits_out,
nbits_frac_out => nbits_frac_out,
reg_mode => reg_mode_in
)
PORT MAP
(
rst => rst,
clk => clk,
ce => post_stage_en,
xin => xin_post,
yin => yin_post,
zin => zin_post,
xout => xout_post,
yout => yout_post,
zout => zout_post,
ready => post_stage_ready,
valid => post_stage_valid,
cordic_mode => cordic_mode
);
Inst_rom_arctan: rom_arctan
GENERIC MAP
(
nbits => coeff_nbits,
nbits_frac => coeff_nbits_frac
)
PORT MAP
(
addr => rom_addr,
dout => rom_data
);
--------------------------------------------------------------------
end Behavioral;
lib/radio/cordic/src/tb_cordic_pipe_top.vhd
+649
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@@ -0,0 +1,649 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:16:42 10/02/2005
-- Design Name: cordic_top
-- Module Name: tb_cordic_top.vhd
-- Project Name: cordic
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: cordic_top
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
-- Results:In 16i2 and Out 16i0
------------------------------
-- xmean = -3.051757808671257e-7
-- ymean = 1.525878906192144e-6
-- zmean = 0.0
-- xvar = 7.723598281502283e-10
-- yvar = 8.539443970667266e-10
-- zvar = 0.0
-- xstd = 2.779136247380161e-5
-- ystd = 2.922232703031582e-5
-- zstd = 0.0
--
------------------------------
-- Results:In 16i2 and Out 16i1
------------------------------
-- xmean = 6.103515628828741e-7
-- ymean = -1.220703125057855e-6
-- zmean = 0.0
-- xvar = 9.76293486677989e-10
-- yvar = 7.934037490259732e-10
-- zvar = 0.0
-- xstd = 3.124569549038697e-5
-- ystd = 2.816742354256017e-5
-- zstd = 0.0
--
------------------------------
-- Results:In 16i2 and Out 16i2
------------------------------
-- xmean = 2.441406250382875e-6
-- ymean = -1.220703125057855e-6
-- zmean = 0.0
-- xvar = 2.126680036682826e-9
-- yvar = 2.117107754473399e-9
-- zvar = 0.0
-- xstd = 4.611594124251206e-5
-- ystd = 4.601203923402438e-5
-- zstd = 0.0
--
------------------------------
-- Results:In 32i2 and Out 32i0
------------------------------
-- xmean = -9.312842871812748e-12
-- ymean = -5.78558739545293e-17
-- zmean = 0.0
-- xvar = 1.671709854744817e-19
-- yvar = 1.790442305004033e-19
-- zvar = 0.0
-- xstd = 4.088654857951228e-10
-- ystd = 4.231361843430591e-10
-- zstd = 0.0
--
------------------------------
-- Results:In 32i2 and Out 32i1
------------------------------
-- xmean = 9.313608620496825e-12
-- ymean = 9.31316789028083e-12
-- zmean = 0.0
-- xvar = 1.876480788588237e-19
-- yvar = 2.238344116260579e-19
-- zvar = 0.0
-- xstd = 4.331836548841885e-10
-- ystd = 4.731114156581492e-10
-- zstd = 0.0
--
------------------------------
-- Results:In 32i2 and Out 32i2
------------------------------
-- xmean = -3.72525201102771e-11
-- ymean = -5.78558739545293e-17
-- zmean = 0.0
-- xvar = 5.458335981037092e-19
-- yvar = 5.704280631341228e-19
-- zvar = 0.0
-- xstd = 7.388055211648797e-10
-- ystd = 7.552668820583376e-10
-- zstd = 0.0
--
------------------------------
-- Results:In 64i2 and Out 64i0
------------------------------
-- xmean = 3.45418680637588e-17
-- ymean = 3.859475130978118e-17
-- zmean = 2.205267218835516e-16
-- xvar = 5.54111959258452e-28
-- yvar = 5.549496221074054e-28
-- zvar = 7.916891206490056e-29
-- xstd = 2.353958281827551e-14
-- ystd = 2.355736874329146e-14
-- zstd = 8.897691389619023e-15
--
------------------------------
-- Results:In 64i2 and Out 64i1
------------------------------
-- xmean = 3.45418680637588e-17
-- ymean = 3.859475130978118e-17
-- zmean = 2.205267218835516e-16
-- xvar = 5.541120861185077e-28
-- yvar = 5.549497432144743e-28
-- zvar = 7.916856202525234e-29
-- xstd = 2.353958551288674e-14
-- ystd = 2.355737131376237e-14
-- zstd = 8.897671719346156e-15
--
------------------------------
-- Results:In 64i2 and Out 64i2
------------------------------
-- xmean = 3.343164503913365e-17
-- ymean = 3.859475130978118e-17
-- zmean = 2.205223850748616e-16
-- xvar = 5.540559656182732e-28
-- yvar = 5.549495010008071e-28
-- zvar = 7.916821581863743e-29
-- xstd = 2.353839343749427e-14
-- ystd = 2.355736617283025e-14
-- zstd = 8.897652264425568e-15
--
--------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
USE ieee.numeric_std.ALL;
use std.textio.all; -- Imports the standard textio package.
library work;
use work.fixed_pkg.all;
use work.cordic_pkg.all;
use work.PCK_FIO.all;
ENTITY tb_cordic_pipe_top IS
Generic (
nbits_x_in : integer := 18;
nbits_y_in : integer := 18;
nbits_z_in : integer := 24;
nbits_frac_x_in : integer := 17;
nbits_frac_y_in : integer := 17;
nbits_frac_z_in : integer := 22;
nbits_x_out : integer := 18;
nbits_y_out : integer := 18;
nbits_z_out : integer := 18;
nbits_frac_x_out : integer := 17;
nbits_frac_y_out : integer := 17;
nbits_frac_z_out : integer := 17
);
END tb_cordic_pipe_top;
ARCHITECTURE behavior OF tb_cordic_pipe_top IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT cordic_pipe_top
GENERIC
(
cordic_mode : cordic_mode_t;
z_range : real;
gain_corr_mode : gain_corr_mode_t;
nstages : integer;
nbits_x_in : integer;
nbits_y_in : integer;
nbits_z_in : integer;
nbits_frac_x_in : integer;
nbits_frac_y_in : integer;
nbits_frac_z_in : integer;
nbits_x_out : integer;
nbits_y_out : integer;
nbits_z_out : integer;
nbits_frac_x_out : integer;
nbits_frac_y_out : integer;
nbits_frac_z_out : integer
);
PORT
(
rst : in std_logic;
clk : in std_logic;
vld_in : in std_logic;
xin : in sfixed;
yin : in sfixed;
zin : in sfixed;
xout : out sfixed;
yout : out sfixed;
zout : out sfixed;
vld_out : out std_logic
);
END COMPONENT;
--Constants
constant num_cycles : integer := 5;
constant num_steps_per_cycle : integer := 100;
constant PERIOD : time := 10 ns;
--Inputs
SIGNAL clk : std_logic := '0';
SIGNAL rst : std_logic := '1';
SIGNAL vld_in : std_logic := '0';
SIGNAL xin : sfixed(sproto(nbits_x_in, nbits_frac_x_in)'high downto sproto(nbits_x_in, nbits_frac_x_in)'low) := to_sfixed(0.0, sproto(nbits_x_in, nbits_frac_x_in)'high, sproto(nbits_x_in, nbits_frac_x_in)'low);
SIGNAL yin : sfixed(sproto(nbits_y_in, nbits_frac_y_in)'high downto sproto(nbits_y_in, nbits_frac_y_in)'low) := to_sfixed(0.0, sproto(nbits_y_in, nbits_frac_y_in)'high, sproto(nbits_y_in, nbits_frac_y_in)'low);
SIGNAL zin : sfixed(sproto(nbits_z_in, nbits_frac_z_in)'high downto sproto(nbits_z_in, nbits_frac_z_in)'low) := to_sfixed(0.0, sproto(nbits_z_in, nbits_frac_z_in)'high, sproto(nbits_z_in, nbits_frac_z_in)'low);
--Outputs
SIGNAL xout : sfixed(sproto(nbits_x_out, nbits_frac_x_out)'high downto sproto(nbits_x_out, nbits_frac_x_out)'low);
SIGNAL yout : sfixed(sproto(nbits_y_out, nbits_frac_y_out)'high downto sproto(nbits_y_out, nbits_frac_y_out)'low);
SIGNAL zout : sfixed(sproto(nbits_z_out, nbits_frac_z_out)'high downto sproto(nbits_z_out, nbits_frac_z_out)'low);
SIGNAL vld_out : std_logic;
--------------------------------------------------------------------
--Functions
--------------------------------------------------------------------
type real_vector_t is array (natural range <>) of real;
function mean(x : real_vector_t; len : integer) return real is
variable xm : real := 0.0;
begin
for i in 0 to len-1 loop
xm := xm + x(i);
end loop;
return xm / real(len);
end mean;
--------------------------------------------------------------------
function var(x : real_vector_t; len : integer) return real is
variable xv, xm, xp : real := 0.0;
begin
xm := mean(x, len);
for i in 0 to len-1 loop
xp := x(i) - xm;
xv := xv + xp*xp;
end loop;
return xv / real(len);
end var;
--------------------------------------------------------------------
function stddev(x : real_vector_t; len : integer) return real is
variable xv, xs : real := 0.0;
begin
xv := var(x, len);
if xv > 0.0 then
xs := sqrt(xv);
end if;
return xs;
end stddev;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: cordic_pipe_top
GENERIC MAP
(
cordic_mode => cordic_mode_rotate,
z_range => pi,
gain_corr_mode => gain_mode_disabled,
nstages => 18,
nbits_x_in => nbits_x_in,
nbits_frac_x_in => nbits_frac_x_in,
nbits_y_in => nbits_y_in,
nbits_frac_y_in => nbits_frac_y_in,
nbits_z_in => nbits_z_in,
nbits_frac_z_in => nbits_frac_z_in,
nbits_x_out => nbits_x_out,
nbits_frac_x_out => nbits_frac_x_out,
nbits_y_out => nbits_y_out,
nbits_frac_y_out => nbits_frac_y_out,
nbits_z_out => nbits_z_out,
nbits_frac_z_out => nbits_frac_z_out
)
PORT MAP
(
rst => rst,
clk => clk,
vld_in => vld_in,
xin => xin,
yin => yin,
zin => zin,
xout => xout,
yout => yout,
zout => zout,
vld_out => vld_out
);
tb_clk : PROCESS
BEGIN
clk <= not clk;
wait for PERIOD/2;
END PROCESS;
tb : PROCESS
variable xerr, yerr, zerr : real_vector_t (0 to num_steps_per_cycle*num_cycles-1);
variable xvar, xstd, xmean, yvar, ystd, ymean, zvar, zstd, zmean : real;
variable argx, argy, argz : real := 0.0;
variable phi, dphi : real := 0.0;
file RESULT: text open write_mode is "STD_OUTPUT";
file RESULT_X: text open write_mode is "x.txt";
file RESULT_Y: text open write_mode is "y.txt";
file RESULT_Z: text open write_mode is "z.txt";
variable L: line;
variable j : integer := 0;
BEGIN
-- Wait 100 ns for global reset to finish
wait for 4*PERIOD;
rst <= '0';
wait for 2*PERIOD;
for i in 0 to arctan_tbl'length-1 loop
fprint(RESULT, L,"coeff arctan (%d) = %s\n", fo(i), REAL'image(arctan_tbl(i)));
end loop;
for i in 0 to gain_tbl'length-1 loop
fprint(RESULT, L,"coeff gain (%d) = %s\n", fo(i), REAL'image(gain_tbl(i)));
end loop;
fprint(RESULT, L,"Pi = %s\n", REAL'image(MATH_PI));
fprint(RESULT, L,"sqrt(2) = %s\n", REAL'image(SQRT(2.0)));
fprint(RESULT, L,"1/sqrt(2) = %s\n", REAL'image(1.0/SQRT(2.0)));
-------------------------------------------
-- 1
argx := 1.0;
argy := 0.0;
argz := -pi/4.0;
wait until rising_edge(clk);
xin <= to_sfixed(argx, xin, false, true);
yin <= to_sfixed(argy, yin, false, true);
zin <= to_sfixed(argz, zin, false, true);
vld_in <= '1';
wait until rising_edge(clk);
vld_in <= '0';
wait until rising_edge(clk) and vld_out = '1';
fprint(RESULT, L,"--------------------------------\n");
-- fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode));
fprint(RESULT, L,"Xn = An*[X0*cos(Z0) - Y0*sin(Z0)]\n");
fprint(RESULT, L,"Yn = An*[Y0*cos(Z0) + X0*sin(Z0)]\n");
fprint(RESULT, L,"\n");
fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
fprint(RESULT, L,"\n");
fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
fprint(RESULT, L,"\n");
-------------------------------------------
-- 2
argx := 1.0;
argy := 0.0;
argz := pi/2.0;
wait until rising_edge(clk);
xin <= to_sfixed(argx, xin, false, true);
yin <= to_sfixed(argy, yin, false, true);
zin <= to_sfixed(argz, zin, false, true);
vld_in <= '1';
wait until rising_edge(clk);
vld_in <= '0';
wait until rising_edge(clk) and vld_out = '1';
fprint(RESULT, L,"--------------------------------\n");
-- fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode));
fprint(RESULT, L,"Xn = An*[X0*cos(Z0) - Y0*sin(Z0)]\n");
fprint(RESULT, L,"Yn = An*[Y0*cos(Z0) + X0*sin(Z0)]\n");
fprint(RESULT, L,"\n");
fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
fprint(RESULT, L,"\n");
fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
fprint(RESULT, L,"\n");
-------------------------------------------
-- 3
argx := sqrt2_inv;
argy := -sqrt2_inv;
argz := pi/2.0;
wait until rising_edge(clk);
xin <= to_sfixed(argx, xin, false, true);
yin <= to_sfixed(argy, yin, false, true);
zin <= to_sfixed(argz, zin, false, true);
vld_in <= '1';
wait until rising_edge(clk);
vld_in <= '0';
wait until rising_edge(clk) and vld_out = '1';
fprint(RESULT, L,"--------------------------------\n");
-- fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode));
fprint(RESULT, L,"Xn = An*[X0*cos(Z0) - Y0*sin(Z0)]\n");
fprint(RESULT, L,"Yn = An*[Y0*cos(Z0) + X0*sin(Z0)]\n");
fprint(RESULT, L,"\n");
fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
fprint(RESULT, L,"\n");
fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
fprint(RESULT, L,"\n");
-------------------------------------------
-- 4
argx := sqrt2_inv;
argy := -sqrt2_inv;
argz := -pi/4.0;
wait until rising_edge(clk);
xin <= to_sfixed(argx, xin, false, true);
yin <= to_sfixed(argy, yin, false, true);
zin <= to_sfixed(argz, zin, false, true);
vld_in <= '1';
wait until rising_edge(clk);
vld_in <= '0';
wait until rising_edge(clk) and vld_out = '1';
fprint(RESULT, L,"--------------------------------\n");
-- fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode));
fprint(RESULT, L,"Xn = An*[X0*cos(Z0) - Y0*sin(Z0)]\n");
fprint(RESULT, L,"Yn = An*[Y0*cos(Z0) + X0*sin(Z0)]\n");
fprint(RESULT, L,"\n");
fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
fprint(RESULT, L,"\n");
fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
fprint(RESULT, L,"\n");
-------------------------------------------
-- 5
argx := 1.0;
argy := 1.0;
argz := 0.0;
wait until rising_edge(clk);
xin <= to_sfixed(argx, xin, false, true);
yin <= to_sfixed(argy, yin, false, true);
zin <= to_sfixed(argz, zin, false, true);
vld_in <= '1';
wait until rising_edge(clk);
vld_in <= '0';
wait until rising_edge(clk) and vld_out = '1';
fprint(RESULT, L,"--------------------------------\n");
-- fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode));
fprint(RESULT, L,"Xn = An*sqrt(X0^2 + Y0^2)\n");
fprint(RESULT, L,"Zn = Z0 + arctan(Y0/X0)\n");
fprint(RESULT, L,"\n");
fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
fprint(RESULT, L,"\n");
fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
fprint(RESULT, L,"\n");
-------------------------------------------
-- 6
argx := sqrt2_inv;
argy := -sqrt2_inv;
argz := 0.0;
wait until rising_edge(clk);
xin <= to_sfixed(argx, xin, false, true);
yin <= to_sfixed(argy, yin, false, true);
zin <= to_sfixed(argz, zin, false, true);
vld_in <= '1';
wait until rising_edge(clk);
vld_in <= '0';
wait until rising_edge(clk) and vld_out = '1';
fprint(RESULT, L,"--------------------------------\n");
fprint(RESULT, L,"Xn = An*sqrt(X0^2 + Y0^2)\n");
fprint(RESULT, L,"Zn = Z0 + arctan(Y0/X0)\n");
fprint(RESULT, L,"\n");
fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
fprint(RESULT, L,"\n");
fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
fprint(RESULT, L,"\n");
-------------------------------------------
-- 7
argx := -sqrt2_inv;
argy := sqrt2_inv;
argz := 0.0;
wait until rising_edge(clk);
xin <= to_sfixed(argx, xin, false, true);
yin <= to_sfixed(argy, yin, false, true);
zin <= to_sfixed(argz, zin, false, true);
vld_in <= '1';
wait until rising_edge(clk);
vld_in <= '0';
wait until rising_edge(clk) and vld_out = '1';
fprint(RESULT, L,"--------------------------------\n");
-- fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode));
fprint(RESULT, L,"Xn = An*sqrt(X0^2 + Y0^2)\n");
fprint(RESULT, L,"Zn = Z0 + arctan(Y0/X0)\n");
fprint(RESULT, L,"\n");
fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
fprint(RESULT, L,"\n");
fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
fprint(RESULT, L,"\n");
-------------------------------------------
-- 8
argx := -sqrt2_inv;
argy := -sqrt2_inv;
argz := 0.0;
wait until rising_edge(clk);
xin <= to_sfixed(argx, xin, false, true);
yin <= to_sfixed(argy, yin, false, true);
zin <= to_sfixed(argz, zin, false, true);
vld_in <= '1';
wait until rising_edge(clk);
vld_in <= '0';
wait until rising_edge(clk) and vld_out = '1';
fprint(RESULT, L,"--------------------------------\n");
-- fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode));
fprint(RESULT, L,"Xn = An*sqrt(X0^2 + Y0^2)\n");
fprint(RESULT, L,"Zn = Z0 + arctan(Y0/X0)\n");
fprint(RESULT, L,"\n");
fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
fprint(RESULT, L,"\n");
fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
fprint(RESULT, L,"\n");
-------------------------------------------
-- Place stimulus here
wait for 10*PERIOD;
wait until rising_edge(clk) and vld_out = '0';
j := 0;
dphi := 2.0*pi/real(num_steps_per_cycle);
for k in 0 to num_cycles-1 loop
phi := -pi;
for i in 0 to num_steps_per_cycle-1 loop
xin <= to_sfixed(1.0, xin);
yin <= to_sfixed(0.0, yin);
zin <= to_sfixed(phi, zin, false, true);
vld_in <= '1';
wait until rising_edge(clk);
vld_in <= '0';
wait until rising_edge(clk) and vld_out = '1';
fprint(RESULT_X, L,"%s\n", REAL'image(to_real(xout)));
fprint(RESULT_Y, L,"%s\n", REAL'image(to_real(yout)));
fprint(RESULT_Z, L,"%s\n", REAL'image(to_real(zout)));
-- fprint(RESULT_X, L,"%s\n", REAL'image(cos(phi)));
-- fprint(RESULT_Y, L,"%s\n", REAL'image(sin(phi)));
-- fprint(RESULT_Z, L,"%s\n", REAL'image(0.0));
xerr(j) := to_real(xout) - cos(phi);
yerr(j) := to_real(yout) - sin(phi);
zerr(j) := to_real(zout);
j := j + 1;
phi := (phi + dphi);
end loop;
end loop;
xmean := mean(xerr, j);
ymean := mean(yerr, j);
zmean := mean(zerr, j);
xvar := var(xerr, j);
yvar := var(yerr, j);
zvar := var(zerr, j);
xstd := stddev(xerr, j);
ystd := stddev(yerr, j);
zstd := stddev(zerr, j);
fprint(RESULT, L,"------------------------------------------\n");
fprint(RESULT, L,"Results: \n");
fprint(RESULT, L,"xmean = %s\n", REAL'image(xmean));
fprint(RESULT, L,"ymean = %s\n", REAL'image(ymean));
fprint(RESULT, L,"zmean = %s\n", REAL'image(zmean));
fprint(RESULT, L,"xvar = %s\n", REAL'image(xvar));
fprint(RESULT, L,"yvar = %s\n", REAL'image(yvar));
fprint(RESULT, L,"zvar = %s\n", REAL'image(zvar));
fprint(RESULT, L,"xstd = %s\n", REAL'image(xstd));
fprint(RESULT, L,"ystd = %s\n", REAL'image(ystd));
fprint(RESULT, L,"zstd = %s\n", REAL'image(zstd));
fprint(RESULT, L,"------------------------------------------\n");
assert false report "Test finished" severity error;
wait;
END PROCESS;
END;
lib/radio/cordic/src/tb_cordic_top.vhd
+645
View File
@@ -0,0 +1,645 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:16:42 10/02/2005
-- Design Name: cordic_top
-- Module Name: tb_cordic_top.vhd
-- Project Name: cordic
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: cordic_top
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
-- Results:In 16i2 and Out 16i0
------------------------------
-- xmean = -3.051757808671257e-7
-- ymean = 1.525878906192144e-6
-- zmean = 0.0
-- xvar = 7.723598281502283e-10
-- yvar = 8.539443970667266e-10
-- zvar = 0.0
-- xstd = 2.779136247380161e-5
-- ystd = 2.922232703031582e-5
-- zstd = 0.0
--
------------------------------
-- Results:In 16i2 and Out 16i1
------------------------------
-- xmean = 6.103515628828741e-7
-- ymean = -1.220703125057855e-6
-- zmean = 0.0
-- xvar = 9.76293486677989e-10
-- yvar = 7.934037490259732e-10
-- zvar = 0.0
-- xstd = 3.124569549038697e-5
-- ystd = 2.816742354256017e-5
-- zstd = 0.0
--
------------------------------
-- Results:In 16i2 and Out 16i2
------------------------------
-- xmean = 2.441406250382875e-6
-- ymean = -1.220703125057855e-6
-- zmean = 0.0
-- xvar = 2.126680036682826e-9
-- yvar = 2.117107754473399e-9
-- zvar = 0.0
-- xstd = 4.611594124251206e-5
-- ystd = 4.601203923402438e-5
-- zstd = 0.0
--
------------------------------
-- Results:In 32i2 and Out 32i0
------------------------------
-- xmean = -9.312842871812748e-12
-- ymean = -5.78558739545293e-17
-- zmean = 0.0
-- xvar = 1.671709854744817e-19
-- yvar = 1.790442305004033e-19
-- zvar = 0.0
-- xstd = 4.088654857951228e-10
-- ystd = 4.231361843430591e-10
-- zstd = 0.0
--
------------------------------
-- Results:In 32i2 and Out 32i1
------------------------------
-- xmean = 9.313608620496825e-12
-- ymean = 9.31316789028083e-12
-- zmean = 0.0
-- xvar = 1.876480788588237e-19
-- yvar = 2.238344116260579e-19
-- zvar = 0.0
-- xstd = 4.331836548841885e-10
-- ystd = 4.731114156581492e-10
-- zstd = 0.0
--
------------------------------
-- Results:In 32i2 and Out 32i2
------------------------------
-- xmean = -3.72525201102771e-11
-- ymean = -5.78558739545293e-17
-- zmean = 0.0
-- xvar = 5.458335981037092e-19
-- yvar = 5.704280631341228e-19
-- zvar = 0.0
-- xstd = 7.388055211648797e-10
-- ystd = 7.552668820583376e-10
-- zstd = 0.0
--
------------------------------
-- Results:In 64i2 and Out 64i0
------------------------------
-- xmean = 3.45418680637588e-17
-- ymean = 3.859475130978118e-17
-- zmean = 2.205267218835516e-16
-- xvar = 5.54111959258452e-28
-- yvar = 5.549496221074054e-28
-- zvar = 7.916891206490056e-29
-- xstd = 2.353958281827551e-14
-- ystd = 2.355736874329146e-14
-- zstd = 8.897691389619023e-15
--
------------------------------
-- Results:In 64i2 and Out 64i1
------------------------------
-- xmean = 3.45418680637588e-17
-- ymean = 3.859475130978118e-17
-- zmean = 2.205267218835516e-16
-- xvar = 5.541120861185077e-28
-- yvar = 5.549497432144743e-28
-- zvar = 7.916856202525234e-29
-- xstd = 2.353958551288674e-14
-- ystd = 2.355737131376237e-14
-- zstd = 8.897671719346156e-15
--
------------------------------
-- Results:In 64i2 and Out 64i2
------------------------------
-- xmean = 3.343164503913365e-17
-- ymean = 3.859475130978118e-17
-- zmean = 2.205223850748616e-16
-- xvar = 5.540559656182732e-28
-- yvar = 5.549495010008071e-28
-- zvar = 7.916821581863743e-29
-- xstd = 2.353839343749427e-14
-- ystd = 2.355736617283025e-14
-- zstd = 8.897652264425568e-15
--
--------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
USE ieee.numeric_std.ALL;
use std.textio.all; -- Imports the standard textio package.
library work;
use work.fixed_pkg.all;
use work.cordic_pkg.all;
use work.PCK_FIO.all;
ENTITY tb_cordic_top IS
Generic (
nbits : integer := 32;
nbits_frac : integer := 30;
nbits_out : integer := 32;
nbits_frac_out : integer := 31
);
END tb_cordic_top;
ARCHITECTURE behavior OF tb_cordic_top IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT cordic_top
GENERIC (
nbits : integer;
nbits_frac : integer;
nbits_out : integer;
nbits_frac_out : integer
);
PORT(
rst : IN std_logic;
clk : IN std_logic;
ce : in std_logic;
xin : IN sfixed;
yin : IN sfixed;
zin : IN sfixed;
xout : OUT sfixed;
yout : OUT sfixed;
zout : OUT sfixed;
ready : OUT std_logic;
valid : out std_logic;
cordic_mode : in cordic_mode_t
);
END COMPONENT;
--Constants
constant num_cycles : integer := 5;
constant num_steps_per_cycle : integer := 100;
constant PERIOD : time := 10 ns;
constant one_sfix : sfixed := to_sfixed(1.0, sproto(nbits, nbits_frac)'high, sproto(nbits, nbits_frac)'low);
constant zero_sfix : sfixed := to_sfixed(0.0, sproto(nbits, nbits_frac)'high, sproto(nbits, nbits_frac)'low);
--Inputs
SIGNAL clk : std_logic := '0';
SIGNAL rst : std_logic := '1';
SIGNAL ce : std_logic := '0';
SIGNAL xin, yin, zin : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low) := zero_sfix;
--Outputs
SIGNAL xout, yout, zout : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
SIGNAL valid, ready : std_logic;
SIGNAL cordic_mode : cordic_mode_t := cordic_mode_vector;
--------------------------------------------------------------------
--Functions
--------------------------------------------------------------------
type real_vector_t is array (natural range <>) of real;
function mean(x : real_vector_t; len : integer) return real is
variable xm : real := 0.0;
begin
for i in 0 to len-1 loop
xm := xm + x(i);
end loop;
return xm / real(len);
end mean;
--------------------------------------------------------------------
function var(x : real_vector_t; len : integer) return real is
variable xv, xm, xp : real := 0.0;
begin
xm := mean(x, len);
for i in 0 to len-1 loop
xp := x(i) - xm;
xv := xv + xp*xp;
end loop;
return xv / real(len);
end var;
--------------------------------------------------------------------
function stddev(x : real_vector_t; len : integer) return real is
variable xv, xs : real := 0.0;
begin
xv := var(x, len);
if xv > 0.0 then
xs := sqrt(xv);
end if;
return xs;
end stddev;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: cordic_top
GENERIC MAP (
nbits => nbits,
nbits_frac => nbits_frac,
nbits_out => nbits_out,
nbits_frac_out => nbits_frac_out
)
PORT MAP(
rst => rst,
clk => clk,
ce => ce,
xin => xin,
yin => yin,
zin => zin,
xout => xout,
yout => yout,
zout => zout,
ready => ready,
valid => valid,
cordic_mode => cordic_mode
);
tb_clk : PROCESS
BEGIN
clk <= not clk;
wait for PERIOD/2;
END PROCESS;
tb : PROCESS
variable xerr, yerr, zerr : real_vector_t (0 to num_steps_per_cycle*num_cycles-1);
variable xvar, xstd, xmean, yvar, ystd, ymean, zvar, zstd, zmean : real;
variable argx, argy, argz : real := 0.0;
variable phi, dphi : real := 0.0;
file RESULT: text open write_mode is "STD_OUTPUT";
file RESULT_X: text open write_mode is "x.txt";
file RESULT_Y: text open write_mode is "y.txt";
file RESULT_Z: text open write_mode is "z.txt";
variable L: line;
variable j : integer := 0;
BEGIN
-- Wait 100 ns for global reset to finish
wait for 4*PERIOD;
rst <= '0';
wait for 2*PERIOD;
for i in 0 to arctan_tbl'length-1 loop
fprint(RESULT, L,"coeff arctan (%d) = %s\n", fo(i), REAL'image(arctan_tbl(i)));
end loop;
for i in 0 to gain_tbl'length-1 loop
fprint(RESULT, L,"coeff gain (%d) = %s\n", fo(i), REAL'image(gain_tbl(i)));
end loop;
fprint(RESULT, L,"Pi = %s\n", REAL'image(MATH_PI));
fprint(RESULT, L,"sqrt(2) = %s\n", REAL'image(SQRT(2.0)));
fprint(RESULT, L,"1/sqrt(2) = %s\n", REAL'image(1.0/SQRT(2.0)));
-------------------------------------------
-- 1
wait until rising_edge(clk) and ready = '1';
cordic_mode <= cordic_mode_rotate;
argx := 1.0;
argy := 0.0;
argz := -pi/4.0;
xin <= to_sfixed(argx, xin);
yin <= to_sfixed(argy, yin);
zin <= to_sfixed(argz, zin);
ce <= '1';
wait until rising_edge(clk);
ce <= '0';
wait until rising_edge(clk) and ready = '0';
wait until rising_edge(clk) and valid = '1';
fprint(RESULT, L,"--------------------------------\n");
fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode));
fprint(RESULT, L,"Xn = An*[X0*cos(Z0) - Y0*sin(Z0)]\n");
fprint(RESULT, L,"Yn = An*[Y0*cos(Z0) + X0*sin(Z0)]\n");
fprint(RESULT, L,"\n");
fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
fprint(RESULT, L,"\n");
fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
fprint(RESULT, L,"\n");
-------------------------------------------
-- 2
wait until rising_edge(clk) and ready = '1';
cordic_mode <= cordic_mode_rotate;
argx := 1.0;
argy := 0.0;
argz := pi/2.0;
xin <= to_sfixed(argx, xin);
yin <= to_sfixed(argy, yin);
zin <= to_sfixed(argz, zin);
ce <= '1';
wait until rising_edge(clk);
ce <= '0';
wait until rising_edge(clk) and ready = '0';
wait until rising_edge(clk) and valid = '1';
fprint(RESULT, L,"--------------------------------\n");
fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode));
fprint(RESULT, L,"Xn = An*[X0*cos(Z0) - Y0*sin(Z0)]\n");
fprint(RESULT, L,"Yn = An*[Y0*cos(Z0) + X0*sin(Z0)]\n");
fprint(RESULT, L,"\n");
fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
fprint(RESULT, L,"\n");
fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
fprint(RESULT, L,"\n");
-------------------------------------------
-- 3
wait until rising_edge(clk) and ready = '1';
cordic_mode <= cordic_mode_rotate;
argx := sqrt2_inv;
argy := -sqrt2_inv;
argz := pi/2.0;
xin <= to_sfixed(argx, xin);
yin <= to_sfixed(argy, yin);
zin <= to_sfixed(argz, zin);
ce <= '1';
wait until rising_edge(clk);
ce <= '0';
wait until rising_edge(clk) and ready = '0';
wait until rising_edge(clk) and valid = '1';
fprint(RESULT, L,"--------------------------------\n");
fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode));
fprint(RESULT, L,"Xn = An*[X0*cos(Z0) - Y0*sin(Z0)]\n");
fprint(RESULT, L,"Yn = An*[Y0*cos(Z0) + X0*sin(Z0)]\n");
fprint(RESULT, L,"\n");
fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
fprint(RESULT, L,"\n");
fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
fprint(RESULT, L,"\n");
-------------------------------------------
-- 4
wait until rising_edge(clk) and ready = '1';
cordic_mode <= cordic_mode_rotate;
argx := sqrt2_inv;
argy := -sqrt2_inv;
argz := -pi/4.0;
xin <= to_sfixed(argx, xin);
yin <= to_sfixed(argy, yin);
zin <= to_sfixed(argz, zin);
ce <= '1';
wait until rising_edge(clk);
ce <= '0';
wait until rising_edge(clk) and ready = '0';
wait until rising_edge(clk) and valid = '1';
fprint(RESULT, L,"--------------------------------\n");
fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode));
fprint(RESULT, L,"Xn = An*[X0*cos(Z0) - Y0*sin(Z0)]\n");
fprint(RESULT, L,"Yn = An*[Y0*cos(Z0) + X0*sin(Z0)]\n");
fprint(RESULT, L,"\n");
fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
fprint(RESULT, L,"\n");
fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
fprint(RESULT, L,"\n");
-------------------------------------------
-- 5
wait until rising_edge(clk) and ready = '1';
cordic_mode <= cordic_mode_vector;
argx := 1.0;
argy := 1.0;
argz := 0.0;
xin <= to_sfixed(argx, xin);
yin <= to_sfixed(argy, yin);
zin <= to_sfixed(argz, zin);
ce <= '1';
wait until rising_edge(clk);
ce <= '0';
wait until rising_edge(clk) and ready = '0';
wait until rising_edge(clk) and valid = '1';
fprint(RESULT, L,"--------------------------------\n");
fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode));
fprint(RESULT, L,"Xn = An*sqrt(X0^2 + Y0^2)\n");
fprint(RESULT, L,"Zn = Z0 + arctan(Y0/X0)\n");
fprint(RESULT, L,"\n");
fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
fprint(RESULT, L,"\n");
fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
fprint(RESULT, L,"\n");
-------------------------------------------
-- 6
wait until rising_edge(clk) and ready = '1';
cordic_mode <= cordic_mode_vector;
argx := sqrt2_inv;
argy := -sqrt2_inv;
argz := 0.0;
xin <= to_sfixed(argx, xin);
yin <= to_sfixed(argy, yin);
zin <= to_sfixed(argz, zin);
ce <= '1';
wait until rising_edge(clk);
ce <= '0';
wait until rising_edge(clk) and ready = '0';
wait until rising_edge(clk) and valid = '1';
fprint(RESULT, L,"--------------------------------\n");
fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode));
fprint(RESULT, L,"Xn = An*sqrt(X0^2 + Y0^2)\n");
fprint(RESULT, L,"Zn = Z0 + arctan(Y0/X0)\n");
fprint(RESULT, L,"\n");
fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
fprint(RESULT, L,"\n");
fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
fprint(RESULT, L,"\n");
-------------------------------------------
-- 7
wait until rising_edge(clk) and ready = '1';
cordic_mode <= cordic_mode_vector;
argx := -sqrt2_inv;
argy := sqrt2_inv;
argz := 0.0;
xin <= to_sfixed(argx, xin);
yin <= to_sfixed(argy, yin);
zin <= to_sfixed(argz, zin);
ce <= '1';
wait until rising_edge(clk);
ce <= '0';
wait until rising_edge(clk) and ready = '0';
wait until rising_edge(clk) and valid = '1';
fprint(RESULT, L,"--------------------------------\n");
fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode));
fprint(RESULT, L,"Xn = An*sqrt(X0^2 + Y0^2)\n");
fprint(RESULT, L,"Zn = Z0 + arctan(Y0/X0)\n");
fprint(RESULT, L,"\n");
fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
fprint(RESULT, L,"\n");
fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
fprint(RESULT, L,"\n");
-------------------------------------------
-- 8
wait until rising_edge(clk) and ready = '1';
cordic_mode <= cordic_mode_vector;
argx := -sqrt2_inv;
argy := -sqrt2_inv;
argz := 0.0;
xin <= to_sfixed(argx, xin);
yin <= to_sfixed(argy, yin);
zin <= to_sfixed(argz, zin);
ce <= '1';
wait until rising_edge(clk);
ce <= '0';
wait until rising_edge(clk) and ready = '0';
wait until rising_edge(clk) and valid = '1';
fprint(RESULT, L,"--------------------------------\n");
fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode));
fprint(RESULT, L,"Xn = An*sqrt(X0^2 + Y0^2)\n");
fprint(RESULT, L,"Zn = Z0 + arctan(Y0/X0)\n");
fprint(RESULT, L,"\n");
fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
fprint(RESULT, L,"\n");
fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
fprint(RESULT, L,"\n");
-------------------------------------------
-- Place stimulus here
wait for 10*PERIOD;
j := 0;
cordic_mode <= cordic_mode_rotate;
dphi := 2.0*pi/real(num_steps_per_cycle);
for k in 0 to num_cycles-1 loop
phi := -pi;
for i in 0 to num_steps_per_cycle-1 loop
xin <= one_sfix;
yin <= zero_sfix;
zin <= to_sfixed(phi, zin, false, true);
wait until rising_edge(clk) and ready = '1';
ce <= '1';
wait until rising_edge(clk);
ce <= '0';
wait until rising_edge(clk) and ready = '0';
wait until rising_edge(clk) and valid = '1';
fprint(RESULT_X, L,"%s\n", REAL'image(to_real(xout)));
fprint(RESULT_Y, L,"%s\n", REAL'image(to_real(yout)));
fprint(RESULT_Z, L,"%s\n", REAL'image(to_real(zout)));
-- fprint(RESULT_X, L,"%s\n", REAL'image(cos(phi)));
-- fprint(RESULT_Y, L,"%s\n", REAL'image(sin(phi)));
-- fprint(RESULT_Z, L,"%s\n", REAL'image(0.0));
xerr(j) := to_real(xout) - cos(phi);
yerr(j) := to_real(yout) - sin(phi);
zerr(j) := to_real(zout);
j := j + 1;
phi := (phi + dphi);
end loop;
end loop;
xmean := mean(xerr, j);
ymean := mean(yerr, j);
zmean := mean(zerr, j);
xvar := var(xerr, j);
yvar := var(yerr, j);
zvar := var(zerr, j);
xstd := stddev(xerr, j);
ystd := stddev(yerr, j);
zstd := stddev(zerr, j);
fprint(RESULT, L,"------------------------------------------\n");
fprint(RESULT, L,"Results: \n");
fprint(RESULT, L,"xmean = %s\n", REAL'image(xmean));
fprint(RESULT, L,"ymean = %s\n", REAL'image(ymean));
fprint(RESULT, L,"zmean = %s\n", REAL'image(zmean));
fprint(RESULT, L,"xvar = %s\n", REAL'image(xvar));
fprint(RESULT, L,"yvar = %s\n", REAL'image(yvar));
fprint(RESULT, L,"zvar = %s\n", REAL'image(zvar));
fprint(RESULT, L,"xstd = %s\n", REAL'image(xstd));
fprint(RESULT, L,"ystd = %s\n", REAL'image(ystd));
fprint(RESULT, L,"zstd = %s\n", REAL'image(zstd));
fprint(RESULT, L,"------------------------------------------\n");
assert false report "Test finished" severity error;
wait;
END PROCESS;
END;
lib/radio/nco/sim/tb_nco_cordic.fdo
+18
View File
@@ -0,0 +1,18 @@
vlib work
vcom -explicit -93 "../../../fixed/fixed_pkg_c.vhd"
vcom -explicit -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993.vhd"
vcom -explicit -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
vcom -explicit -93 "../../cordic/src/cordic_pkg.vhd"
vcom -explicit -93 "../../cordic/src/cordic_pipe_stage.vhd"
vcom -explicit -93 "../../cordic/src/cordic_pipe_pre.vhd"
vcom -explicit -93 "../../cordic/src/cordic_pipe_post.vhd"
vcom -explicit -93 "../../cordic/src/cordic_pipe_top.vhd"
vcom -explicit -93 "../src/nco_pkg.vhd"
vcom -explicit -93 "../src/nco_cordic_dbg.vhd"
vcom -explicit -93 "../src/tb_nco_cordic.vhd"
vsim -t 1ps -lib work tb_nco
do {tb_nco_cordic.wdo}
view wave
view structure
view signals
run 250us
lib/radio/nco/sim/tb_nco_cordic.wdo
+42
View File
@@ -0,0 +1,42 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_nco/uut/srst
add wave -noupdate -format Logic /tb_nco/uut/clk
add wave -noupdate -format Logic /tb_nco/uut/pacc_clr
add wave -noupdate -format Logic /tb_nco/uut/pacc_inc
add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/freq_in
add wave -noupdate -format Logic /tb_nco/uut/freq_load
add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase_in
add wave -noupdate -format Logic /tb_nco/uut/phase_load
add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase_out
add wave -noupdate -format Analog-Step -radix decimal -scale 7.6294199999999999e-005 /tb_nco/uut/wave_out_i
add wave -noupdate -format Analog-Step -radix decimal -scale 7.6294199999999999e-005 /tb_nco/uut/wave_out_q
add wave -noupdate -format Logic /tb_nco/uut/out_valid
add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/debug_out
add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase
add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/freq_in_r
add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase_in_r
add wave -noupdate -format Literal -radix decimal /tb_nco/uut/wave_i_ud
add wave -noupdate -format Literal -radix decimal /tb_nco/uut/wave_q_ud
add wave -noupdate -format Logic /tb_nco/uut/wave_ud_valid
add wave -noupdate -divider Cordic
add wave -noupdate -format Literal -radix decimal /tb_nco/uut/zin_ud
add wave -noupdate -format Literal -radix decimal /tb_nco/uut/xin
add wave -noupdate -format Literal -radix decimal /tb_nco/uut/yin
add wave -noupdate -format Literal -radix decimal /tb_nco/uut/zout_ud
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {239431582 ps} 0}
configure wave -namecolwidth 193
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {234759392 ps} {243485961 ps}
lib/radio/nco/src/nco_cordic.vhd
+256
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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:16:14 10/02/05
-- Design Name:
-- Module Name: cordic_stage - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
USE ieee.numeric_std.ALL;
use work.fixed_pkg.all;
use work.nco_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity nco is
Generic
(
nbits_wave : integer := 18;
nbits_phase : integer := 16;
nbits_lut_depth : integer := 12;
nbits_dither : integer := 4;
nbits_lfsr : integer := 12;
q_phase : phase_relation_t := phase_90deg;
has_pipe_reg : boolean := false;
has_out_reg : boolean := false
);
Port
(
srst : in std_logic;
clk : in std_logic;
pacc_clr : in std_logic;
pacc_inc : in std_logic;
freq_in : in unsigned(nbits_phase-1 downto 0);
freq_load : in std_logic;
phase_in : in unsigned(nbits_phase-1 downto 0);
phase_load : in std_logic;
phase_out : out unsigned(nbits_phase-1 downto 0);
wave_out_i : out sfixed;
wave_out_q : out sfixed;
out_valid : out std_logic
);
end nco;
architecture Behavioral of nco is
COMPONENT cordic_pipe_top
GENERIC
(
cordic_mode : cordic_mode_t;
z_range : real;
nstages : integer;
nbits_x_in : integer;
nbits_y_in : integer;
nbits_z_in : integer;
nbits_frac_x_in : integer;
nbits_frac_y_in : integer;
nbits_frac_z_in : integer;
nbits_x_out : integer;
nbits_y_out : integer;
nbits_z_out : integer;
nbits_frac_x_out : integer;
nbits_frac_y_out : integer;
nbits_frac_z_out : integer
);
PORT
(
rst : in std_logic;
clk : in std_logic;
vld_in : in std_logic;
xin : in sfixed;
yin : in sfixed;
zin : in sfixed;
xout : out sfixed;
yout : out sfixed;
zout : out sfixed;
vld_out : out std_logic
);
END COMPONENT;
-------------------------------------------------------------------------------
constant nbits_wave_frac : integer := nbits_wave;
-------------------------------------------------------------------------------
constant lfsr_gen_poly : unsigned(nbits_lfsr-1 downto 0) := to_unsigned(lfsr_poly(nbits_lfsr), nbits_lfsr); -- 24
signal phase : unsigned(nbits_phase-1 downto 0);
signal freq_in_r : unsigned(nbits_phase-1 downto 0);
signal phase_in_r : unsigned(nbits_phase-1 downto 0);
signal lut_addr_d : unsigned(nbits_lut_depth-1 downto 0);
signal wave_i_d, wave_q_d : sfixed(shi(nbits_wave, nbits_wave_frac) downto slo(nbits_wave, nbits_wave_frac));
type lfsr_t is array (0 to 1) of unsigned(nbits_lfsr-1 downto 0);
signal lfsr : lfsr_t;
signal lfsr_out : unsigned(nbits_dither-1 downto 0);
signal lut_addr_valid, lfsr_valid, wave_d_valid : std_logic;
signal zin : sfixed(shi(nbits_lut_depth, nbits_lut_depth) downto slo(nbits_lut_depth, nbits_lut_depth));
signal xin : sfixed(shi(nbits_wave, nbits_wave_frac) downto slo(nbits_wave, nbits_wave_frac)) := to_sfixed(0.0, shi(nbits_x_in, nbits_frac_x_in), slo(nbits_x_in, nbits_frac_x_in));
signal yin :sfixed(shi(nbits_wave, nbits_wave_frac) downto slo(nbits_wave, nbits_wave_frac)) := to_sfixed(1.0, shi(nbits_y_in, nbits_frac_y_in), slo(nbits_y_in, nbits_frac_y_in));
-------------------------------------------------------------------------------
begin
wave_out_i <= wave_i_d;
wave_out_q <= wave_q_d;
out_valid <= wave_d_valid;
z_in <= to_sfixed(signed(lut_addr_d), z_in);
------------------------------------------------------------
proc_lfsr: process(srst, clk, lfsr, pacc_inc)
variable lo : unsigned(nbits_dither-1 downto 0);
begin
if rising_edge(clk) then
if srst = '1' then
lfsr_valid <= '0';
lfsr_out <= (others => '0');
for i in lfsr'range loop
lfsr(i) <= to_unsigned(2**i, nbits_lfsr);
end loop;
else
lfsr_valid <= '0';
if pacc_inc ='1' then
lfsr_valid <= '1';
lo := (others => '0');
for i in lfsr'range loop
if lfsr(i)(lfsr(i)'left) = '1' then
lfsr(i) <= (lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left)) xor lfsr_gen_poly;
else
lfsr(i) <= lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left);
end if;
end loop;
for i in lfsr'range loop
lo := lo + lfsr(i)(nbits_dither-1 downto 0);
end loop;
-- lo := lfsr(0)(nbits_dither downto 0);
lfsr_out <= lo(nbits_dither-1 downto 0);
end if;
end if;
end if;
end process;
------------------------------------------------------------
proc_phase_accu: process(clk, phase)
variable phase_accu : unsigned(nbits_phase-1 downto 0);
begin
if rising_edge(clk) then
if srst = '1' then
phase_accu := (others => '0');
else
phase <= phase_accu + phase_in_r;
if pacc_clr = '1' then
phase_accu := (others => '0');
elsif pacc_inc = '1' then
phase_accu := phase_accu + freq_in_r;
end if;
end if;
end if;
phase_out <= phase;
end process;
------------------------------------------------------------
freq_in_reg: process(srst, clk, freq_load, freq_in)
begin
if rising_edge(clk) then
if srst = '1' then
freq_in_r <= (others => '0');
elsif freq_load = '1' then
freq_in_r <= freq_in;
end if;
end if;
end process;
------------------------------------------------------------
phase_in_reg: process(srst, clk, phase_load, phase_in)
begin
if rising_edge(clk) then
if srst = '1' then
phase_in_r <= (others => '0');
elsif phase_load = '1' then
phase_in_r <= phase_in;
end if;
end if;
end process;
------------------------------------------------------------
proc_pipe_reg: process(clk)
variable lfsr_sum : unsigned(nbits_phase-1 downto 0);
begin
if rising_edge(clk) then
lut_addr_valid <= '0';
if srst = '1' then
lfsr_sum := (others => '0');
elsif lfsr_valid = '1' then
lut_addr_valid <= '1';
lfsr_sum := lfsr_out + phase;
end if;
end if;
lut_addr_d <= lfsr_sum(nbits_phase-1 downto nbits_phase-nbits_lut_depth);
end process;
------------------------------------------------------------
inst_cordic: cordic_pipe_top
GENERIC MAP
(
cordic_mode => cordic_mode_rotate,
z_range => 1.0,
nstages => 18,
nbits_x_in => nbits_wave,
nbits_frac_x_in => nbits_wave_frac,
nbits_y_in => nbits_wave,
nbits_frac_y_in => nbits_wave_frac,
nbits_z_in => nbits_lut_depth,
nbits_frac_z_in => nbits_lut_depth-2,
nbits_x_out => nbits_wave,
nbits_frac_x_out => nbits_wave_frac,
nbits_y_out => nbits_wave,
nbits_frac_y_out => nbits_wave_frac,
nbits_z_out => nbits_lut_depth,
nbits_frac_z_out => nbits_lut_depth-2
)
PORT MAP
(
rst => srst,
clk => clk,
vld_in => lut_addr_valid,
xin => xin,
yin => yin,
zin => zin,
xout => wave_i_d,
yout => wave_q_d,
zout => open,
vld_out => wave_d_valid
);
------------------------------------------------------------
end Behavioral;
lib/radio/nco/src/nco_cordic_dbg.vhd
+209
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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:16:14 10/02/05
-- Design Name:
-- Module Name: cordic_stage - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
USE ieee.numeric_std.ALL;
use work.fixed_pkg.all;
use work.cordic_pkg.all;
use work.nco_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity nco is
Generic
(
nbits_wave : integer := 18;
nbits_phase : integer := 16
);
Port
(
srst : in std_logic;
clk : in std_logic;
pacc_clr : in std_logic;
pacc_inc : in std_logic;
freq_in : in unsigned(nbits_phase-1 downto 0);
freq_load : in std_logic;
phase_in : in unsigned(nbits_phase-1 downto 0);
phase_load : in std_logic;
phase_out : out unsigned(nbits_phase-1 downto 0);
wave_out_i : out sfixed;
wave_out_q : out sfixed;
out_valid : out std_logic;
debug_out : out debug_out_t
);
end nco;
architecture Behavioral of nco is
COMPONENT cordic_pipe_top
GENERIC
(
cordic_mode : cordic_mode_t;
z_range : real;
gain_corr_mode : gain_corr_mode_t;
nstages : integer;
nbits_x_in : integer;
nbits_y_in : integer;
nbits_z_in : integer;
nbits_frac_x_in : integer;
nbits_frac_y_in : integer;
nbits_frac_z_in : integer;
nbits_x_out : integer;
nbits_y_out : integer;
nbits_z_out : integer;
nbits_frac_x_out : integer;
nbits_frac_y_out : integer;
nbits_frac_z_out : integer
);
PORT
(
rst : in std_logic;
clk : in std_logic;
vld_in : in std_logic;
xin : in sfixed;
yin : in sfixed;
zin : in sfixed;
xout : out sfixed;
yout : out sfixed;
zout : out sfixed;
vld_out : out std_logic
);
END COMPONENT;
-------------------------------------------------------------------------------
constant nbits_wave_frac : integer := nbits_wave-1;
constant nbits_phase_frac : integer := nbits_phase;
-------------------------------------------------------------------------------
signal phase : signed(nbits_phase-1 downto 0);
signal freq_in_r : signed(nbits_phase-1 downto 0);
signal phase_in_r : signed(nbits_phase-1 downto 0);
signal wave_i_ud, wave_q_ud : sfixed(shi(nbits_wave, nbits_wave_frac) downto slo(nbits_wave, nbits_wave_frac));
signal wave_ud_valid, phase_vld : std_logic;
signal zin_ud : sfixed(shi(nbits_phase, nbits_phase_frac) downto slo(nbits_phase, nbits_phase_frac));
signal xin : sfixed(shi(nbits_wave, nbits_wave_frac) downto slo(nbits_wave, nbits_wave_frac)) := to_sfixed(0.0, shi(nbits_wave, nbits_wave_frac), slo(nbits_wave, nbits_wave_frac));
signal yin :sfixed(shi(nbits_wave, nbits_wave_frac) downto slo(nbits_wave, nbits_wave_frac)) := to_sfixed(1.0, shi(nbits_wave, nbits_wave_frac), slo(nbits_wave, nbits_wave_frac));
signal zout_ud : sfixed(shi(nbits_phase, nbits_phase_frac) downto slo(nbits_phase, nbits_phase_frac));
-------------------------------------------------------------------------------
begin
wave_out_i <= wave_i_ud;
wave_out_q <= wave_q_ud;
out_valid <= wave_ud_valid;
debug_out.lfsr <= (others => '0');
debug_out.i_d <= 0.0;
debug_out.q_d <= 0.0;
debug_out.i_ud <= to_real(wave_i_ud);
debug_out.q_ud <= to_real(wave_q_ud);
------------------------------------------------------------
proc_phase_accu: process(srst, clk, pacc_clr, pacc_inc, freq_in_r, phase_in_r)
variable phase_accu : signed(nbits_phase-1 downto 0);
begin
if rising_edge(clk) then
phase_vld <= '0';
if srst = '1' then
phase_accu := (others => '0');
else
phase_vld <= '1';
phase <= phase_accu + phase_in_r;
if pacc_clr = '1' then
phase_accu := (others => '0');
elsif pacc_inc = '1' then
phase_accu := phase_accu + freq_in_r;
end if;
end if;
end if;
phase_out <= unsigned(phase);
zin_ud <= sfixed(phase);
end process;
------------------------------------------------------------
freq_in_reg: process(srst, clk, freq_load, freq_in)
begin
if rising_edge(clk) then
if srst = '1' then
freq_in_r <= (others => '0');
elsif freq_load = '1' then
freq_in_r <= signed(freq_in);
end if;
end if;
end process;
------------------------------------------------------------
phase_in_reg: process(srst, clk, phase_load, phase_in)
begin
if rising_edge(clk) then
if srst = '1' then
phase_in_r <= (others => '0');
elsif phase_load = '1' then
phase_in_r <= signed(phase_in);
end if;
end if;
end process;
------------------------------------------------------------
inst_cordic_ud: cordic_pipe_top
GENERIC MAP
(
cordic_mode => cordic_mode_rotate,
z_range => 1.0,
gain_corr_mode => gain_mode_disabled,
nstages => nbits_phase,
nbits_x_in => nbits_wave,
nbits_frac_x_in => nbits_wave_frac,
nbits_y_in => nbits_wave,
nbits_frac_y_in => nbits_wave_frac,
nbits_z_in => nbits_phase,
nbits_frac_z_in => nbits_phase_frac,
nbits_x_out => nbits_wave,
nbits_frac_x_out => nbits_wave_frac,
nbits_y_out => nbits_wave,
nbits_frac_y_out => nbits_wave_frac,
nbits_z_out => nbits_phase,
nbits_frac_z_out => nbits_phase_frac
)
PORT MAP
(
rst => srst,
clk => clk,
vld_in => phase_vld,
xin => xin,
yin => yin,
zin => zin_ud,
xout => wave_i_ud,
yout => wave_q_ud,
zout => zout_ud,
vld_out => wave_ud_valid
);
------------------------------------------------------------
end Behavioral;
lib/radio/nco/src/tb_nco_cordic.vhd
+281
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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:16:42 13.05.2007
-- Design Name: tb_nco
-- Module Name: tb_nco.vhd
-- Project Name: nco
-- Target Device:
-- Tool versions:
-- Description:
--
--------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
USE ieee.numeric_std.ALL;
use std.textio.all; -- Imports the standard textio package.
library work;
use work.fixed_pkg.all;
use work.nco_pkg.all;
use work.PCK_FIO.all;
ENTITY tb_nco IS
Generic
(
nbits_wave : integer := 16;
nbits_phase : integer := 20
);
END tb_nco;
ARCHITECTURE behavior OF tb_nco IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT nco
GENERIC
(
nbits_wave : integer;
nbits_phase : integer
);
PORT(
srst : in std_logic;
clk : in std_logic;
pacc_clr : in std_logic;
pacc_inc : in std_logic;
freq_in : in unsigned(nbits_phase-1 downto 0);
freq_load : in std_logic;
phase_in : in unsigned(nbits_phase-1 downto 0);
phase_load : in std_logic;
phase_out : out unsigned(nbits_phase-1 downto 0);
wave_out_i : out sfixed;
wave_out_q : out sfixed;
out_valid : out std_logic;
debug_out : out debug_out_t
);
END COMPONENT;
--Constants
constant f : REAL := 15.0E6;
constant df : REAL := 10.0E3;
constant fa : REAL := 100.0E6;
constant PERIOD : time := 10 ns;
constant nbits_wave_frac : integer := nbits_wave;
SIGNAL freq_word : integer := integer(f/fa*2.0**nbits_phase);
SIGNAL dfreq_word : integer := integer(df/fa*2.0**nbits_phase);
--Inputs
SIGNAL clk : std_logic := '0';
SIGNAL srst : std_logic := '1';
SIGNAL pacc_clr : std_logic := '0';
SIGNAL pacc_inc : std_logic := '0';
SIGNAL phase_load : std_logic := '0';
SIGNAL freq_load : std_logic := '0';
SIGNAL freq_in : unsigned(nbits_phase-1 downto 0);
SIGNAL phase_in : unsigned(nbits_phase-1 downto 0);
--Outputs
SIGNAL wave_out_i : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
SIGNAL wave_out_q : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
SIGNAL out_valid : std_logic;
SIGNAL phase_out : unsigned(nbits_phase-1 downto 0);
SIGNAL debug_out : debug_out_t;
SIGNAL fileout_enable : std_logic := '0';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: nco
GENERIC MAP
(
nbits_wave => nbits_wave,
nbits_phase => nbits_phase
)
PORT MAP
(
srst => srst,
clk => clk,
pacc_clr => pacc_clr,
pacc_inc => pacc_inc,
freq_in => freq_in,
freq_load => freq_load,
phase_in => phase_in,
phase_load => phase_load,
phase_out => phase_out,
wave_out_i => wave_out_i,
wave_out_q => wave_out_q,
out_valid => out_valid,
debug_out => debug_out
);
tb_clk : PROCESS
BEGIN
clk <= not clk;
wait for PERIOD/2;
END PROCESS;
tb : PROCESS
file RESULT_FREQ: text open write_mode is "freq.txt";
variable L: line;
BEGIN
-- Wait 100 ns for global reset to finish
wait for 4*PERIOD;
srst <= '0';
fprint(RESULT_FREQ, L,"%s\n", REAL'image(f));
wait for 2*PERIOD;
-------------------------------------------
-- 1
phase_in <= to_unsigned(0,nbits_phase);
wait until rising_edge(clk);
phase_load <= '1';
wait until rising_edge(clk);
phase_load <= '0';
freq_in <= to_unsigned(1411,nbits_phase);
wait until rising_edge(clk);
freq_load <= '1';
wait until rising_edge(clk);
freq_load <= '0';
wait for 2*PERIOD;
pacc_inc <= '1';
wait for 2*PERIOD;
wait until rising_edge(clk);
wait for 40*PERIOD;
-------------------------------------------
freq_in <= to_unsigned(643,nbits_phase);
wait until rising_edge(clk);
freq_load <= '1';
wait until rising_edge(clk);
freq_load <= '0';
wait for 40*PERIOD;
-------------------------------------------
phase_in <= to_unsigned(800,nbits_phase);
wait until rising_edge(clk);
phase_load <= '1';
wait until rising_edge(clk);
phase_load <= '0';
wait for 20*PERIOD;
-------------------------------------------
phase_in <= to_unsigned(45072,nbits_phase);
wait until rising_edge(clk);
phase_load <= '1';
wait until rising_edge(clk);
phase_load <= '0';
wait for 20*PERIOD;
-------------------------------------------
phase_in <= to_unsigned(20593,nbits_phase);
wait until rising_edge(clk);
phase_load <= '1';
wait until rising_edge(clk);
phase_load <= '0';
-------------------------------------------
freq_in <= to_unsigned(freq_word,nbits_phase);
wait until rising_edge(clk);
freq_load <= '1';
wait until rising_edge(clk);
freq_load <= '0';
wait for 20*PERIOD;
fileout_enable <= '1';
wait for 20000*PERIOD;
fileout_enable <= '0';
-------------------------------------------
-- Sweep
freq_word <= 100;
for i in 1 to 200 loop
wait for 20*PERIOD;
freq_word <= freq_word + dfreq_word;
freq_in <= to_unsigned(freq_word,nbits_phase);
wait until rising_edge(clk);
freq_load <= '1';
wait until rising_edge(clk);
freq_load <= '0';
end loop;
pacc_inc <= '0';
wait for 20*PERIOD;
fileout_enable <= '0';
wait until rising_edge(clk);
pacc_clr <= '1';
wait until rising_edge(clk);
pacc_clr <= '0';
wait for 20*PERIOD;
pacc_inc <= '1';
wait for 20*PERIOD;
wait until rising_edge(clk);
pacc_clr <= '1';
wait until rising_edge(clk);
pacc_clr <= '0';
wait for 20*PERIOD;
pacc_inc <= '0';
wait for 20*PERIOD;
wait until rising_edge(clk);
pacc_inc <= '1';
wait until rising_edge(clk);
pacc_inc <= '0';
wait for 20*PERIOD;
wait until rising_edge(clk);
srst <= '1';
wait until rising_edge(clk);
srst <= '0';
freq_in <= to_unsigned(freq_word,nbits_phase);
wait until rising_edge(clk);
freq_load <= '1';
wait until rising_edge(clk);
freq_load <= '0';
wait for 20*PERIOD;
pacc_inc <= '1';
wait for 20*PERIOD;
wait until rising_edge(clk);
srst <= '1';
wait until rising_edge(clk);
srst <= '0';
wait for 20*PERIOD;
pacc_inc <= '0';
wait for 20*PERIOD;
assert false report "Test finished" severity error;
wait;
END PROCESS;
tb_fo : PROCESS(clk, fileout_enable, out_valid)
file RESULT_I: text open write_mode is "i_ud.txt";
file RESULT_Q: text open write_mode is "q_ud.txt";
file RESULT_ID: text open write_mode is "i_d.txt";
file RESULT_QD: text open write_mode is "q_d.txt";
file RESULT_LFSR: text open write_mode is "lfsr.txt";
variable L: line;
BEGIN
if rising_edge(clk) and fileout_enable = '1' and out_valid = '1' then
fprint(RESULT_I, L,"%s\n", REAL'image(debug_out.i_ud));
fprint(RESULT_Q, L,"%s\n", REAL'image(debug_out.q_ud));
fprint(RESULT_ID, L,"%s\n", REAL'image(debug_out.i_d));
fprint(RESULT_QD, L,"%s\n", REAL'image(debug_out.q_d));
fprint(RESULT_LFSR, L,"%s\n", INTEGER'image(to_integer(debug_out.lfsr)));
end if;
END PROCESS;
END;