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- more realistic timing of J-Bus Master

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git-svn-id: http://moon:8086/svn/vhdl/trunk@843 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-03-28 22:32:27 +00:00
parent 67136eeedf
commit 4f1f4ca77b
1 changed files with 77 additions and 29 deletions
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lib/emac/src/tb_emac_top_jb.vhd
+77 -29
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@@ -32,7 +32,7 @@ END tb_emac_top_jb;
ARCHITECTURE behavior OF tb_emac_top_jb IS
constant CLK_PERIOD : time := 10 ns;
constant MII_CLK_PERIOD : time := 8 ns;
constant MII_CLK_PERIOD : time := 40 ns;
signal CLK : std_logic := '1';
signal RST : std_logic := '1';
@@ -78,7 +78,7 @@ ARCHITECTURE behavior OF tb_emac_top_jb IS
signal dat_o_cnt : natural;
signal pkt_count : natural;
type emac_action_t is (emac_idle, emac_alloc, emac_wait_alloc, emac_write, emac_wait_data, emac_read, emac_free);
type emac_action_t is (emac_idle, emac_alloc, emac_write, emac_commit, emac_wait_data, emac_read, emac_free);
signal emac_action : emac_action_t;
BEGIN
@@ -124,9 +124,9 @@ inst_pkt_gen : entity work.pkt_gen
(
f_sysclk => 100.0,
PKT_DLY_MIN => 1.0E-6,
PKT_DLY_MAX => 10.0E-6,
PKT_DLY_MAX => 5.0E-6,
PKT_SIZE_MIN => 64,
PKT_SIZE_MAX => 512
PKT_SIZE_MAX => 1512
)
PORT MAP
@@ -200,41 +200,62 @@ STIMULUS: process
STB_I <= '1';
WE_I <= '1';
ADDR_I <= X"0000_0004";
wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '0';
-- set alloc request
check_alloc_ok:
while(true) loop
-- set alloc request
wait until rising_edge(CLK) and SRDY_O = '1';
DAT_I <= X"0200_0000";
STB_I <= '1';
WE_I <= '1';
ADDR_I <= X"0000_0000";
check_bsy:
while (true) loop
wait until rising_edge(CLK) and SRDY_O = '1';
WE_I <= '0';
STB_I <= '1';
ADDR_I <= X"0000_0000";
wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '0';
wait until rising_edge(CLK) and ACK_O = '1';
wait until rising_edge(CLK);
if DAT_O_reg(25) = '0' then
exit check_bsy;
end if;
end loop;
if DAT_O_reg(24) = '1' then
exit check_alloc_ok;
end if;
end loop;
CYC_I <= '0';
emac_action <= emac_idle;
end procedure emac_alloc;
procedure emac_commit is
begin
-- RX- DEALLOCATION
emac_action <= emac_commit;
-- set free request
CYC_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1';
DAT_I <= X"0200_0000";
DAT_I <= X"0100_0000";
STB_I <= '1';
WE_I <= '1';
ADDR_I <= X"0000_0000";
wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '0';
WE_I <= '0';
-- check alloc busy
emac_action <= emac_wait_alloc;
check_bsy:
while (true) loop
CYC_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '1';
ADDR_I <= X"0000_0000";
wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '0';
wait until rising_edge(CLK) and ACK_O = '1';
wait until rising_edge(CLK);
if DAT_O_reg(25) = '0' then
exit check_bsy;
end if;
end loop;
emac_action <= emac_idle;
end procedure emac_alloc;
end procedure emac_commit;
procedure emac_write (size : natural) is
variable data : unsigned (7 downto 0);
variable num_words : natural;
@@ -268,6 +289,9 @@ STIMULUS: process
STB_I <= '0';
wait until rising_edge(CLK) and SRDY_O = '1';
emac_commit;
emac_action <= emac_idle;
end procedure emac_write;
@@ -377,6 +401,30 @@ STIMULUS: process
RST <= '0';
wait for 60*CLK_PERIOD;
emac_alloc (1004);
emac_alloc (1004);
emac_alloc (1004);
emac_alloc (1004);
emac_alloc (1004);
emac_alloc (1004);
emac_alloc (1004);
emac_alloc (1004);
emac_alloc (1004);
emac_alloc (1004);
emac_alloc (1004);
emac_alloc (1004);
for i in 1 to 10 loop
for j in 1 to 500 loop
emac_alloc (72);
emac_write (72);
end loop;
wait for 2 ms;
end loop;
wait until rising_edge(mii_tx_clk) and mii_tx_en = '0';
wait for 6000*CLK_PERIOD;
loop_back_en <= '1';
emac_alloc (72);
@@ -480,8 +528,8 @@ STIMULUS: process
loop_back_en <= '0';
pktgen_rst <= '0';
pkt_count <= 0;
for i in 1 to 100 loop
wait for 100000*CLK_PERIOD;
for i in 1 to 500 loop
wait for 7 us;
emac_read (0);
emac_free;
pkt_count <= pkt_count + 1;