- changed to J-Bus interface
git-svn-id: http://moon:8086/svn/vhdl/trunk@244 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -1,18 +1,35 @@
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## NOTE: Do not edit this file.
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##
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vlib work
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# Misc
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vcom -explicit -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
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# RAMS
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vcom -explicit -93 "../../../misc/dpram_2w2r.vhd"
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vcom -explicit -93 "../../../misc/dpram_1w1r.vhd"
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vcom -explicit -93 "../../../misc/dpram_1w1r_dist.vhd"
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# FIFOS
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vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
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vcom -explicit -93 "../../../FIFO/src/sync_fifo_ctrl.vhd"
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vcom -explicit -93 "../../../FIFO/src/fifo_sync_dist.vhd"
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# MIPS
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vcom -explicit -93 "../src/core/mips_types.vhd"
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vcom -explicit -93 "../src/core/mips_instr.vhd"
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vcom -explicit -93 "../src/core/mips_idecode_rom.vhd"
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vcom -explicit -93 "../src/core/mips_reg.vhd"
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vcom -explicit -93 "../src/core/mips_shifter.vhd"
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vcom -explicit -93 "../src/core/mips_alu.vhd"
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vcom -explicit -93 "../src/core/mips_muldiv.vhd"
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vcom -explicit -93 "../src/core/mips_cop.vhd"
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vcom -explicit -93 "../src/core/icache.vhd"
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vcom -explicit -93 "../src/core/dcache.vhd"
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vcom -explicit -93 "../src/core/mips_bui.vhd"
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vcom -explicit -93 "../src/core/mips_bcu.vhd"
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vcom -explicit -93 "../src/core/mips_pipeline.vhd"
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vcom -explicit -93 "../src/core/mips_top.vhd"
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vcom -explicit -93 "../asm/fibonacci.vhd"
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vcom -explicit -93 "../src/ram.vhd"
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vcom -explicit -93 "../src/tb_mips_top.vhd"
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vsim -t 1ps -lib work tb_mips_top
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do {tb_mips_top.wdo}
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@@ -1,40 +1,31 @@
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onerror {resume}
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quietly WaveActivateNextPane {} 0
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add wave -noupdate -format Logic /tb_mips_top/rst
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add wave -noupdate -format Logic /tb_mips_top/clk
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add wave -noupdate -format Logic /tb_mips_top/cpu_halt
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/irom_data
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/irom_addr
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_addr
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_din
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_dout
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add wave -noupdate -format Logic /tb_mips_top/dmem_re
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add wave -noupdate -format Logic /tb_mips_top/dmem_we
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_ram/sram
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add wave -noupdate -divider {TOP interface}
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add wave -noupdate -format Literal /tb_mips_top/debug
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add wave -noupdate -format Logic /tb_mips_top/rst_i
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add wave -noupdate -format Logic /tb_mips_top/clk_i
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add wave -noupdate -format Logic /tb_mips_top/ack_i
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add wave -noupdate -format Logic /tb_mips_top/srdy_i
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/addr_o
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dat_i
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dat_o
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add wave -noupdate -format Logic /tb_mips_top/we_o
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add wave -noupdate -format Literal /tb_mips_top/sel_o
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add wave -noupdate -format Logic /tb_mips_top/cyc_o
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add wave -noupdate -format Logic /tb_mips_top/stb_o
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add wave -noupdate -format Logic /tb_mips_top/mrdy_o
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add wave -noupdate -format Literal /tb_mips_top/int
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add wave -noupdate -divider ALU
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add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline/hdu
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add wave -noupdate -format Logic /tb_mips_top/clk
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add wave -noupdate -divider PC
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/pc
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add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/exception
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add wave -noupdate -format Logic /tb_mips_top/clk
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add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/stall
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add wave -noupdate -divider PC
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add wave -noupdate -format Logic /tb_mips_top/clk
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/if_stage
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add wave -noupdate -format Logic /tb_mips_top/clk
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add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/id_stage
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add wave -noupdate -format Logic /tb_mips_top/clk
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_din
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add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/ex_stage
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add wave -noupdate -format Logic /tb_mips_top/clk
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add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/mem_stage
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add wave -noupdate -format Logic /tb_mips_top/clk
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_din
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add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/wb_stage
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add wave -noupdate -format Logic /tb_mips_top/clk
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 1} {0 ps} 0}
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WaveRestoreCursors {{Cursor 1} {21313433 ps} 0}
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configure wave -namecolwidth 188
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configure wave -valuecolwidth 100
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configure wave -justifyvalue left
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@@ -37,136 +37,78 @@ END tb_mips_top;
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ARCHITECTURE behavior OF tb_mips_top IS
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COMPONENT mips_top
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Port
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PORT
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(
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rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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halt : in STD_LOGIC;
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imem_din : in unsigned (WORD_WIDTH-1 downto 0);
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imem_addr : out unsigned (WORD_WIDTH-1 downto 0);
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dmem_we : out STD_LOGIC;
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dmem_re : out STD_LOGIC;
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dmem_din : in unsigned (WORD_WIDTH-1 downto 0);
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dmem_dout : out unsigned (WORD_WIDTH-1 downto 0);
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dmem_addr : out unsigned (WORD_WIDTH-1 downto 0)
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);
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END COMPONENT;
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COMPONENT rom
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Port
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(
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clk : in STD_LOGIC;
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addr : in word_t;
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dout : out word_t
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);
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END COMPONENT;
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COMPONENT ram
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Generic
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(
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word_addr_width : integer
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);
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Port
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(
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clk : in STD_LOGIC;
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we : in STD_LOGIC;
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addr : in word_t;
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din : in word_t;
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dout : out word_t
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debug : out unsigned(1 downto 0);
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RST_I : in STD_LOGIC;
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CLK_I : in STD_LOGIC;
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ACK_I : in STD_LOGIC;
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SRDY_I : in STD_LOGIC;
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ADDR_O : out word_t;
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DAT_I : in word_t;
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DAT_O : out word_t;
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WE_O : out STD_LOGIC;
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SEL_O : out unsigned(3 downto 0);
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CYC_O : out STD_LOGIC;
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STB_O : out STD_LOGIC;
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MRDY_O : out STD_LOGIC;
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INT : in unsigned (5 downto 0)
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);
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END COMPONENT;
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constant CLK_PERIOD : time := 10 ns;
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signal rst : std_logic := '1';
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signal clk : std_logic := '1';
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signal cpu_halt : std_logic;
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signal irom_data : word_t := (others => '-');
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signal irom_addr : word_t;
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signal dmem_din : word_t := (others => '-');
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signal dmem_dout : word_t;
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signal dmem_addr : word_t;
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signal dmem_we : std_logic;
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signal dmem_re : std_logic;
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signal debug : unsigned(1 downto 0);
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signal RST_I : STD_LOGIC := '1';
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signal CLK_I : STD_LOGIC := '0';
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signal ACK_I : STD_LOGIC := '0';
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signal SRDY_I : STD_LOGIC := '0';
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signal ADDR_O : word_t;
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signal DAT_I : word_t := (others => '0');
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signal DAT_O : word_t;
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signal WE_O : STD_LOGIC;
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signal SEL_O : unsigned(3 downto 0);
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signal CYC_O : STD_LOGIC;
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signal STB_O : STD_LOGIC;
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signal MRDY_O : STD_LOGIC;
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signal INT : unsigned (5 downto 0) := (others => '0');
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BEGIN
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uut: mips_top
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PORT MAP(
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rst => rst,
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clk => clk,
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halt => cpu_halt,
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imem_din => irom_data,
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imem_addr => irom_addr,
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dmem_we => dmem_we,
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dmem_re => dmem_re,
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dmem_din => dmem_din,
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dmem_dout => dmem_dout,
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dmem_addr => dmem_addr
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);
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inst_rom: rom
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PORT MAP
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(
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clk => clk,
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addr => irom_addr,
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dout => irom_data
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);
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inst_ram: ram
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GENERIC MAP
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(
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word_addr_width => 6
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)
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PORT MAP
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(
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clk => clk,
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we => dmem_we,
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addr => dmem_addr,
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din => dmem_dout,
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dout => dmem_din
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debug => debug,
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RST_I => RST_I,
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CLK_I => CLK_I,
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ACK_I => ACK_I,
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SRDY_I => SRDY_I,
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ADDR_O => ADDR_O,
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DAT_I => DAT_I,
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DAT_O => DAT_O,
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WE_O => WE_O,
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SEL_O => SEL_O,
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CYC_O => CYC_O,
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STB_O => STB_O,
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MRDY_O => MRDY_O,
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INT => INT
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);
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CLK_GEN: process
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begin
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wait for CLK_PERIOD/2;
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clk <= not clk;
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end process;
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HLT_GEN:
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process(rst, clk)
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subtype cnt_t is natural range 0 to 2;
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variable cnt : cnt_t;
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begin
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if rst = '1' then
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cnt := cnt_t'high;
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cpu_halt <= '0';
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elsif rising_edge(clk) then
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cpu_halt <= '0';
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if cnt /= 0 then
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cnt := cnt - 1;
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else
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cnt := cnt_t'high;
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cpu_halt <= '1';
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end if;
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end if;
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CLK_I <= not CLK_I;
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end process;
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STIMULUS: process
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begin
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-- for i in 0 to instr_name_array'length-1 loop
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-- fprint(RESULT, L,"%d %s\n", fo(i), instr_name_array(i));
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-- end loop;
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wait for 3*CLK_PERIOD;
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wait until rising_edge(clk);
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rst <= '0';
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wait for 2*CLK_PERIOD;
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-- assert false report "Test finished" severity error;
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wait until rising_edge(CLK_I);
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RST_I <= '0';
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wait;
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end process;
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