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- Loads image for bugfix: instructions uncached LW => cached LW (with cache-miss) was buggy.

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git-svn-id: http://moon:8086/svn/vhdl/trunk@682 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-11-24 11:35:08 +00:00
parent 21b41da6e2
commit 1f387fdd75
1 changed files with 2 additions and 2 deletions
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lib/CPUs/MIPS/src/tb_mips_top.vhd
+2 -2
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@@ -394,7 +394,7 @@ SRAM_WRITE:
FLASH_READ:
process(rst, flash_cs_n, flash_oe_n, flash_a)
type file_t is file of integer;
file load_flash : file_t open read_mode is "lwl.flash.bin";
file load_flash : file_t open read_mode is "ucb.elf.flash.bin";
variable instr : integer;
variable index : natural;
variable temp : signed(31 downto 0);
@@ -441,7 +441,7 @@ STIMULUS: process
rst <= '0';
wait for 778254*CLK_PERIOD;
wait until rising_edge(clk);
nmi <= '1';
nmi <= '0';
wait for 3000*CLK_PERIOD;
wait until rising_edge(clk);
nmi <= '0';