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- bugfix: BLIT IRQ-ack had no effect

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- increased BLIT chunk-size to 512 QWORDs
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git-svn-id: http://moon:8086/svn/vhdl/trunk@690 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-11-28 20:32:28 +00:00
parent 7023fc8c69
commit ebf615967c
1 changed files with 4 additions and 6 deletions
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lib/VGA_ctrl/src/vga_frontend64.vhd
+4 -6
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@@ -167,7 +167,7 @@ architecture Behavioral of vga_frontend64 is
signal back : unsigned(31 downto 0);
-- Blitter vars
constant BLIT_CHUNK_SIZE : natural := 128;
constant BLIT_CHUNK_SIZE : natural := 512;
signal blit_chunk_cnt : natural range 0 to BLIT_CHUNK_SIZE-1;
-- Blitter FIFO signals
@@ -255,10 +255,8 @@ proc_blit_request_flags:
if rising_edge(CLK_I) then
if RST_I = '1' then
blit_request <= '0';
elsif blit_request = '0' then
if blit_request_set = '1' then
blit_request <= '1';
end if;
elsif blit_request_set = '1' then
blit_request <= '1';
elsif blit_dst_finish = '1' and blitfifo_empty = '1' then
blit_request <= '0';
end if;
@@ -271,7 +269,7 @@ proc_blit_complete_flag:
if rising_edge(CLK_I) then
if RST_I = '1' or blit_request_set = '1' or blit_complete_ack = '1' then
blit_complete <= '0';
elsif blit_dst_finish = '1' and blitfifo_empty = '1' then
elsif blit_dst_finish = '1' and blitfifo_empty = '1' and blit_request = '1' then
blit_complete <= '1';
end if;
end if;