jens 023b7e42a3 - added dedicated sys_clk_out frequency synthesis ...

- SDRAM clocks use sys_clk_out for clock generation
- added cpu_clk_out which is the same as sys_clk_in

Committed on the Free edition of March Hare Software CVSNT Server.
Upgrade to CVS Suite for more features and support:
http://march-hare.com/cvsnt/


git-svn-id: http://moon:8086/svn/vhdl/trunk@727 cc03376c-175c-47c8-b038-4cd826a8556b

2010-02-07 19:16:11 +00:00

Common

- Intital revision

2008-10-26 23:52:49 +00:00

lib

- added asynchronous BUS FIFOs

2010-02-07 19:12:19 +00:00

projects/mips_sys

- added dedicated sys_clk_out frequency synthesis

2010-02-07 19:16:11 +00:00

S

Description

No description provided

23 MiB

Languages

VHDL 90.1%

Verilog 4.2%

Tcl 2.5%

SystemVerilog 0.8%

IGOR Pro 0.5%

Other 1.5%