jens 5ce761ead5 - removed RAM-init during synthesizing ...

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git-svn-id: http://moon:8086/svn/vhdl/trunk@323 cc03376c-175c-47c8-b038-4cd826a8556b

2009-02-08 17:32:41 +00:00

Common

- Intital revision

2008-10-26 23:52:49 +00:00

lib

- removed RAM-init during synthesizing

2009-02-08 17:32:41 +00:00

projects/mips_sys

- update

2009-01-30 21:43:29 +00:00

S

Description

No description provided

23 MiB

Languages

VHDL 90.1%

Verilog 4.2%

Tcl 2.5%

SystemVerilog 0.8%

IGOR Pro 0.5%

Other 1.5%