- Cleaned up
git-svn-id: http://moon:8086/svn/vhdl/trunk@118 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -1,35 +0,0 @@
|
||||
vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_types.vhd"
|
||||
vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_instr.vhd"
|
||||
vhdl work "../../src/sdram_config.vhd"
|
||||
vhdl work "../../../../lib/misc/utils_pkg.vhd"
|
||||
vhdl work "../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
|
||||
vhdl work "../../../../lib/misc/dpram_1w2r.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_types.vhd"
|
||||
vhdl work "../../../../lib/FIFO/src/sync_fifo_ctrl.vhd"
|
||||
vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_shifter.vhd"
|
||||
vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_reg.vhd"
|
||||
vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_muldiv.vhd"
|
||||
vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_idecode_rom.vhd"
|
||||
vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_cop.vhd"
|
||||
vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_bcu.vhd"
|
||||
vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_alu.vhd"
|
||||
vhdl work "../../../../lib/uart/kcuart_tx.vhd"
|
||||
vhdl work "../../../../lib/uart/kcuart_rx.vhd"
|
||||
vhdl work "../../../../lib/uart/bbfifo_16x8.vhd"
|
||||
vhdl work "../../../../lib/misc/dpram_2w2r_virtex4.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_cmd.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/reset_virtex4.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/fifo_sync.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/ddr_phy_virtex4.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/clockgen_virtex4.vhd"
|
||||
vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_pipeline.vhd"
|
||||
vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_bui.vhd"
|
||||
vhdl work "../../src/ram_ld.vhd"
|
||||
vhdl work "../../asm/bootloader/bootloader.ROM_ld.vhd"
|
||||
vhdl work "../../../../lib/uart/uart_tx.vhd"
|
||||
vhdl work "../../../../lib/uart/uart_rx.vhd"
|
||||
vhdl work "../../../../lib/misc/lcd_port.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_top.vhd"
|
||||
vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_top.vhd"
|
||||
vhdl work "../../src/mips_sys.vhd"
|
||||
@@ -1,35 +0,0 @@
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_instr.vhd"
|
||||
vhdl work "W:\vhdl\projects\mips_sys\src\sdram_config.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\utils_pkg.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\dpram_1w2r.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_types.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\sync_fifo_ctrl.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_shifter.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_reg.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_muldiv.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_idecode_rom.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_cop.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bcu.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_alu.vhd"
|
||||
vhdl work "W:\vhdl\lib\uart\kcuart_tx.vhd"
|
||||
vhdl work "W:\vhdl\lib\uart\kcuart_rx.vhd"
|
||||
vhdl work "W:\vhdl\lib\uart\bbfifo_16x8.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\dpram_2w2r_virtex4.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_ctrl.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_cmd.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\reset_virtex4.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\fifo_sync.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\ddr_phy_virtex4.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\clockgen_virtex4.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_pipeline.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bui.vhd"
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vhdl work "W:\vhdl\projects\mips_sys\src\ram_ld.vhd"
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vhdl work "W:\vhdl\projects\mips_sys\asm\bootloader\bootloader.ROM_ld.vhd"
|
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vhdl work "W:\vhdl\lib\uart\uart_tx.vhd"
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vhdl work "W:\vhdl\lib\uart\uart_rx.vhd"
|
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vhdl work "W:\vhdl\lib\misc\lcd_port.vhd"
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vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_ctrl_top.vhd"
|
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vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_top.vhd"
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vhdl work "W:\vhdl\projects\mips_sys\src\mips_sys.vhd"
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@@ -1,245 +0,0 @@
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#
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# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
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# SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
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# XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
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# AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
|
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# OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
|
||||
# IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
|
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# AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
|
||||
# FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
|
||||
# WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
|
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# IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
|
||||
# REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
|
||||
# INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
# FOR A PARTICULAR PURPOSE.
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||||
#
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# (c) Copyright 2005 Xilinx, Inc.
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# All rights reserved.
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#
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CONFIG STEPPING = "ES";
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# Bus clock nets
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NET "clk" TNM_NET = "clk";
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TIMESPEC "TS_clk" = PERIOD "clk" 9.9 ns HIGH 50 %;
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NET "sys_clk_in" LOC = "AE14";
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#NET sys_clk_in IOSTANDARD = LVCMOS33;
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NET "sys_rst_n_in" LOC = "D6";
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NET sys_rst_n_in PULLUP;
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NET "sys_rst_n_in" TIG;
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NET "rst" TIG;
|
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|
||||
# Locate DCM/BUFG - Tools can probably figure them out automatically
|
||||
# but just LOC them down to be safe
|
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#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_0 LOC = DCM_ADV_X0Y2;
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#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_1 LOC = DCM_ADV_X0Y1;
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////////////////////////////////////////////////////////////////////////////
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// Misc Board Signals
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////////////////////////////////////////////////////////////////////////////
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NET sys_error<0> LOC = V6;
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NET sys_error<1> LOC = L24;
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||||
#NET sys_error<*> IOSTANDARD = LVCMOS33;
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NET sys_error<*> DRIVE = 2;
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NET sys_error<*> TIG;
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////////////////////////////////////////////////////////////////////////////
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// RS-232
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////////////////////////////////////////////////////////////////////////////
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NET sys_rx LOC = W2;
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#NET sys_rx IOSTANDARD = LVCMOS33;
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NET sys_rx TIG;
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NET "sys_tx" LOC = "W1";
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#NET sys_tx IOSTANDARD = LVCMOS33;
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NET "sys_tx" TIG;
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////////////////////////////////////////////////////////////////////////////
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// Buttons, LEDs, and DIP Switches
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////////////////////////////////////////////////////////////////////////////
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# GPLED 0-3
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NET "sys_led<0>" LOC = "G5"; #GPLED0
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NET "sys_led<1>" LOC = "G6"; #GPLED1
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NET "sys_led<2>" LOC = "A11"; #GPLED2
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NET "sys_led<3>" LOC = "A12"; #GPLED3
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# North-East-South-West-Center LEDs
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NET "sys_led<4>" LOC = "F9"; # W LED
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NET "sys_led<5>" LOC = "E2"; # N LED
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NET "sys_led<6>" LOC = "E10"; # E LED
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NET "sys_led<7>" LOC = "A5"; # S LED
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NET "sys_led<8>" LOC = "C6"; # C LED
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NET "sys_led<*>" TIG;
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NET "sys_led<*>" SLEW = SLOW;
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NET "sys_led<*>" DRIVE = 2;
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#NET "sys_led<*>" IOSTANDARD = LVCMOS33;
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# North-East-South-West-Center Buttons
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NET "sys_btn<0>" LOC = "E9"; # W Button
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NET "sys_btn<1>" LOC = "E7"; # N Button
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NET "sys_btn<2>" LOC = "F10"; # E Button
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NET "sys_btn<3>" LOC = "A6"; # S Button
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NET "sys_btn<4>" LOC = "B6"; # C Button
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NET "sys_btn<*>" TIG;
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NET "sys_btn<*>" PULLDOWN;
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#NET "sys_btn<*>" IOSTANDARD = LVCMOS33;
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# Dip Switches 1-8
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NET "sys_dip<7>" LOC = "U24"; # DIP SW 8
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NET "sys_dip<6>" LOC = "U25"; # DIP SW 7
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NET "sys_dip<5>" LOC = "V23"; # DIP SW 6
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NET "sys_dip<4>" LOC = "U23"; # DIP SW 5
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NET "sys_dip<3>" LOC = "U26"; # DIP SW 4
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NET "sys_dip<2>" LOC = "T26"; # DIP SW 3
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NET "sys_dip<1>" LOC = "R19"; # DIP SW 2
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NET "sys_dip<0>" LOC = "R20"; # DIP SW 1
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NET "sys_dip<*>" PULLDOWN;
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#NET "sys_dip<*>" IOSTANDARD = LVCMOS33;
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NET "sys_dip<*>" TIG;
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////////////////////////////////////////////////////////////////////////////
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// LCD
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////////////////////////////////////////////////////////////////////////////
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NET sys_lcd_e LOC = AE13; # LCD_E
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#NET sys_lcd_e IOSTANDARD = LVCMOS33;
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NET sys_lcd_e SLEW = SLOW;
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NET sys_lcd_e DRIVE = 2;
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NET sys_lcd_e TIG;
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NET sys_lcd_rs LOC = AC17; # LCD_RS
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#NET sys_lcd_rs IOSTANDARD = LVCMOS33;
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NET sys_lcd_rs SLEW = SLOW;
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NET sys_lcd_rs DRIVE = 2;
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NET sys_lcd_rs TIG;
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NET sys_lcd_rw LOC = AB17; # LCD_RW
|
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#NET sys_lcd_rw IOSTANDARD = LVCMOS33;
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NET sys_lcd_rw SLEW = SLOW;
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NET sys_lcd_rw DRIVE = 2;
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NET sys_lcd_rw TIG;
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NET sys_lcd_d<3> LOC = AF12; # LCD_DB7
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NET sys_lcd_d<2> LOC = AE12; # LCD_DB6
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NET sys_lcd_d<1> LOC = AC10; # LCD_DB5
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NET sys_lcd_d<0> LOC = AB10; # LCD_DB4
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#NET sys_lcd_d<*> IOSTANDARD = LVCMOS33;
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NET sys_lcd_d<*> SLEW = SLOW;
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NET sys_lcd_d<*> DRIVE = 2;
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NET sys_lcd_d<*> PULLDOWN;
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NET sys_lcd_d<*> TIG;
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|
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#------------------------------------------------------------------------------
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# IO Pad Location Constraints / Properties for DDR Controllers
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#------------------------------------------------------------------------------
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NET sys_sdr_a_q<0> LOC = C26; # DDR_A0
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NET sys_sdr_a_q<1> LOC = E17; # DDR_A1
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NET sys_sdr_a_q<2> LOC = D18; # DDR_A2
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NET sys_sdr_a_q<3> LOC = C19; # DDR_A3
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NET sys_sdr_a_q<4> LOC = F17; # DDR_A4
|
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NET sys_sdr_a_q<5> LOC = B18; # DDR_A5
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NET sys_sdr_a_q<6> LOC = B20; # DDR_A6
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NET sys_sdr_a_q<7> LOC = C20; # DDR_A7
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NET sys_sdr_a_q<8> LOC = D20; # DDR_A8
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NET sys_sdr_a_q<9> LOC = C21; # DDR_A9
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NET sys_sdr_a_q<10> LOC = A18; # DDR_A10
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NET sys_sdr_a_q<11> LOC = B21; # DDR_A11
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NET sys_sdr_a_q<12> LOC = A24; # DDR_A12
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NET sys_sdr_ba_q<0> LOC = B12; # DDR_BA0
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NET sys_sdr_ba_q<1> LOC = A16; # DDR_BA1
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NET sys_sdr_cas_qn LOC = F23; # DDR_CAS_N
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NET sys_sdr_cke_q LOC = G22; # DDR_CKE
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NET sys_sdr_cs_qn LOC = G21; # DDR_CS_N
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NET sys_sdr_ras_qn LOC = F24; # DDR_RAS_N
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||||
NET sys_sdr_we_qn LOC = A23; # DDR_WE_N
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NET sys_sdr_clk_p LOC = A10; # DDR_CK1_P
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||||
NET sys_sdr_clk_fb LOC = B13; # DDR_CK1_P (FEEDBACK)
|
||||
NET sys_sdr_clk_n LOC = B10; # DDR_CK1_N
|
||||
|
||||
NET sys_sdr_dm_q<0> LOC = G19; # DDR_DM0
|
||||
NET sys_sdr_dm_q<1> LOC = G24; # DDR_DM1
|
||||
NET sys_sdr_dm_q<2> LOC = G20; # DDR_DM2
|
||||
NET sys_sdr_dm_q<3> LOC = C22; # DDR_DM3
|
||||
|
||||
NET sys_sdr_dqs_q<0> LOC = D25; # DDR_DQS0
|
||||
NET sys_sdr_dqs_q<1> LOC = G18; # DDR_DQS1
|
||||
NET sys_sdr_dqs_q<2> LOC = G17; # DDR_DQS2
|
||||
NET sys_sdr_dqs_q<3> LOC = D26; # DDR_DQS3
|
||||
|
||||
NET sys_sdr_data<0> LOC = H20; # DDR_D0
|
||||
NET sys_sdr_data<1> LOC = E23; # DDR_D1
|
||||
NET sys_sdr_data<2> LOC = H26; # DDR_D2
|
||||
NET sys_sdr_data<3> LOC = H22; # DDR_D3
|
||||
NET sys_sdr_data<4> LOC = E25; # DDR_D4
|
||||
NET sys_sdr_data<5> LOC = E26; # DDR_D5
|
||||
NET sys_sdr_data<6> LOC = F26; # DDR_D6
|
||||
NET sys_sdr_data<7> LOC = E24; # DDR_D7
|
||||
NET sys_sdr_data<8> LOC = E20; # DDR_D8
|
||||
NET sys_sdr_data<9> LOC = A22; # DDR_D9
|
||||
NET sys_sdr_data<10> LOC = C23; # DDR_D10
|
||||
NET sys_sdr_data<11> LOC = C24; # DDR_D11
|
||||
NET sys_sdr_data<12> LOC = A20; # DDR_D12
|
||||
NET sys_sdr_data<13> LOC = A21; # DDR_D13
|
||||
NET sys_sdr_data<14> LOC = D24; # DDR_D14
|
||||
NET sys_sdr_data<15> LOC = E18; # DDR_D15
|
||||
NET sys_sdr_data<16> LOC = F18; # DDR_D16
|
||||
NET sys_sdr_data<17> LOC = A19; # DDR_D17
|
||||
NET sys_sdr_data<18> LOC = F19; # DDR_D18
|
||||
NET sys_sdr_data<19> LOC = B23; # DDR_D19
|
||||
NET sys_sdr_data<20> LOC = E21; # DDR_D20
|
||||
NET sys_sdr_data<21> LOC = D22; # DDR_D21
|
||||
NET sys_sdr_data<22> LOC = D23; # DDR_D22
|
||||
NET sys_sdr_data<23> LOC = B24; # DDR_D23
|
||||
NET sys_sdr_data<24> LOC = E22; # DDR_D24
|
||||
NET sys_sdr_data<25> LOC = F20; # DDR_D25
|
||||
NET sys_sdr_data<26> LOC = H23; # DDR_D26
|
||||
NET sys_sdr_data<27> LOC = G25; # DDR_D27
|
||||
NET sys_sdr_data<28> LOC = G26; # DDR_D28
|
||||
NET sys_sdr_data<29> LOC = H25; # DDR_D29
|
||||
NET sys_sdr_data<30> LOC = H24; # DDR_D30
|
||||
NET sys_sdr_data<31> LOC = H21; # DDR_D31
|
||||
|
||||
NET sys_sdr_a_q<*> IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_a_q<*> FAST;
|
||||
|
||||
NET sys_sdr_ba_q<*> IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_ba_q<*> FAST;
|
||||
|
||||
NET sys_sdr_cas_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_cas_qn FAST;
|
||||
|
||||
NET sys_sdr_cke_q IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_cke_q FAST;
|
||||
|
||||
NET sys_sdr_clk_p IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_clk_p FAST;
|
||||
NET sys_sdr_clk_fb IOSTANDARD = LVCMOS25;
|
||||
NET sys_sdr_clk_fb IOBDELAY = NONE;
|
||||
NET sys_sdr_clk_n IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_clk_n FAST;
|
||||
|
||||
NET sys_sdr_cas_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_cas_qn FAST;
|
||||
|
||||
NET sys_sdr_cs_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_cs_qn FAST;
|
||||
|
||||
NET sys_sdr_ras_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_ras_qn FAST;
|
||||
|
||||
NET sys_sdr_we_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_we_qn FAST;
|
||||
|
||||
NET sys_sdr_dqs_q<*> IOSTANDARD = SSTL2_II;
|
||||
NET sys_sdr_dqs_q<*> IOBDELAY = NONE;
|
||||
NET sys_sdr_dqs_q<*> FAST;
|
||||
|
||||
NET sys_sdr_dm_q<*> IOSTANDARD = SSTL2_II;
|
||||
NET sys_sdr_dm_q<*> IOBDELAY = NONE;
|
||||
NET sys_sdr_dm_q<*> FAST;
|
||||
|
||||
NET sys_sdr_data<*> IOSTANDARD = SSTL2_II;
|
||||
NET sys_sdr_data<*> IOBDELAY = NONE;
|
||||
NET sys_sdr_data<*> FAST;
|
||||
|
||||
#NET "sys_sdr_data<*>" OFFSET=OUT 2.5 ns BEFORE "sys_sdr_clk_n";
|
||||
|
||||
|
||||
# Timing Constraint for DDR Feedback Clock
|
||||
NET sys_sdr_clk_fb FEEDBACK = 1 ns NET sys_sdr_clk_p;
|
||||
|
||||
Reference in New Issue
Block a user