- Intital revision

git-svn-id: http://moon:8086/svn/vhdl/trunk@146 cc03376c-175c-47c8-b038-4cd826a8556b

lib/radio/nco/sim/tb_mix_cordic.fdo

@@ -0,0 +1,19 @@
+vlib work
+vcom -explicit  -93 "../../../fixed/fixed_pkg_c.vhd"
+vcom -explicit  -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993.vhd"
+vcom -explicit  -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
+vcom -explicit  -93 "../../cordic/src/cordic_pkg.vhd"
+vcom -explicit  -93 "../../cordic/src/cordic_pipe_stage.vhd"
+vcom -explicit  -93 "../../cordic/src/cordic_pipe_pre.vhd"
+vcom -explicit  -93 "../../cordic/src/cordic_pipe_post.vhd"
+vcom -explicit  -93 "../../cordic/src/cordic_pipe_top.vhd"
+vcom -explicit  -93 "../src/nco_pkg.vhd"
+vcom -explicit  -93 "../src/nco_cordic_dbg.vhd"
+vcom -explicit  -93 "../src/mix_cordic_dbg.vhd"
+vcom -explicit  -93 "../src/tb_mix_cordic.vhd"
+vsim -t 1ps   -lib work tb_mix
+do {tb_mix_cordic.wdo}
+view wave
+view structure
+view signals
+run 250us

lib/radio/nco/sim/tb_mix_cordic.wdo

@@ -0,0 +1,33 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_mix/clk
+add wave -noupdate -format Logic /tb_mix/srst
+add wave -noupdate -format Logic /tb_mix/pacc_clr
+add wave -noupdate -format Logic /tb_mix/pacc_inc
+add wave -noupdate -format Logic /tb_mix/phase_load
+add wave -noupdate -format Logic /tb_mix/freq_load
+add wave -noupdate -format Literal -radix decimal /tb_mix/freq_in
+add wave -noupdate -format Literal -radix decimal /tb_mix/phase_in
+add wave -noupdate -format Analog-Step -radix decimal -scale 0.00025940300000000001 /tb_mix/wave_in_i
+add wave -noupdate -format Analog-Step -radix decimal -scale 0.00025940300000000001 /tb_mix/wave_in_q
+add wave -noupdate -format Literal -radix decimal /tb_mix/wave_out_i
+add wave -noupdate -format Literal -radix decimal /tb_mix/wave_out_q
+add wave -noupdate -format Logic /tb_mix/out_valid
+add wave -noupdate -format Literal /tb_mix/mix_debug_out
+add wave -noupdate -format Literal /tb_mix/rfgen_debug_out
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {77110000 ps} 0}
+configure wave -namecolwidth 193
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+update
+WaveRestoreZoom {246747082 ps} {250171207 ps}

lib/radio/nco/sim/tb_mix_results.m

@@ -0,0 +1,58 @@
+% Read data
+function tb_mix_results()
+fa = 100.0;
+f = TEXTREAD('freq.txt')*1E-6
+
+I_in = TEXTREAD('i_in.txt')';
+I_out = TEXTREAD('i_out.txt')';
+
+N= length(I_out);
+N_fft = N
+N_fft2 = N_fft/2;
+
+fft_y2 = 2/N_fft*abs(fft(I_out(1:N_fft).*hann(N_fft)'));
+
+[i, v] = get_maxpur(fft_y2, fa, f);
+max_spur_freq = (i*fa/N_fft);
+max_spur_value = 20*log10(v);
+
+fft_y3 = 2/N_fft*abs(fft(I_in(1:N_fft).*hann(N_fft)'));
+
+[i, v] = get_maxpur(fft_y3, fa, f);
+max_ditherd_spur_freq = (i*fa/N_fft);
+max_ditherd_spur_value = 20*log10(v);
+
+% Output
+close all;
+
+subplot(2,1,1)
+plot(fa/N_fft*(0:N_fft2),20*log10(fft_y2(1:N_fft2+1)), '-', fa/N_fft*(0:N_fft2), max_spur_value*ones(1,N_fft2+1), 'r-', [max_spur_freq], [max_spur_value], 'ro'); grid;
+spur_legend = sprintf('Max. spur %.1fdB at %.3fMHz', max_spur_value, max_spur_freq);
+legend('With dithering', spur_legend);
+legend('No dithering', spur_legend);
+title('Table');
+ylabel('dB');
+xlabel('f/MHz');
+axis([0 fa/2 -140 0]);
+subplot(2,1,2)
+plot(fa/N_fft*(0:N_fft2),20*log10(fft_y3(1:N_fft2+1)), '-', fa/N_fft*(0:N_fft2), max_ditherd_spur_value*ones(1,N_fft2+1), 'r-', [max_ditherd_spur_freq], [max_ditherd_spur_value], 'ro'); grid;
+spur_legend = sprintf('Max. spur %.1fdB at %.3fMHz', max_ditherd_spur_value, max_ditherd_spur_freq);
+legend('With dithering', spur_legend);
+title('Table');
+ylabel('dB');
+xlabel('f/MHz');
+axis([0 fa/2 -140 0]);
+
+function [max_i, max_v] = get_maxpur(spec, fa, f)
+max_v = 0;
+max_i = 0;
+for ii=1:fix(length(spec)/2+1),
+	fi = ii*fa/length(spec);
+	dfi = fi - f;
+	if abs(dfi) > 0.005*f
+		if spec(ii) > max_v
+			max_v = spec(ii);
+			max_i = ii-1;
+		end
+	end;
+end;

lib/radio/nco/src/mix_cordic_dbg.vhd

@@ -0,0 +1,209 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:    12:16:14 10/02/05
+-- Design Name:    
+-- Module Name:    cordic_stage - Behavioral
+-- Project Name:   
+-- Target Device:  
+-- Tool versions:  
+-- Description:
+--
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.MATH_REAL.ALL;
+USE ieee.numeric_std.ALL;
+use work.fixed_pkg.all;
+use work.cordic_pkg.all;
+use work.nco_pkg.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity mix is
+Generic
+(
+	nbits_wave_in	: integer := 18;
+	nbits_wave_out	: integer := 18;
+	nbits_phase		: integer := 16
+);
+Port
+(
+	srst		: in std_logic;
+	clk			: in std_logic;
+	pacc_clr	: in std_logic;
+	pacc_inc	: in std_logic;
+	freq_in		: in unsigned(nbits_phase-1 downto 0);
+	freq_load	: in std_logic;
+	phase_in	: in unsigned(nbits_phase-1 downto 0);
+	phase_load	: in std_logic;
+	wave_in_i	: in  sfixed;
+	wave_in_q	: in  sfixed;
+	wave_out_i	: out sfixed;
+	wave_out_q	: out sfixed;
+	out_valid	: out std_logic;
+	debug_out	: out debug_mix_out_t
+);
+end mix;
+
+architecture Behavioral of mix is
+
+	COMPONENT cordic_pipe_top
+	GENERIC 
+	(
+		cordic_mode			: cordic_mode_t;
+		z_range				: real;
+		gain_corr_mode		: gain_corr_mode_t;
+		nstages				: integer;
+		nbits_x_in			: integer;
+		nbits_y_in			: integer;
+		nbits_z_in			: integer;
+		nbits_frac_x_in		: integer;
+		nbits_frac_y_in		: integer;
+		nbits_frac_z_in		: integer;
+		nbits_x_out			: integer;
+		nbits_y_out			: integer;
+		nbits_z_out			: integer;
+		nbits_frac_x_out	: integer;
+		nbits_frac_y_out	: integer;
+		nbits_frac_z_out	: integer
+	);
+	PORT
+	(
+		rst					: in std_logic;
+		clk					: in std_logic;
+		vld_in				: in std_logic;
+		xin					: in sfixed;
+		yin					: in sfixed;
+		zin					: in sfixed;
+		xout				: out sfixed;
+		yout				: out sfixed;
+		zout				: out sfixed;
+		vld_out				: out std_logic
+	);
+	END COMPONENT;
+
+-------------------------------------------------------------------------------
+	constant nbits_wave_in_frac : integer := nbits_wave_in-1;
+	constant nbits_wave_out_frac : integer := nbits_wave_out-1;
+	constant nbits_phase_frac : integer := nbits_phase;
+
+-------------------------------------------------------------------------------
+	signal phase : signed(nbits_phase-1 downto 0);
+	signal freq_in_r : signed(nbits_phase-1 downto 0);
+	signal phase_in_r : signed(nbits_phase-1 downto 0);
+	signal xin, yin : sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac));
+	signal xout, yout : sfixed(shi(nbits_wave_out, nbits_wave_out_frac) downto slo(nbits_wave_out, nbits_wave_out_frac));
+	
+	signal wave_out_valid : std_logic;
+
+	signal zin : sfixed(shi(nbits_phase, nbits_phase_frac) downto slo(nbits_phase, nbits_phase_frac));
+	signal zout : sfixed(shi(nbits_phase, nbits_phase_frac) downto slo(nbits_phase, nbits_phase_frac));
+	
+-------------------------------------------------------------------------------
+begin
+
+	wave_out_i	<= xout;
+	wave_out_q	<= yout;
+	xin			<= wave_in_i;
+	yin			<= wave_in_q;
+	
+	out_valid <= wave_out_valid;
+
+	debug_out.i_in <= to_real(wave_in_i);
+	debug_out.q_in <= to_real(wave_in_q);
+	debug_out.i_out <= to_real(xout);
+	debug_out.q_out <= to_real(yout);
+
+
+------------------------------------------------------------
+	proc_phase_accu: process(clk)
+	variable phase_accu : signed(nbits_phase-1 downto 0);
+
+	begin
+		if rising_edge(clk) then 
+			if srst = '1' then
+				phase_accu := (others => '0');
+			else
+				phase <= phase_accu + phase_in_r;
+				if pacc_clr = '1' then
+					phase_accu := (others => '0');
+				elsif pacc_inc = '1' then
+					phase_accu := phase_accu + freq_in_r;
+				end if;	
+			end if;	
+		end if;
+		zin	<= sfixed(phase);
+	end process;
+
+------------------------------------------------------------
+	freq_in_reg: process(srst, clk, freq_load, freq_in)
+	begin
+		if rising_edge(clk) then
+			if srst = '1' then
+				freq_in_r <= (others => '0');
+			elsif freq_load = '1' then
+				freq_in_r <= signed(freq_in);
+			end if;
+		end if;
+	end process;
+
+------------------------------------------------------------
+	phase_in_reg: process(srst, clk, phase_load, phase_in)
+	begin
+		if rising_edge(clk) then
+			if srst = '1' then
+				phase_in_r <= (others => '0');
+			elsif phase_load = '1' then
+				phase_in_r <= signed(phase_in);
+			end if;
+		end if;
+	end process;
+
+------------------------------------------------------------
+	inst_cordic_ud: cordic_pipe_top
+	GENERIC MAP
+	(
+		cordic_mode 		=> cordic_mode_rotate,
+		z_range				=> 1.0,
+		gain_corr_mode		=> gain_mode_disabled,
+		nstages				=> nbits_phase,
+		nbits_x_in			=> nbits_wave_in,
+		nbits_frac_x_in		=> nbits_wave_in_frac,
+		nbits_y_in			=> nbits_wave_in,
+		nbits_frac_y_in		=> nbits_wave_in_frac,
+		nbits_z_in			=> nbits_phase,
+		nbits_frac_z_in		=> nbits_phase_frac,
+		nbits_x_out			=> nbits_wave_out,
+		nbits_frac_x_out	=> nbits_wave_out_frac,
+		nbits_y_out			=> nbits_wave_out,
+		nbits_frac_y_out	=> nbits_wave_out_frac,
+		nbits_z_out			=> nbits_phase,
+		nbits_frac_z_out	=> nbits_phase_frac
+	)
+	PORT MAP
+	(
+		rst					=> srst,
+		clk					=> clk,
+		vld_in				=> '1',
+		xin					=> xin,
+		yin					=> yin,
+		zin					=> zin,
+		xout				=> xout,
+		yout				=> yout,
+		zout				=> zout,
+		vld_out				=> wave_out_valid
+	);
+
+------------------------------------------------------------
+end Behavioral;

lib/radio/nco/src/tb_mix_cordic.vhd

@@ -0,0 +1,373 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:   17:16:42 13.05.2007
+-- Design Name:   tb_nco
+-- Module Name:   tb_nco.vhd
+-- Project Name:  nco
+-- Target Device:  
+-- Tool versions:  
+-- Description:   
+-- 
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.MATH_REAL.ALL;
+USE ieee.numeric_std.ALL;
+use std.textio.all; --  Imports the standard textio package.
+
+library work;
+use work.fixed_pkg.all;
+use work.cordic_pkg.all;
+use work.nco_pkg.all;
+use work.PCK_FIO.all;
+
+ENTITY tb_mix IS
+	Generic 
+	(
+		nbits_wave_in	: integer := 16;
+		nbits_wave_out	: integer := 16;
+		nbits_phase		: integer := 20
+	);
+END tb_mix;
+
+ARCHITECTURE behavior OF tb_mix IS 
+
+	-- Component Declaration for the Unit Under Test (UUT)
+	COMPONENT mix
+	GENERIC 
+	(
+		nbits_wave_in	: integer;
+		nbits_wave_out	: integer;
+		nbits_phase		: integer
+		);
+	PORT(
+		srst		: in std_logic;
+		clk			: in std_logic;
+		pacc_clr	: in std_logic;
+		pacc_inc	: in std_logic;
+		freq_in		: in unsigned(nbits_phase-1 downto 0);
+		freq_load	: in std_logic;
+		phase_in	: in unsigned(nbits_phase-1 downto 0);
+		phase_load	: in std_logic;
+		wave_in_i	: in  sfixed;
+		wave_in_q	: in  sfixed;
+		wave_out_i	: out sfixed;
+		wave_out_q	: out sfixed;
+		out_valid	: out std_logic;
+		debug_out	: out debug_mix_out_t
+	);
+	END COMPONENT;
+
+	-- Rf-Generator
+	COMPONENT nco
+	GENERIC 
+	(
+		nbits_wave		: integer;
+		nbits_phase		: integer
+		);
+	PORT(
+		srst		: in std_logic;
+		clk			: in std_logic;
+		pacc_clr	: in std_logic;
+		pacc_inc	: in std_logic;
+		freq_in		: in unsigned(nbits_phase-1 downto 0);
+		freq_load	: in std_logic;
+		phase_in	: in unsigned(nbits_phase-1 downto 0);
+		phase_load	: in std_logic;
+		phase_out	: out unsigned(nbits_phase-1 downto 0);
+		wave_out_i	: out sfixed;
+		wave_out_q	: out sfixed;
+		out_valid	: out std_logic;
+		debug_out	: out debug_out_t
+	);
+	END COMPONENT;
+
+	--Constants
+	constant f : REAL := 9.125E6;
+	constant frf : REAL := 10.875E6;
+	constant df : REAL := 10.0E3;
+	constant fa : REAL := 100.0E6;
+	constant PERIOD : time := 10 ns;
+	constant num_steps : integer := 1000000;
+
+	constant nbits_wave_in_frac : integer := nbits_wave_in;
+	constant nbits_wave_out_frac : integer := nbits_wave_out;
+	
+	SIGNAL rfgen_freq_word : integer := integer(frf/fa*2.0**nbits_phase);
+	SIGNAL freq_word : integer := integer(f/fa*2.0**nbits_phase);
+	SIGNAL dfreq_word : integer := integer(df/fa*2.0**nbits_phase);
+
+	--Inputs
+	SIGNAL clk         : std_logic := '0';
+	SIGNAL srst        : std_logic := '1';
+	SIGNAL pacc_clr   : std_logic := '0';
+	SIGNAL pacc_inc   : std_logic := '0';
+	SIGNAL phase_load  : std_logic := '0';
+	SIGNAL freq_load   : std_logic := '0';
+	SIGNAL freq_in     : unsigned(nbits_phase-1 downto 0);
+	SIGNAL phase_in    : unsigned(nbits_phase-1 downto 0);
+
+	--Outputs
+	SIGNAL wave_in_i	: sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac));
+	SIGNAL wave_in_q	: sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac));
+	SIGNAL wave_out_i	: sfixed(shi(nbits_wave_out, nbits_wave_out_frac) downto slo(nbits_wave_out, nbits_wave_out_frac));
+	SIGNAL wave_out_q	: sfixed(shi(nbits_wave_out, nbits_wave_out_frac) downto slo(nbits_wave_out, nbits_wave_out_frac));
+	SIGNAL out_valid	: std_logic;
+	SIGNAL mix_debug_out	: debug_mix_out_t;
+	
+	SIGNAL rfgen_pacc_clr   : std_logic := '0';
+	SIGNAL rfgen_pacc_inc   : std_logic := '0';
+	SIGNAL rfgen_phase_load  : std_logic := '0';
+	SIGNAL rfgen_freq_load   : std_logic := '0';
+	SIGNAL rfgen_freq_in     : unsigned(nbits_phase-1 downto 0);
+	SIGNAL rfgen_phase_in    : unsigned(nbits_phase-1 downto 0);
+
+	--Outputs
+	SIGNAL rfgen_wave_out_i	: sfixed(shi(nbits_wave_out, nbits_wave_out_frac) downto slo(nbits_wave_out, nbits_wave_out_frac));
+	SIGNAL rfgen_wave_out_q	: sfixed(shi(nbits_wave_out, nbits_wave_out_frac) downto slo(nbits_wave_out, nbits_wave_out_frac));
+	SIGNAL rfgen_out_valid	: std_logic;
+	SIGNAL rfgen_debug_out	: debug_out_t;
+	SIGNAL fileout_enable   : std_logic := '0';
+
+BEGIN
+
+	-- Instantiate the Unit Under Test (UUT)
+	uut: mix 
+	GENERIC MAP
+	(
+		nbits_wave_in	=> nbits_wave_in,
+		nbits_wave_out	=> nbits_wave_out,
+		nbits_phase		=> nbits_phase
+	)
+	PORT MAP
+	(
+		srst		=> srst,
+		clk			=> clk,
+		pacc_clr	=> pacc_clr,
+		pacc_inc	=> pacc_inc,
+		freq_in		=> freq_in,
+		freq_load	=> freq_load,
+		phase_in	=> phase_in,
+		phase_load	=> phase_load,
+		wave_in_i	=> wave_in_i,
+		wave_in_q	=> wave_in_q,
+		wave_out_i	=> wave_out_i,
+		wave_out_q	=> wave_out_q,
+		out_valid	=> out_valid,
+		debug_out	=> mix_debug_out
+	);
+
+	rfgen1: nco 
+	GENERIC MAP
+	(
+		nbits_wave		=> nbits_wave_in,
+		nbits_phase		=> nbits_phase
+	)
+	PORT MAP
+	(
+		srst		=> srst,
+		clk			=> clk,
+		pacc_clr	=> rfgen_pacc_clr,
+		pacc_inc	=> rfgen_pacc_inc,
+		freq_in		=> rfgen_freq_in,
+		freq_load	=> rfgen_freq_load,
+		phase_in	=> rfgen_phase_in,
+		phase_load	=> rfgen_phase_load,
+		phase_out	=> open,
+		wave_out_i	=> rfgen_wave_out_i,
+		wave_out_q	=> rfgen_wave_out_q,
+		out_valid	=> rfgen_out_valid,
+		debug_out	=> rfgen_debug_out
+	);
+
+ 	tb_clk : PROCESS
+	BEGIN
+		clk <= not clk;
+		wait for PERIOD/2;
+	END PROCESS;
+
+	wave_in_i <= resize(0.25*rfgen_wave_out_i, wave_in_i, false, true);
+	wave_in_q <= to_sfixed(0.0, wave_in_q);
+
+	tb : PROCESS
+	file RESULT_FREQ:   text open write_mode is "freq.txt"; 
+	variable L:         line;
+
+	BEGIN
+
+		-- Wait 100 ns for global reset to finish
+		wait for 4*PERIOD;
+		srst <= '0';
+
+		fprint(RESULT_FREQ, L,"%s\n", REAL'image(f));
+
+		wait for 2*PERIOD;
+		-------------------------------------------
+		-- 1
+		phase_in <= to_unsigned(0,nbits_phase);
+		wait until rising_edge(clk);
+		phase_load <= '1';
+		wait until rising_edge(clk);
+		phase_load <= '0';
+		
+		freq_in <= to_unsigned(1411,nbits_phase);
+		wait until rising_edge(clk);
+		freq_load <= '1';
+		wait until rising_edge(clk);
+		freq_load <= '0';
+
+		wait for 2*PERIOD;
+		pacc_inc <= '1';
+		
+		wait for 2*PERIOD;
+		wait until rising_edge(clk);
+
+		wait for 40*PERIOD;
+		-------------------------------------------
+		freq_in <= to_unsigned(643,nbits_phase);
+		wait until rising_edge(clk);
+		freq_load <= '1';
+		wait until rising_edge(clk);
+		freq_load <= '0';
+
+		wait for 40*PERIOD;
+		-------------------------------------------
+		phase_in <= to_unsigned(800,nbits_phase);
+		wait until rising_edge(clk);
+		phase_load <= '1';
+		wait until rising_edge(clk);
+		phase_load <= '0';
+
+		wait for 20*PERIOD;
+		-------------------------------------------
+		phase_in <= to_unsigned(45072,nbits_phase);
+		wait until rising_edge(clk);
+		phase_load <= '1';
+		wait until rising_edge(clk);
+		phase_load <= '0';
+
+		wait for 20*PERIOD;
+		-------------------------------------------
+		phase_in <= to_unsigned(20593,nbits_phase);
+		wait until rising_edge(clk);
+		phase_load <= '1';
+		wait until rising_edge(clk);
+		phase_load <= '0';
+
+		-------------------------------------------
+		freq_in <= to_unsigned(freq_word,nbits_phase);
+		wait until rising_edge(clk);
+		freq_load <= '1';
+		wait until rising_edge(clk);
+		freq_load <= '0';
+	
+		wait for 20*PERIOD;
+		fileout_enable <= '1';
+
+		wait for 20000*PERIOD;
+		fileout_enable <= '0';
+
+		-------------------------------------------
+		-- Sweep
+		freq_word <= 100;
+		for i in 1 to 200 loop
+			wait for 20*PERIOD;
+			freq_word <= freq_word + dfreq_word;
+			
+			freq_in <= to_unsigned(freq_word,nbits_phase);
+			wait until rising_edge(clk);
+			freq_load <= '1';
+			wait until rising_edge(clk);
+			freq_load <= '0';
+	
+		end loop;
+		
+		pacc_inc <= '0';
+		wait for 20*PERIOD;
+		fileout_enable <= '0';
+		wait until rising_edge(clk);
+		pacc_clr <= '1';
+		wait until rising_edge(clk);
+		pacc_clr <= '0';
+		wait for 20*PERIOD;
+		pacc_inc <= '1';
+		wait for 20*PERIOD;
+		wait until rising_edge(clk);
+		pacc_clr <= '1';
+		wait until rising_edge(clk);
+		pacc_clr <= '0';
+		wait for 20*PERIOD;
+		pacc_inc <= '0';
+		wait for 20*PERIOD;
+		wait until rising_edge(clk);
+		pacc_inc <= '1';
+		wait until rising_edge(clk);
+		pacc_inc <= '0';
+		wait for 20*PERIOD;
+		wait until rising_edge(clk);
+		srst <= '1';
+		wait until rising_edge(clk);
+		srst <= '0';
+		freq_in <= to_unsigned(freq_word,nbits_phase);
+		wait until rising_edge(clk);
+		freq_load <= '1';
+		wait until rising_edge(clk);
+		freq_load <= '0';
+		
+		wait for 20*PERIOD;
+		pacc_inc <= '1';
+		wait for 20*PERIOD;
+		wait until rising_edge(clk);
+		srst <= '1';
+		wait until rising_edge(clk);
+		srst <= '0';
+		wait for 20*PERIOD;
+		pacc_inc <= '0';
+
+		wait for 20*PERIOD;
+
+		assert false report "Test finished" severity error;
+		wait; 
+	END PROCESS;
+	
+	
+	rfgen_ctrl : PROCESS
+
+	BEGIN
+			wait for 20*PERIOD;
+			wait until rising_edge(clk) and srst = '0';
+			rfgen_freq_in <= to_unsigned(rfgen_freq_word,nbits_phase);
+			wait until rising_edge(clk);
+			rfgen_freq_load <= '1';
+			wait until rising_edge(clk);
+			rfgen_freq_load <= '0';
+			
+			wait for 20*PERIOD;
+			rfgen_pacc_inc <= '1';
+	
+			wait for 20*PERIOD;
+
+		wait; 
+	END PROCESS;
+
+	tb_fo : PROCESS(clk, fileout_enable, out_valid)
+	file RESULT_Ii:      text open write_mode is "i_in.txt"; 
+	file RESULT_Qi:      text open write_mode is "q_in.txt"; 
+	file RESULT_Io:      text open write_mode is "i_out.txt"; 
+	file RESULT_Qo:      text open write_mode is "q_out.txt"; 
+	variable L:         line;
+
+	BEGIN
+		if rising_edge(clk) and fileout_enable = '1' and out_valid = '1' then
+			fprint(RESULT_Ii, L,"%s\n", REAL'image(rfgen_debug_out.i_ud));
+			fprint(RESULT_Qi, L,"%s\n", REAL'image(rfgen_debug_out.q_ud));
+			fprint(RESULT_Io, L,"%s\n", REAL'image(mix_debug_out.i_out));
+			fprint(RESULT_Qo, L,"%s\n", REAL'image(mix_debug_out.q_out));
+		end if;
+
+	END PROCESS;
+
+
+END;