- added clkgen for vga
Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@587 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -45,7 +45,9 @@ GENERIC
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(
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sys_freq : integer := 100E6;
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ddr_phaseshift : integer := 0;
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ddr_frequency_hz : integer := 100E6
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ddr_frequency_hz : integer := 100E6;
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tsvga : vga_timespec_t := ts_vga_800_600_72
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);
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PORT
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(
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@@ -305,7 +307,6 @@ ARCHITECTURE behavior OF mips_sys IS
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COMPONENT vga_frontend64
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GENERIC
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(
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sys_freq : integer;
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fifo_depth : integer;
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fifo_almost_full_thresh : natural;
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fifo_almost_empty_thresh : natural;
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@@ -342,7 +343,8 @@ ARCHITECTURE behavior OF mips_sys IS
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SDAT_O : out unsigned(31 downto 0);
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-- VGA signals
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vga_clk_out : out std_logic;
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vga_clk_in : in std_logic;
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vga_clk_ce : in std_logic;
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vga_red : out unsigned(7 downto 0);
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vga_green : out unsigned(7 downto 0);
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vga_blue : out unsigned(7 downto 0);
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@@ -354,11 +356,14 @@ ARCHITECTURE behavior OF mips_sys IS
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END COMPONENT;
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signal nmi : std_logic;
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signal rst : std_logic;
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signal clk : std_logic;
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signal eb : std_logic;
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signal clk270 : std_logic;
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signal clk270var : std_logic;
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signal sdram_clk_lock : std_logic;
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signal sdram_clk0 : std_logic;
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signal sdram_clk270 : std_logic;
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signal sdram_clk270var : std_logic;
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signal vga_clk : std_logic;
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signal vga_clk_prebuf : std_logic;
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signal vga_clk_lock : std_logic;
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signal rst_in : std_logic;
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signal int_timer : std_logic;
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signal int_uart0 : std_logic;
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@@ -391,6 +396,8 @@ ARCHITECTURE behavior OF mips_sys IS
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signal arb_gnt : unsigned (ARB_MAX_MASTER-1 downto 0);
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-- J-Bus signals
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signal CLK_O : std_logic;
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signal RST_O : std_logic;
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signal INT : unsigned(5 downto 0);
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signal MDAT_I : word_t;
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signal MDAT_O : word_t;
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@@ -512,7 +519,6 @@ BEGIN
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sys_error <= debug;
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nmi <= not sys_rst_n_in;
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rst_in <= not sys_rst_n_in and sys_btn(0) and sys_btn(2);
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rst <= not locked;
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sys_usb_rstn <= not gpo1(0);
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sys_flash_byten <= '1';
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ADDR_I_usb <= X"0000000" & "00" & ADDR_O(3 downto 2);
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@@ -522,11 +528,13 @@ BEGIN
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SEL_I_sdram <= "0000" & SEL_O;
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sys_flash_ac97_rstn <= ac97_rstn and flash_rstn;
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CLK_O <= sys_clk_in;
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RST_O <= not (sdram_clk_lock and vga_clk_lock);
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sys_flash_ssram_out:
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process(clk)
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process(CLK_O)
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begin
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if rising_edge(clk) then
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if rising_edge(CLK_O) then
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sys_flash_ssram_d <= (others => 'Z') after topad;
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sys_flash_ssram_oe_n <= '1';
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sys_flash_ssram_we_n <= '1';
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@@ -568,10 +576,10 @@ sys_flash_ssram_out:
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MDAT_I_vga <= SDAT_O_sdram(63 downto 32) & MDAT_I;
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arbiter_proc:
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process(clk)
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process(CLK_O)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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if rising_edge(CLK_O) then
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if RST_O = '1' then
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arb_gnt <= (others => '0');
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arb_idx <= 0;
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elsif arb_req(arb_idx) = '0' then
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@@ -588,9 +596,9 @@ arbiter_proc:
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end process;
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int_sample:
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process(clk)
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process(CLK_O)
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begin
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if rising_edge(clk) then
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if rising_edge(CLK_O) then
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INT <= int_timer & '0' & (gpo1(2) and INT_O_ac97) & (gpo1(1) and sys_usb_int) & (int_uart0 or int_uart1 or int_uart2) & sys_btn(4);
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end if;
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end process;
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@@ -715,8 +723,8 @@ inst_mips_top: mips_top
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debug => debug,
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eb => eb,
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nmi => nmi,
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RST_I => rst,
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CLK_I => clk,
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RST_I => RST_O,
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CLK_I => CLK_O,
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ACK_I => ACK_I_cpu,
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SRDY_I => SRDY_I_cpu,
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MRDY_O => MRDY_O_cpu,
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@@ -733,8 +741,8 @@ inst_mips_top: mips_top
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inst_rom_wb : rom_wb
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PORT MAP
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(
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CLK_I => clk,
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RST_I => rst,
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CLK_I => CLK_O,
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RST_I => RST_O,
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CYC_I => CYC_I_rom,
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STB_I => STB_O,
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ACK_O => ACK_O_rom,
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@@ -748,8 +756,8 @@ inst_rom_wb : rom_wb
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inst_lcd_port: lcd_port
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PORT MAP
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(
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clk => clk,
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rst => rst,
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clk => CLK_O,
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rst => RST_O,
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we => '0',
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din => X"00",
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dout => open,
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@@ -762,8 +770,8 @@ inst_lcd_port: lcd_port
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inst_gpio_wb : gpio_wb
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PORT MAP
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(
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CLK_I => clk,
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RST_I => rst,
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CLK_I => CLK_O,
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RST_I => RST_O,
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CYC_I => CYC_I_gpio,
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STB_I => STB_O,
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SEL_I => SEL_O,
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@@ -791,8 +799,8 @@ inst_flash_port : flash_port_wb
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)
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PORT MAP
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(
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CLK_I => clk,
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RST_I => rst,
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CLK_I => CLK_O,
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RST_I => RST_O,
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CYC_I => CYC_I_flash,
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STB_I => STB_O,
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WE_I => WE_O,
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@@ -824,8 +832,8 @@ inst_usb_port : async_port_wb
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)
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PORT MAP
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(
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CLK_I => clk,
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RST_I => rst,
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CLK_I => CLK_O,
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RST_I => RST_O,
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CYC_I => CYC_I_usb,
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STB_I => STB_O,
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WE_I => WE_O,
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@@ -849,8 +857,8 @@ inst_usb_port : async_port_wb
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inst_uart_wb_0 : uart_wb
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PORT MAP
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(
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CLK_I => clk,
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RST_I => rst,
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CLK_I => CLK_O,
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RST_I => RST_O,
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CYC_I => CYC_I_uart0,
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STB_I => STB_O,
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SEL_I => SEL_O,
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@@ -869,8 +877,8 @@ inst_uart_wb_0 : uart_wb
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inst_uart_wb_1 : uart_wb
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PORT MAP
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(
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CLK_I => clk,
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RST_I => rst,
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CLK_I => CLK_O,
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RST_I => RST_O,
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CYC_I => CYC_I_uart1,
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STB_I => STB_O,
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SEL_I => SEL_O,
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@@ -889,8 +897,8 @@ inst_uart_wb_1 : uart_wb
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inst_uart_wb_2 : uart_wb
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PORT MAP
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(
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CLK_I => clk,
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RST_I => rst,
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CLK_I => CLK_O,
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RST_I => RST_O,
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CYC_I => CYC_I_uart2,
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STB_I => STB_O,
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SEL_I => SEL_O,
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@@ -915,8 +923,8 @@ inst_ssram_port_wb : entity work.ssram_port_wb
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PORT MAP
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(
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-- J-Bus domain
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RST_I => rst,
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CLK_I => clk,
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RST_I => RST_O,
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CLK_I => CLK_O,
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CYC_I => CYC_I_ssram,
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STB_I => STB_O,
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SEL_I => SEL_O,
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@@ -948,6 +956,27 @@ inst_ssram_port_wb : entity work.ssram_port_wb
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ssram_bw_n => sys_ssram_bw_n
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);
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inst_clockgen : entity work.clockgen
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GENERIC MAP
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(
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clk_in_freq_hz => 100E6,
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clk0_out_phaseshift => 0,
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clk1_out_phaseshift => 0
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)
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PORT MAP
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(
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-- Clocks and Reset
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rst => rst_in, -- external async reset, low active
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clk_in => CLK_O, -- system clock (e.g. 100MHz), from board
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clk_fb_in => sys_sdr_clk_fb, -- feedback clock
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clk0_0_out => sdram_clk0, -- System clock #0, dcm#0 output 0°
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clk0_270_out => sdram_clk270, -- System clock #0, dcm#0 output 270°
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clk1_0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
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clk1_270_out => sdram_clk270var, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
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locked_out => sdram_clk_lock, -- DCM locked status
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error_out => open
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);
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inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb
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GENERIC MAP
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(
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@@ -957,72 +986,74 @@ inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb
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)
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PORT MAP
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(
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RST_I => rst,
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CLK_I => clk,
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CLK270_I => clk270,
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CLK270VAR_I => clk270var,
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RST_I => RST_O,
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CLK_I => CLK_O,
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SDRAM_CLK0_I => sdram_clk0,
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SDRAM_CLK270_I => sdram_clk270,
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SDRAM_CLK270VAR_I => sdram_clk270var,
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CYC_I => CYC_I_sdram,
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STB_I => STB_O,
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SEL_I => SEL_I_sdram,
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WE_I => WE_O,
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ACK_O => ACK_O_sdram,
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MRDY_I => MRDY_O,
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SRDY_O => SRDY_O_sdram,
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ADDR_I => ADDR_O,
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DAT_I => SDAT_I_sdram,
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DAT_O => SDAT_O_sdram,
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CYC_I => CYC_I_sdram,
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STB_I => STB_O,
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SEL_I => SEL_I_sdram,
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WE_I => WE_O,
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ACK_O => ACK_O_sdram,
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MRDY_I => MRDY_O,
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SRDY_O => SRDY_O_sdram,
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ADDR_I => ADDR_O,
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DAT_I => SDAT_I_sdram,
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DAT_O => SDAT_O_sdram,
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-- SDRAM signals
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sd_clk_p => sys_sdr_clk_p,
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sd_clk_n => sys_sdr_clk_n,
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sd_cke => sys_sdr_cke_q,
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sd_cs_n => sys_sdr_cs_qn,
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sd_cas_n => sys_sdr_cas_qn,
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sd_ras_n => sys_sdr_ras_qn,
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sd_we_n => sys_sdr_we_qn,
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sd_addr => sys_sdr_a_q,
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sd_ba => sys_sdr_ba_q,
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sd_dm => sys_sdr_dm_q,
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sd_dqs => sys_sdr_dqs_q,
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sd_data => sys_sdr_data
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sd_clk_p => sys_sdr_clk_p,
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sd_clk_n => sys_sdr_clk_n,
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sd_cke => sys_sdr_cke_q,
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sd_cs_n => sys_sdr_cs_qn,
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sd_cas_n => sys_sdr_cas_qn,
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sd_ras_n => sys_sdr_ras_qn,
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sd_we_n => sys_sdr_we_qn,
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sd_addr => sys_sdr_a_q,
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sd_ba => sys_sdr_ba_q,
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sd_dm => sys_sdr_dm_q,
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sd_dqs => sys_sdr_dqs_q,
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sd_data => sys_sdr_data
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);
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inst_clockgen : entity work.clockgen
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inst_clkgen: entity work.clkgen
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GENERIC MAP
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(
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sys1_phaseshift => 0,
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frequency_hz => 100E6
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)
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PORT MAP
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clk_in_freq_hz => sys_freq,
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clk_out_freq_hz => tsvga.f_pxl_clk
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)
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PORT MAP
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(
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-- Clocks and Reset
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rst => rst_in, -- external async reset, low active
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clk_in => sys_clk_in, -- system clock (e.g. 100MHz), from board
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clk_fb_in => sys_sdr_clk_fb, -- feedback clock
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sys1_clk0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
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sys1_clk270_out => clk270var, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
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sys0_clk0_out => clk, -- System clock #0, dcm#0 output 0°
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sys0_clk270_out => clk270, -- System clock #0, dcm#0 output 270°
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locked_out => locked, -- DCM locked status
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error_out => open
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rst => rst_in,
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clk_in => CLK_O,
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clk_out => vga_clk_prebuf,
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locked => vga_clk_lock
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);
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BUFG_out_clk : BUFG
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port map
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(
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O => vga_clk, -- Clock buffer output
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I => vga_clk_prebuf -- Clock buffer input
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);
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inst_vga_frontend : vga_frontend64
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GENERIC MAP
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(
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sys_freq => 100E6,
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fifo_depth => 2048,
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fifo_almost_full_thresh => 1860,
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fifo_almost_empty_thresh => 256,
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tsvga => ts_vga_testbench
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tsvga => tsvga
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)
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PORT MAP
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(
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-- System signals
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RST_I => rst,
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CLK_I => clk,
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RST_I => RST_O,
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CLK_I => CLK_O,
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-- JBUS Master signals
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CYC_O => CYC_O_vga,
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@@ -1049,7 +1080,8 @@ inst_vga_frontend : vga_frontend64
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SDAT_O => SDAT_O_vga,
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-- VGA signals
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vga_clk_out => sys_vga_clk,
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vga_clk_in => vga_clk,
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vga_clk_ce => vga_clk_lock,
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vga_red => sys_vga_red,
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vga_green => sys_vga_green,
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vga_blue => sys_vga_blue,
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@@ -1067,8 +1099,8 @@ inst_ac97_wb : entity work.ac97_wb
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PORT MAP
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(
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-- J-Bus domain
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CLK_I => clk,
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RST_I => rst,
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CLK_I => CLK_O,
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RST_I => RST_O,
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CYC_I => CYC_I_ac97,
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STB_I => STB_O,
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WE_I => WE_O,
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