- use now non-debug-versions (NCO, MIX) for TB
git-svn-id: http://moon:8086/svn/vhdl/trunk@155 cc03376c-175c-47c8-b038-4cd826a8556b
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@@ -8,12 +8,12 @@ vcom -explicit -93 "../../cordic/src/cordic_pipe_pre.vhd"
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vcom -explicit -93 "../../cordic/src/cordic_pipe_post.vhd"
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vcom -explicit -93 "../../cordic/src/cordic_pipe_top.vhd"
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vcom -explicit -93 "../src/nco_pkg.vhd"
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vcom -explicit -93 "../src/nco_cordic_dbg.vhd"
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vcom -explicit -93 "../src/mix_cordic_dbg.vhd"
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vcom -explicit -93 "../src/nco_cordic.vhd"
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vcom -explicit -93 "../src/mix_cordic.vhd"
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vcom -explicit -93 "../src/tb_mix_cordic.vhd"
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vsim -t 1ps -lib work tb_mix
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do {tb_mix_cordic.wdo}
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view wave
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view structure
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view signals
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run 250us
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run 400us
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@@ -57,8 +57,7 @@ ARCHITECTURE behavior OF tb_mix IS
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wave_in_q : in sfixed;
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wave_out_i : out sfixed;
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wave_out_q : out sfixed;
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out_valid : out std_logic;
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debug_out : out debug_mix_out_t
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out_valid : out std_logic
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);
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END COMPONENT;
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@@ -82,16 +81,15 @@ ARCHITECTURE behavior OF tb_mix IS
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phase_out : out unsigned(nbits_phase-1 downto 0);
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wave_out_i : out sfixed;
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wave_out_q : out sfixed;
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out_valid : out std_logic;
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debug_out : out debug_out_t
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out_valid : out std_logic
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);
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END COMPONENT;
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--Constants
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constant f : REAL := 9.125E6;
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constant frf : REAL := 10.875E6;
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constant df : REAL := 10.0E3;
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constant fa : REAL := 100.0E6;
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constant frf : REAL := 3.333E5;
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constant flo : REAL := 3.333E5;
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constant df : REAL := 10.0E3;
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constant PERIOD : time := 10 ns;
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constant num_steps : integer := 1000000;
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@@ -99,7 +97,7 @@ ARCHITECTURE behavior OF tb_mix IS
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constant nbits_wave_out_frac : integer := nbits_wave_out-2;
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SIGNAL rfgen_freq_word : integer := integer(frf/fa*2.0**nbits_phase);
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SIGNAL freq_word : integer := integer(f/fa*2.0**nbits_phase);
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SIGNAL freq_word : integer := integer(flo/fa*2.0**nbits_phase);
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SIGNAL dfreq_word : integer := integer(df/fa*2.0**nbits_phase);
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--Inputs
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@@ -117,8 +115,7 @@ ARCHITECTURE behavior OF tb_mix IS
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SIGNAL wave_in_q : sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac));
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SIGNAL wave_out_i : sfixed(shi(nbits_wave_out, nbits_wave_out_frac) downto slo(nbits_wave_out, nbits_wave_out_frac));
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SIGNAL wave_out_q : sfixed(shi(nbits_wave_out, nbits_wave_out_frac) downto slo(nbits_wave_out, nbits_wave_out_frac));
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SIGNAL out_valid : std_logic;
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SIGNAL mix_debug_out : debug_mix_out_t;
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SIGNAL mix_out_valid : std_logic;
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SIGNAL rfgen_pacc_clr : std_logic := '0';
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SIGNAL rfgen_pacc_inc : std_logic := '0';
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@@ -128,10 +125,9 @@ ARCHITECTURE behavior OF tb_mix IS
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SIGNAL rfgen_phase_in : unsigned(nbits_phase-1 downto 0);
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--Outputs
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SIGNAL rfgen_wave_out_i : sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac));
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SIGNAL rfgen_wave_out_q : sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac));
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SIGNAL rfgen_out_i : sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac));
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SIGNAL rfgen_out_q : sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac));
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SIGNAL rfgen_out_valid : std_logic;
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SIGNAL rfgen_debug_out : debug_out_t;
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SIGNAL fileout_enable : std_logic := '0';
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BEGIN
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@@ -160,8 +156,7 @@ BEGIN
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wave_in_q => wave_in_q,
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wave_out_i => wave_out_i,
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wave_out_q => wave_out_q,
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out_valid => out_valid,
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debug_out => mix_debug_out
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out_valid => mix_out_valid
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);
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rfgen1: nco
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@@ -182,10 +177,9 @@ BEGIN
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phase_in => rfgen_phase_in,
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phase_load => rfgen_phase_load,
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phase_out => open,
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wave_out_i => rfgen_wave_out_i,
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wave_out_q => rfgen_wave_out_q,
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out_valid => rfgen_out_valid,
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debug_out => rfgen_debug_out
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wave_out_i => rfgen_out_i,
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wave_out_q => rfgen_out_q,
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out_valid => rfgen_out_valid
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);
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tb_clk : PROCESS
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@@ -194,8 +188,8 @@ BEGIN
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wait for PERIOD/2;
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END PROCESS;
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-- wave_in_i <= resize(1.0*rfgen_wave_out_i, wave_in_i, false, true);
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wave_in_i <= rfgen_wave_out_i;
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-- wave_in_i <= resize(1.0*rfgen_out_i, wave_in_i, false, true);
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wave_in_i <= rfgen_out_i;
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wave_in_q <= to_sfixed(0.0, wave_in_q);
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tb : PROCESS
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@@ -208,7 +202,7 @@ BEGIN
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wait for 4*PERIOD;
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srst <= '0';
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fprint(RESULT_FREQ, L,"%s\n", REAL'image(f));
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fprint(RESULT_FREQ, L,"%s\n", REAL'image(flo));
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wait for 2*PERIOD;
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-------------------------------------------
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@@ -273,7 +267,7 @@ BEGIN
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wait for 20*PERIOD;
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fileout_enable <= '1';
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wait for 20000*PERIOD;
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wait for 200000*PERIOD;
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fileout_enable <= '0';
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-------------------------------------------
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@@ -359,7 +353,7 @@ BEGIN
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wait;
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END PROCESS;
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tb_fo : PROCESS(clk, fileout_enable, out_valid)
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tb_fo : PROCESS(clk, fileout_enable, mix_out_valid)
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file RESULT_Ii: text open write_mode is "i_in.txt";
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file RESULT_Qi: text open write_mode is "q_in.txt";
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file RESULT_Io: text open write_mode is "i_out.txt";
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@@ -367,11 +361,15 @@ BEGIN
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variable L: line;
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BEGIN
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if rising_edge(clk) and fileout_enable = '1' and out_valid = '1' then
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fprint(RESULT_Ii, L,"%s\n", REAL'image(rfgen_debug_out.i_ud));
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fprint(RESULT_Qi, L,"%s\n", REAL'image(rfgen_debug_out.q_ud));
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fprint(RESULT_Io, L,"%s\n", REAL'image(mix_debug_out.i_out));
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fprint(RESULT_Qo, L,"%s\n", REAL'image(mix_debug_out.q_out));
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if rising_edge(clk) and fileout_enable = '1' then
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if rfgen_out_valid = '1' then
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fprint(RESULT_Ii, L,"%s\n", REAL'image(to_real(rfgen_out_i)));
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fprint(RESULT_Qi, L,"%s\n", REAL'image(to_real(rfgen_out_q)));
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end if;
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if mix_out_valid = '1' then
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fprint(RESULT_Io, L,"%s\n", REAL'image(to_real(wave_out_i)));
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fprint(RESULT_Qo, L,"%s\n", REAL'image(to_real(wave_out_q)));
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end if;
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end if;
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END PROCESS;
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