jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

- Cleaned up

Browse Source 
git-svn-id: http://moon:8086/svn/vhdl/trunk@101 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2008-10-24 20:56:13 +00:00
parent 48c7618752
commit b81ce94c39
2 changed files with 10 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/FIFO/src/fifo_sync.vhd
+6 -4
View File
@@ -29,7 +29,8 @@ USE IEEE.NUMERIC_STD.ALL;
use work.fifo_ctrl_pkg.all;
entity fifo_sync is
Generic (
Generic
(
addr_width : natural := 4;
data_width : natural := 8;
almost_full_thresh : integer := 12;
@@ -72,7 +73,7 @@ begin
fifo_afull <= almost_full;
fifo_aempty <= almost_empty;
inst_sync_fifo_ctrl: entity work.sync_fifo_ctrl
inst_sync_fifo_ctrl: entity work.sync_fifo_ctrl
GENERIC MAP
(
addr_width => addr_width,
@@ -96,8 +97,9 @@ begin
);
inst_dpram_1w1r: entity work.dpram_1w1r
GENERIC MAP (
inst_dpram_1w1r: entity work.dpram_1w1r
GENERIC MAP
(
addr_width => addr_width,
data_width => data_width
)
lib/VGA_ctrl/src/tb_vga_frontend.vhd
+4 -4
View File
@@ -160,7 +160,7 @@ STIMULUS: process
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
DAT_O <= X"0000_0000";
SDAT_I <= X"0000_0000";
ADDR_O <= X"0000_0008";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
@@ -168,7 +168,7 @@ STIMULUS: process
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
DAT_O <= X"0000_0000";
SDAT_I <= X"0000_0000";
ADDR_O <= X"0000_0010";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
@@ -176,7 +176,7 @@ STIMULUS: process
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
DAT_O <= X"0000_0035";
SDAT_I <= X"0000_0035";
ADDR_O <= X"0000_0004";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
@@ -184,7 +184,7 @@ STIMULUS: process
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
DAT_O <= X"0000_0035";
SDAT_I <= X"0000_0035";
ADDR_O <= X"0000_0020";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';