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- changed TIMESPEC for VGA

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- added TIMESPEC  for SDRAM
- SDRAM_CLK is now unrelated to SYS_CLK
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git-svn-id: http://moon:8086/svn/vhdl/trunk@591 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-11-03 22:52:50 +00:00
parent bfed7a6680
commit 643a506496
1 changed files with 9 additions and 5 deletions
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projects/mips_sys/ise101/mips_sys/ucf/systest.ucf
+9 -5
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@@ -20,19 +20,23 @@
CONFIG STEPPING = "ES";
# Bus clock nets
NET "clk" TNM_NET = "clk";
TIMESPEC "TS_clk" = PERIOD "clk" 9.9 ns HIGH 50 %;
NET "sys_clk_in" TNM_NET = "sys_clk";
TIMESPEC "TS_clk" = PERIOD "sys_clk" 9.9 ns HIGH 50 %;
NET "inst_vga_frontend/inst_vga_backend/inst_clkgen/vga_clk0" TNM_NET = "vga_clk";
NET "sdram_clk0" TNM_NET = "sdram_clk";
TIMESPEC "TS_sdram_clk" = PERIOD "sdram_clk" 9.9 ns HIGH 50 %;
TIMESPEC "TS_unrelate_SDRAM" = FROM sys_clk TO sdram_clk TIG;
NET "vga_clk" TNM_NET = "vga_clk";
#TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 7.5 ns HIGH 50 %;
TIMESPEC TS_unrelate = FROM clk TO vga_clk TIG;
TIMESPEC "TS_unrelate_VGA" = FROM sys_clk TO vga_clk TIG;
NET "sys_clk_in" LOC = "AE14";
NET sys_clk_in IOSTANDARD = LVCMOS33;
NET "sys_rst_n_in" LOC = "D6";
NET sys_rst_n_in PULLUP;
NET "sys_rst_n_in" TIG;
NET "rst" TIG;
NET "RST_O" TIG;
NET "sys_clk_in" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "inst_clockgen/inst_DCM_BASE_0.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE;