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- changed frequencies into MHz units (real data type)

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Committed on the Free edition of March Hare Software CVSNT Server.
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git-svn-id: http://moon:8086/svn/vhdl/trunk@734 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-02-09 07:50:27 +00:00
parent 385aa5e008
commit 0c50e933f8
19 changed files with 161 additions and 144 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd
+7 -7
View File
@@ -31,8 +31,8 @@ use work.sdram_types.all;
entity sdram_cmd is
Generic
(
f_sdrclk_hz : natural := 100E6;
BL : natural := 2
f_sdrclk : real := 100.0;
BL : natural := 2
);
Port
(
@@ -73,13 +73,13 @@ architecture behaviour of sdram_cmd is
( SD_DESELECT => (0 ),
SD_NOP => (0 ),
SD_LMR => (TMRD-1 ),
SD_ACT => (to_cycles(TRCD, f_sdrclk_hz)-1),
SD_ACT => (to_cycles(TRCD, f_sdrclk)-1),
SD_READ => (TCAS-1 ),
SD_WRITE => (to_cycles(TWR, f_sdrclk_hz)-1),
SD_PRE => (to_cycles(TRP, f_sdrclk_hz)-1),
SD_WRITE => (to_cycles(TWR, f_sdrclk)-1),
SD_PRE => (to_cycles(TRP, f_sdrclk)-1),
SD_BST => (0 ),
SD_AR => (to_cycles(TRFC, f_sdrclk_hz)-1),
SD_SR => (to_cycles(TRFC, f_sdrclk_hz)-1)
SD_AR => (to_cycles(TRFC, f_sdrclk)-1),
SD_SR => (to_cycles(TRFC, f_sdrclk)-1)
);
begin
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd
+4 -4
View File
@@ -32,8 +32,8 @@ use work.utils_pkg.all;
entity sdram_ctrl is
Generic
(
f_sysclk_hz : natural := 100E6;
BL : natural := 2
f_sysclk : real := 100.0;
BL : natural := 2
);
Port (
rst : in STD_LOGIC;
@@ -60,7 +60,7 @@ architecture behaviour of sdram_ctrl is
type ctrl_state_t is (RESET, POWER_WAIT, INIT, INIT_WAIT, USER_READY, USER_WRITE_PRE, USER_WRITE_ACT, USER_WRITE, USER_READ_PRE, USER_READ_ACT, USER_READ, REFRESH_PRE, REFRESH);
signal st_ctrl, st_ctrl_next : ctrl_state_t;
constant PWR_UP_CLOCK_INTERVAL : natural := to_cycles(PWR_UP_WAIT, f_sysclk_hz);
constant PWR_UP_CLOCK_INTERVAL : natural := to_cycles(PWR_UP_WAIT, f_sysclk);
signal pwr_up_cnt : natural range 0 to PWR_UP_CLOCK_INTERVAL-1;
signal pwr_up_cnt_rst : std_logic;
signal pwr_up_finished : std_logic;
@@ -74,7 +74,7 @@ architecture behaviour of sdram_ctrl is
signal seq_rst_en : std_logic;
signal seq_cnt_en : std_logic;
constant REFRESH_CLOCK_INTERVAL : natural := to_cycles(REFRESH_INTERVAL, f_sysclk_hz);
constant REFRESH_CLOCK_INTERVAL : natural := to_cycles(REFRESH_INTERVAL, f_sysclk);
signal refresh_cnt : natural range 0 to REFRESH_CLOCK_INTERVAL-1;
signal refresh_request : std_logic;
signal refresh_cnt_rst : std_logic;
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd
+6 -6
View File
@@ -32,10 +32,10 @@ use work.sdram_types.all;
entity sdram_ctrl_frontend64_wb is
Generic
(
BL : natural := 2;
f_sysclk_hz : natural := 100E6;
f_sdrclk_hz : natural := 100E6;
fifo_depth : integer := 4
BL : natural := 2;
f_sysclk : real := 100.0;
f_sdrclk : real := 100.0;
fifo_depth : integer := 4
);
Port
(
@@ -205,8 +205,8 @@ begin
Generic map
(
BL => BL,
f_sysclk_hz => f_sysclk_hz,
f_sdrclk_hz => f_sdrclk_hz,
f_sysclk => f_sysclk,
f_sdrclk => f_sdrclk,
fifo_depth => fifo_depth
)
Port map
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd
+5 -5
View File
@@ -32,9 +32,9 @@ use work.sdram_types.all;
entity sdram_ctrl_frontend_wb is
Generic
(
BL : natural := 2;
f_sysclk_hz : natural := 100E6;
f_sdrclk_hz : natural := 100E6;
BL : natural := 2;
f_sysclk : real := 100.0;
f_sdrclk : real := 100.0;
fifo_depth : integer := 4
);
Port
@@ -205,8 +205,8 @@ begin
Generic map
(
BL => BL,
f_sysclk_hz => f_sysclk_hz,
f_sdrclk_hz => f_sdrclk_hz,
f_sysclk => f_sysclk,
f_sdrclk => f_sdrclk,
fifo_depth => fifo_depth
)
Port map
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd
+5 -5
View File
@@ -31,9 +31,9 @@ use work.sdram_types.all;
entity sdram_ctrl_top is
Generic
(
BL : natural := 2;
f_sysclk_hz : natural := 100E6;
f_sdrclk_hz : natural := 100E6;
BL : natural := 2;
f_sysclk : real := 100.0;
f_sdrclk : real := 100.0;
fifo_depth : natural := 3
);
Port
@@ -133,7 +133,7 @@ begin
inst_sdram_ctrl : entity work.sdram_ctrl
Generic map
(
f_sysclk_hz => f_sysclk_hz,
f_sysclk => f_sysclk,
BL => BL
)
Port map
@@ -180,7 +180,7 @@ begin
inst_sdram_cmd : entity work.sdram_cmd
Generic map
(
f_sdrclk_hz => f_sdrclk_hz,
f_sdrclk => f_sdrclk,
BL => BL
)
Port map
lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd
+3 -3
View File
@@ -113,16 +113,16 @@ package sdram_types is
wait_cycle : natural;
end record init_seq_t;
function to_cycles(T_ns : real; f_hz : natural) return natural;
function to_cycles(T_ns : real; f_Mhz : real) return natural;
end sdram_types;
package body sdram_types is
function to_cycles(T_ns : real; f_hz : natural) return natural is
function to_cycles(T_ns : real; f_Mhz : real) return natural is
begin
return natural(0.5 + 1.0E-9*T_ns*real(f_hz));
return natural(0.5 + 1.0E-3*T_ns*f_Mhz);
end to_cycles;
lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend64_wb.vhd
+3 -3
View File
@@ -122,7 +122,7 @@ begin
inst_clockgen : entity work.clockgen
GENERIC MAP
(
clk_in_freq_hz => 100E6,
clk_in_freq => 100.0,
clk0_out_phaseshift => 0,
clk1_out_phaseshift => 0
)
@@ -151,8 +151,8 @@ inst_clockgen : entity work.clockgen
GENERIC MAP
(
BL => BURST_LEN,
f_sysclk_hz => 100E6,
f_sdrclk_hz => 133E6,
f_sysclk => 100.000,
f_sdrclk => 133.333,
fifo_depth => 4
)
PORT MAP
lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd
+3 -3
View File
@@ -119,7 +119,7 @@ begin
inst_clockgen : entity work.clockgen
GENERIC MAP
(
clk_in_freq_hz => 100E6,
clk_in_freq => 100.0,
clk0_out_phaseshift => 0,
clk1_out_phaseshift => 0
)
@@ -146,8 +146,8 @@ inst_clockgen : entity work.clockgen
GENERIC MAP
(
BL => BURST_LEN,
f_sysclk_hz => 100E6,
f_sdrclk_hz => 100E6,
f_sysclk => 100.0,
f_sdrclk => 100.0,
fifo_depth => 4
)
PORT MAP
lib/VGA_ctrl/src/clkgen_virtex4.vhd
+5 -5
View File
@@ -32,8 +32,8 @@ use UNISIM.vcomponents.all;
entity clkgen is
Generic
(
clk_in_freq_hz : integer := 100E6;
clk_out_freq_hz : integer := 100E6
clk_in_freq : real := 100.0;
clk_out_freq : real := 100.0
);
Port
(
@@ -57,10 +57,10 @@ architecture tech of clkgen is
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => UTILS_FREQ_D(clk_in_freq_hz, clk_out_freq_hz), -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => UTILS_FREQ_M(clk_in_freq_hz, clk_out_freq_hz), -- Can be any integer from 2 to 32
CLKFX_DIVIDE => UTILS_FREQ_D(clk_in_freq, clk_out_freq), -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => UTILS_FREQ_M(clk_in_freq, clk_out_freq), -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq_hz), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
lib/misc/async_port_wb.vhd
+21 -21
View File
@@ -1,5 +1,5 @@
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.14 2010-02-07 15:42:47 Jens Exp $
-- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.15 2010-02-09 07:46:19 Jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
@@ -10,10 +10,10 @@ use work.async_types.all;
entity async_port_wb is
Generic
(
f_sysclk_hz : natural := 100E6;
addr_width : natural := 32;
data_width : natural := 32;
byte_sel_width : natural := 4;
f_sysclk : real := 100.0;
addr_width : natural := 32;
data_width : natural := 32;
byte_sel_width : natural := 4;
async_timespec : async_timespec_t
);
Port
@@ -73,9 +73,9 @@ architecture Behavioral of async_port_wb is
------------------------------------------------------------------
begin
ASSERT to_cycles(async_timespec.T_pulse_rd, f_sysclk_hz) > 0 report "Read pulse length must be greater than zero!" severity failure;
ASSERT to_cycles(async_timespec.T_pulse_wr, f_sysclk_hz) > 0 report "Write pulse length must be greater than zero!" severity failure;
ASSERT (not async_timespec.can_page_rd OR (to_cycles(async_timespec.T_pulse_page_rd, f_sysclk_hz) > 1)) report "Read page pulse length must be greater than one!" severity failure;
ASSERT to_cycles(async_timespec.T_pulse_rd, f_sysclk) > 0 report "Read pulse length must be greater than zero!" severity failure;
ASSERT to_cycles(async_timespec.T_pulse_wr, f_sysclk) > 0 report "Write pulse length must be greater than zero!" severity failure;
ASSERT (not async_timespec.can_page_rd OR (to_cycles(async_timespec.T_pulse_page_rd, f_sysclk) > 1)) report "Read page pulse length must be greater than one!" severity failure;
SRDY_O <= CYC_I and rdyo;
en <= CYC_I and STB_I;
@@ -111,7 +111,7 @@ architecture Behavioral of async_port_wb is
process(s, cycle_cnt, en, WE_I, WE_I_r, do_page_read)
begin
cycle_reload <= to_cycles(async_timespec.T_pulse_rst, f_sysclk_hz);
cycle_reload <= to_cycles(async_timespec.T_pulse_rst, f_sysclk);
cc_rst <= '0';
as.rst <= '0';
as.cs <= '0';
@@ -139,17 +139,17 @@ architecture Behavioral of async_port_wb is
if en = '1' then
as.cs <= '1';
cc_rst <= '1';
if to_cycles(async_timespec.T_leadin, f_sysclk_hz) = 0 then
if to_cycles(async_timespec.T_leadin, f_sysclk) = 0 then
sn <= pulse;
if WE_I = '1' then
cycle_reload <= 0;
sn <= leadin; -- always lead-in for writes
else
cycle_reload <= to_cycles(async_timespec.T_pulse_rd, f_sysclk_hz) - 1;
cycle_reload <= to_cycles(async_timespec.T_pulse_rd, f_sysclk) - 1;
as.rd <= '1';
end if;
else
cycle_reload <= to_cycles(async_timespec.T_leadin, f_sysclk_hz) - 1;
cycle_reload <= to_cycles(async_timespec.T_leadin, f_sysclk) - 1;
sn <= leadin;
end if;
end if;
@@ -163,9 +163,9 @@ architecture Behavioral of async_port_wb is
cc_rst <= '1';
sn <= pulse;
if WE_I_r = '1' then
cycle_reload <= to_cycles(async_timespec.T_pulse_wr, f_sysclk_hz) - 1;
cycle_reload <= to_cycles(async_timespec.T_pulse_wr, f_sysclk) - 1;
else
cycle_reload <= to_cycles(async_timespec.T_pulse_rd, f_sysclk_hz) - 1;
cycle_reload <= to_cycles(async_timespec.T_pulse_rd, f_sysclk) - 1;
end if;
end if;
@@ -180,17 +180,17 @@ architecture Behavioral of async_port_wb is
ack <= not WE_I_r;
rdy <= do_page_read;
if en = '1' and do_page_read = '1' then
cycle_reload <= to_cycles(async_timespec.T_pulse_page_rd, f_sysclk_hz) - 1;
cycle_reload <= to_cycles(async_timespec.T_pulse_page_rd, f_sysclk) - 1;
sn <= pulse;
elsif to_cycles(async_timespec.T_leadout, f_sysclk_hz) = 0 then
if to_cycles(async_timespec.T_release, f_sysclk_hz) = 0 then
elsif to_cycles(async_timespec.T_leadout, f_sysclk) = 0 then
if to_cycles(async_timespec.T_release, f_sysclk) = 0 then
sn <= idle;
else
cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk_hz) - 1;
cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk) - 1;
sn <= release;
end if;
else
cycle_reload <= to_cycles(async_timespec.T_leadout, f_sysclk_hz) - 1;
cycle_reload <= to_cycles(async_timespec.T_leadout, f_sysclk) - 1;
sn <= leadout;
end if;
end if;
@@ -200,10 +200,10 @@ architecture Behavioral of async_port_wb is
as.drive_d <= WE_I_r;
if cycle_cnt = 0 then
cc_rst <= '1';
if to_cycles(async_timespec.T_release, f_sysclk_hz) = 0 then
if to_cycles(async_timespec.T_release, f_sysclk) = 0 then
sn <= idle;
else
cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk_hz) - 1;
cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk) - 1;
sn <= release;
end if;
end if;
lib/misc/async_types.vhd
+3 -3
View File
@@ -44,16 +44,16 @@ package async_types is
pol_rst : std_logic;
end record;
function to_cycles(T_ns : real; f_hz : natural) return natural;
function to_cycles(T_ns : real; f_Mhz : real) return natural;
end async_types;
package body async_types is
function to_cycles(T_ns : real; f_hz : natural) return natural is
function to_cycles(T_ns : real; f_Mhz : real) return natural is
begin
return natural(0.5 + 1.0E-9*T_ns*real(f_hz));
return natural(0.5 + 1.0E-3*T_ns*f_Mhz);
end to_cycles;
end async_types;
lib/misc/clockgen_virtex4.vhd
+5 -5
View File
@@ -33,9 +33,9 @@ use UNISIM.vcomponents.all;
entity clockgen is
generic
(
clk_in_freq_hz : integer := 100E6;
clk0_out_phaseshift : integer := 0;
clk1_out_phaseshift : integer := 0
clk_in_freq : real := 100.0;
clk0_out_phaseshift : integer := 0;
clk1_out_phaseshift : integer := 0
);
port
(
@@ -114,7 +114,7 @@ inst_DCM_BASE_0 : DCM_BASE
CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq_hz), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
@@ -150,7 +150,7 @@ inst_DCM_BASE_0 : DCM_BASE
CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq_hz), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
lib/misc/gpio_wb.vhd
+2 -2
View File
@@ -5,7 +5,7 @@ USE IEEE.NUMERIC_STD.ALL;
ENTITY gpio_wb IS
Generic
(
f_sysclk_hz : natural := 100E6
f_sysclk : real := 100.0
);
Port
(
@@ -34,7 +34,7 @@ END gpio_wb;
ARCHITECTURE behavior OF gpio_wb IS
constant num_timers : natural := 2;
constant ncycles_usec : natural := f_sysclk_hz/1E6;
constant ncycles_usec : natural := natural(f_sysclk + 0.5);
signal gpo0_reg : unsigned(31 downto 0);
signal gpo1_reg : unsigned(31 downto 0);
lib/misc/utils_pkg.vhd
+19 -19
View File
@@ -1,5 +1,5 @@
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/utils_pkg.vhd,v 1.3 2009-11-03 20:38:30 Jens Exp $
-- $Header: /tmp/cvsroot/VHDL/lib/misc/utils_pkg.vhd,v 1.4 2010-02-09 07:46:19 Jens Exp $
-----------------------------------------------------------------------
library IEEE;
@@ -18,9 +18,9 @@ package utils_pkg is
function NextExpBaseTwo(x : natural) return natural;
function GCD(a, b : natural) return natural;
function LCM(a, b : natural) return natural;
function UTILS_PERIOD_NS(f_in_hz : natural) return real;
function UTILS_FREQ_M(f_in_hz, f_out_hz : natural) return natural;
function UTILS_FREQ_D(f_in_hz, f_out_hz : natural) return natural;
function UTILS_PERIOD_NS(f_in_MHz : real) return real;
function UTILS_FREQ_M(f_in_MHz, f_out_MHz : real) return natural;
function UTILS_FREQ_D(f_in_MHz, f_out_MHz : real) return natural;
end utils_pkg;
@@ -74,21 +74,21 @@ package body utils_pkg is
end LCM;
function UTILS_PERIOD_NS(f_in_hz : natural) return real is
function UTILS_PERIOD_NS(f_in_MHz : real) return real is
begin
return 1.0E9/real(f_in_hz);
return 1.0E3/f_in_MHz;
end UTILS_PERIOD_NS;
function UTILS_FREQ_M(f_in_hz, f_out_hz : natural) return natural is
variable f_in_mhz : natural;
variable f_out_mhz : natural;
function UTILS_FREQ_M(f_in_MHz, f_out_MHz : real) return natural is
variable f_in_hz : natural;
variable f_out_hz : natural;
variable m : natural;
begin
f_in_mhz := f_in_hz/1E6;
f_out_mhz := f_out_hz/1E6;
m := f_out_mhz/GCD(f_in_mhz, f_out_mhz);
f_in_hz := natural(f_in_MHz*1.0E6);
f_out_hz := natural(f_out_MHz*1.0E6);
m := f_out_hz/GCD(f_in_hz, f_out_hz);
if m = 1 then
m := 2;
@@ -98,16 +98,16 @@ package body utils_pkg is
end UTILS_FREQ_M;
function UTILS_FREQ_D(f_in_hz, f_out_hz : natural) return natural is
variable f_in_mhz : natural;
variable f_out_mhz : natural;
function UTILS_FREQ_D(f_in_MHz, f_out_MHz : real) return natural is
variable f_in_hz : natural;
variable f_out_hz : natural;
variable m : natural;
variable d : natural;
begin
m := UTILS_FREQ_M(f_in_hz, f_out_hz);
f_in_mhz := f_in_hz/1E6;
f_out_mhz := f_out_hz/1E6;
d := m*f_in_mhz/f_out_mhz;
m := UTILS_FREQ_M(f_in_MHz, f_out_MHz);
f_in_hz := natural(f_in_MHz*1.0E6);
f_out_hz := natural(f_out_MHz*1.0E6);
d := m*f_in_hz/f_out_hz;
return d;
lib/ps2_port/src/ps2_core.vhd
+2 -2
View File
@@ -29,7 +29,7 @@ USE IEEE.NUMERIC_STD.ALL;
entity ps2_core is
Generic
(
f_sys_clk_hz : integer := 100E6
f_sys_clk : real := 100.0
);
Port
(
@@ -69,7 +69,7 @@ type line_state_tx_t is (tx_idle_st, tx_clock_assert_st, tx_start_latency_st,
tx_ack_trans_st, tx_ack_sample_st, tx_valid_st);
-- Constant
constant prescaler_us : integer := f_sys_clk_hz/1E6;
constant prescaler_us : integer := integer(f_sys_clk + 0.5);
constant timeout_us : integer := 15000;
constant time_clock_assert : integer := 120;
constant time_clock_abort : integer := 500;
lib/ps2_port/src/ps2_wb.vhd
+2 -2
View File
@@ -5,7 +5,7 @@ USE IEEE.NUMERIC_STD.ALL;
ENTITY ps2_wb IS
Generic
(
f_sys_clk_hz : integer := 100E6
f_sys_clk : real := 100.0
);
Port
(
@@ -118,7 +118,7 @@ irq_register:
inst_ps2_core: entity work.ps2_core
GENERIC MAP
(
f_sys_clk_hz => f_sys_clk_hz
f_sys_clk => f_sys_clk
)
PORT MAP
(
projects/mips_sys/src/clockgen_virtex4.vhd
+11 -11
View File
@@ -33,9 +33,9 @@ use UNISIM.vcomponents.all;
entity clockgen is
generic
(
clk_in_freq_hz : integer := 100E6;
vga_clk_out_freq_hz : integer := 100E6;
sys_clk_out_freq_hz : integer := 100E6;
clk_in_freq : real := 100.0;
vga_clk_out_freq : real := 100.0;
sys_clk_out_freq : real := 100.0;
sdr0_clk_out_phaseshift : integer := 0;
sdr1_clk_out_phaseshift : integer := 0
);
@@ -93,10 +93,10 @@ begin
(
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => UTILS_FREQ_D(clk_in_freq_hz, vga_clk_out_freq_hz), -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => UTILS_FREQ_M(clk_in_freq_hz, vga_clk_out_freq_hz), -- Can be any integer from 2 to 32
CLKFX_DIVIDE => UTILS_FREQ_D(clk_in_freq, vga_clk_out_freq), -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => UTILS_FREQ_M(clk_in_freq, vga_clk_out_freq), -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq_hz), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
@@ -146,10 +146,10 @@ BUFG_vga_clkfx : BUFG
(
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => UTILS_FREQ_D(clk_in_freq_hz, sys_clk_out_freq_hz), -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => UTILS_FREQ_M(clk_in_freq_hz, sys_clk_out_freq_hz), -- Can be any integer from 2 to 32
CLKFX_DIVIDE => UTILS_FREQ_D(clk_in_freq, sys_clk_out_freq), -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => UTILS_FREQ_M(clk_in_freq, sys_clk_out_freq), -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq_hz), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
@@ -204,7 +204,7 @@ inst_DCM_SDRCLK_0 : DCM_BASE
CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => UTILS_PERIOD_NS(sys_clk_out_freq_hz), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKIN_PERIOD => UTILS_PERIOD_NS(sys_clk_out_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
@@ -256,7 +256,7 @@ bufg_sdr0_clk270: bufg
CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => UTILS_PERIOD_NS(sys_clk_out_freq_hz), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKIN_PERIOD => UTILS_PERIOD_NS(sys_clk_out_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
projects/mips_sys/src/mips_sys.vhd
+26 -17
View File
@@ -42,10 +42,10 @@ use work.async_defs.all;
ENTITY mips_sys IS
GENERIC
(
sys_freq_in : integer := 100E6;
sys_freq : integer := 100E6;
ddr_frequency_hz : integer := 100E6;
ddr_phaseshift : integer := 0;
sys_freq_in : real := 100.0;
sys_freq : real := 125.0;
sdram_freq : real := 125.0;
sdram_phaseshift : integer := 0;
tsvga : vga_timespec_t := ts_vga_800_600_60
);
@@ -195,10 +195,10 @@ ARCHITECTURE behavior OF mips_sys IS
COMPONENT async_port_wb
GENERIC
(
f_sysclk_hz : natural := 100E6;
addr_width : natural := 32;
data_width : natural := 32;
byte_sel_width : natural := 4;
f_sysclk : real := 100.0;
addr_width : natural := 32;
data_width : natural := 32;
byte_sel_width : natural := 4;
async_timespec : async_timespec_t
);
PORT
@@ -248,6 +248,10 @@ ARCHITECTURE behavior OF mips_sys IS
END COMPONENT;
COMPONENT gpio_wb
Generic
(
f_sysclk : real := 100.0
);
PORT
(
CLK_I : in STD_LOGIC;
@@ -464,6 +468,7 @@ ARCHITECTURE behavior OF mips_sys IS
-- DDR SDRAM
constant BURST_LEN : natural := 2;
constant vga_freq : real := real(tsvga.f_pxl_clk)/1.0E6;
-- attribute rom_style: string;
@@ -723,6 +728,10 @@ inst_lcd_port: lcd_port
);
inst_gpio_wb : gpio_wb
GENERIC MAP
(
f_sysclk => sys_freq
)
PORT MAP
(
CLK_I => CLK_O,
@@ -748,7 +757,7 @@ inst_gpio_wb : gpio_wb
inst_flash_port : async_port_wb
GENERIC MAP
(
f_sysclk_hz => sys_freq,
f_sysclk => sys_freq,
addr_width => 25,
data_width => 32,
byte_sel_width => 1,
@@ -781,7 +790,7 @@ inst_flash_port : async_port_wb
inst_usb_port : async_port_wb
GENERIC MAP
(
f_sysclk_hz => sys_freq,
f_sysclk => sys_freq,
addr_width => 4,
data_width => 16,
byte_sel_width => 1,
@@ -855,9 +864,9 @@ inst_uart_wb_1 : uart_wb
inst_clockgen : entity work.clockgen
GENERIC MAP
(
clk_in_freq_hz => sys_freq_in,
sys_clk_out_freq_hz => sys_freq,
vga_clk_out_freq_hz => tsvga.f_pxl_clk,
clk_in_freq => sys_freq_in,
sys_clk_out_freq => sys_freq,
vga_clk_out_freq => vga_freq,
sdr0_clk_out_phaseshift => 0,
sdr1_clk_out_phaseshift => 0
)
@@ -881,8 +890,8 @@ inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb
GENERIC MAP
(
BL => BURST_LEN,
f_sysclk_hz => sys_freq,
f_sdrclk_hz => ddr_frequency_hz,
f_sysclk => sys_freq,
f_sdrclk => sdram_freq,
fifo_depth => 5
)
PORT MAP
@@ -1004,7 +1013,7 @@ inst_ac97_wb : entity work.ac97_wb
inst_ps2_wb_0: entity work.ps2_wb
GENERIC MAP
(
f_sys_clk_hz => sys_freq
f_sys_clk => sys_freq
)
PORT MAP
(
@@ -1043,7 +1052,7 @@ inst_ps2_phy_0: entity work.ps2_phy
inst_ps2_wb_1: entity work.ps2_wb
GENERIC MAP
(
f_sys_clk_hz => sys_freq
f_sys_clk => sys_freq
)
PORT MAP
(
projects/mips_sys/src/mips_sys_sim.vhd
+29 -21
View File
@@ -43,10 +43,10 @@ use work.async_defs.all;
ENTITY mips_sys IS
GENERIC
(
sys_freq_in : integer := 100E6;
sys_freq : integer := 125E6;
ddr_frequency_hz : integer := 125E6;
ddr_phaseshift : integer := 0;
sys_freq_in : real := 100.0;
sys_freq : real := 125.0;
sdram_freq : real := 125.0;
sdram_phaseshift : integer := 0;
tsvga : vga_timespec_t := ts_vga_800_600_72
);
@@ -201,10 +201,10 @@ ARCHITECTURE behavior OF mips_sys IS
COMPONENT async_port_wb
GENERIC
(
f_sysclk_hz : natural := sys_freq;
addr_width : natural := 32;
data_width : natural := 32;
byte_sel_width : natural := 4;
f_sysclk : real := sys_freq;
addr_width : natural := 32;
data_width : natural := 32;
byte_sel_width : natural := 4;
async_timespec : async_timespec_t
);
PORT
@@ -235,9 +235,9 @@ ARCHITECTURE behavior OF mips_sys IS
COMPONENT flash_port_wb
GENERIC
(
f_sysclk_hz : natural := sys_freq;
addr_width : natural := 32;
data_width : natural := 32;
f_sysclk : real := sys_freq;
addr_width : natural := 32;
data_width : natural := 32;
async_timespec : async_timespec_t
);
PORT
@@ -288,6 +288,10 @@ ARCHITECTURE behavior OF mips_sys IS
END COMPONENT;
COMPONENT gpio_wb
Generic
(
f_sysclk : real := 100.0
);
PORT
(
CLK_I : in STD_LOGIC;
@@ -516,8 +520,8 @@ ARCHITECTURE behavior OF mips_sys IS
-- DDR SDRAM
constant BURST_LEN : natural := 2;
constant topad : time := 3 ns;
constant topad : time := 3 ns;
constant vga_freq : real := real(tsvga.f_pxl_clk)/1.0E6;
-- attribute rom_style: string;
-- attribute rom_style of cmd_fifo_dout: signal is "DISTRIBUTED";
@@ -785,6 +789,10 @@ inst_lcd_port: lcd_port
);
inst_gpio_wb : gpio_wb
GENERIC MAP
(
f_sysclk => sys_freq
)
PORT MAP
(
CLK_I => CLK_O,
@@ -810,7 +818,7 @@ inst_gpio_wb : gpio_wb
inst_flash_port : flash_port_wb
GENERIC MAP
(
f_sysclk_hz => sys_freq,
f_sysclk => sys_freq,
addr_width => 25,
data_width => 32,
async_timespec => ts_flash
@@ -843,7 +851,7 @@ inst_flash_port : flash_port_wb
inst_usb_port : async_port_wb
GENERIC MAP
(
f_sysclk_hz => sys_freq,
f_sysclk => sys_freq,
addr_width => 2,
data_width => 16,
byte_sel_width => 1,
@@ -978,9 +986,9 @@ inst_ssram_port_wb : entity work.ssram_port_wb
inst_clockgen : entity work.clockgen
GENERIC MAP
(
clk_in_freq_hz => sys_freq_in,
sys_clk_out_freq_hz => sys_freq,
vga_clk_out_freq_hz => tsvga.f_pxl_clk,
clk_in_freq => sys_freq_in,
sys_clk_out_freq => sys_freq,
vga_clk_out_freq => vga_freq,
sdr0_clk_out_phaseshift => 0,
sdr1_clk_out_phaseshift => 0
)
@@ -1005,8 +1013,8 @@ inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb
GENERIC MAP
(
BL => BURST_LEN,
f_sysclk_hz => sys_freq,
f_sdrclk_hz => ddr_frequency_hz,
f_sysclk => sys_freq,
f_sdrclk => sdram_freq,
fifo_depth => 5
)
PORT MAP
@@ -1127,7 +1135,7 @@ inst_ac97_wb : entity work.ac97_wb
inst_ps2_wb: entity work.ps2_wb
GENERIC MAP
(
f_sys_clk_hz => sys_freq
f_sys_clk => sys_freq
)
PORT MAP
(