- Intital revision
git-svn-id: http://moon:8086/svn/vhdl/trunk@96 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -0,0 +1,43 @@
|
||||
vhdl work "../../src/sdram_config.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/vga_types.vhd"
|
||||
vhdl work "../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/vga_sync.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd"
|
||||
vhdl work "../../../../lib/misc/utils_pkg.vhd"
|
||||
vhdl work "../../../../lib/misc/dpram_1w1r.vhd"
|
||||
vhdl work "../../../../lib/FIFO/src/sync_fifo_ctrl.vhd"
|
||||
vhdl work "../../../../lib/FIFO/src/gray_counter.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/vga_timing.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/dpram.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/clkgen_virtex4.vhd"
|
||||
vhdl work "../../../../lib/uart/kcuart_tx.vhd"
|
||||
vhdl work "../../../../lib/uart/kcuart_rx.vhd"
|
||||
vhdl work "../../../../lib/uart/bbfifo_16x8.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
|
||||
vhdl work "../../../../lib/misc/dpram_2w2r_virtex4.vhd"
|
||||
vhdl work "../../../../lib/FIFO/src/fifo_sync.vhd"
|
||||
vhdl work "../../../../lib/FIFO/src/async_fifo_ctrl.vhd"
|
||||
vhdl work "../../src/sys_types.vhd"
|
||||
vhdl work "../../src/ram_ld.vhd"
|
||||
vhdl work "../../src/bootloader.ROM_ld.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/vga_backend.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/linefifo.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/char_gen.vhd"
|
||||
vhdl work "../../../../lib/uart/uart_tx.vhd"
|
||||
vhdl work "../../../../lib/uart/uart_rx.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/vga_frontend.vhd"
|
||||
vhdl work "../../../../lib/uart/uart_wb.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd"
|
||||
vhdl work "../../../../lib/misc/rom_wb.vhd"
|
||||
vhdl work "../../../../lib/misc/ram_wb.vhd"
|
||||
vhdl work "../../../../lib/misc/lcd_port.vhd"
|
||||
vhdl work "../../../../lib/misc/gpio_wb.vhd"
|
||||
vhdl work "../../../../lib/misc/clockgen_virtex4.vhd"
|
||||
vhdl work "../../../../lib/misc/async_port_wb.vhd"
|
||||
vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_types.vhd"
|
||||
vhdl work "../../src/mips_sys.vhd"
|
||||
@@ -0,0 +1,43 @@
|
||||
vhdl work "W:\vhdl\projects\mips_sys\src\sdram_config.vhd"
|
||||
vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_types.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
|
||||
vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_sync.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_types.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\utils_pkg.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\sync_fifo_ctrl.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\gray_counter.vhd"
|
||||
vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_timing.vhd"
|
||||
vhdl work "W:\vhdl\lib\VGA_ctrl\src\fonts\char_rom_fixedsys_8x16.vhd"
|
||||
vhdl work "W:\vhdl\lib\VGA_ctrl\src\dpram.vhd"
|
||||
vhdl work "W:\vhdl\lib\VGA_ctrl\src\clkgen_virtex4.vhd"
|
||||
vhdl work "W:\vhdl\lib\uart\kcuart_tx.vhd"
|
||||
vhdl work "W:\vhdl\lib\uart\kcuart_rx.vhd"
|
||||
vhdl work "W:\vhdl\lib\uart\bbfifo_16x8.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_cmd.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\reset_virtex4.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\ddr_phy_virtex4.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\dpram_2w2r_virtex4.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\async_fifo_ctrl.vhd"
|
||||
vhdl work "W:\vhdl\projects\mips_sys\src\sys_types.vhd"
|
||||
vhdl work "W:\vhdl\projects\mips_sys\src\ram_ld.vhd"
|
||||
vhdl work "W:\vhdl\projects\mips_sys\src\bootloader.ROM_ld.vhd"
|
||||
vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_backend.vhd"
|
||||
vhdl work "W:\vhdl\lib\VGA_ctrl\src\linefifo.vhd"
|
||||
vhdl work "W:\vhdl\lib\VGA_ctrl\src\char_gen.vhd"
|
||||
vhdl work "W:\vhdl\lib\uart\uart_tx.vhd"
|
||||
vhdl work "W:\vhdl\lib\uart\uart_rx.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_top.vhd"
|
||||
vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_frontend.vhd"
|
||||
vhdl work "W:\vhdl\lib\uart\uart_wb.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_frontend_wb.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\rom_wb.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\ram_wb.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\lcd_port.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\gpio_wb.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\clockgen_virtex4.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\async_port_wb.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd"
|
||||
vhdl work "W:\vhdl\projects\mips_sys\src\mips_sys.vhd"
|
||||
@@ -0,0 +1,503 @@
|
||||
#
|
||||
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
|
||||
# SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
|
||||
# XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
# AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
|
||||
# OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
|
||||
# IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
|
||||
# AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
|
||||
# FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
|
||||
# WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
|
||||
# IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
|
||||
# REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
|
||||
# INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
# FOR A PARTICULAR PURPOSE.
|
||||
#
|
||||
# (c) Copyright 2005 Xilinx, Inc.
|
||||
# All rights reserved.
|
||||
#
|
||||
|
||||
CONFIG STEPPING = "ES";
|
||||
|
||||
# Bus clock nets
|
||||
NET "clk" TNM_NET = "clk";
|
||||
TIMESPEC "TS_clk" = PERIOD "clk" 9.95 ns HIGH 50 %;
|
||||
|
||||
NET "inst_vga_frontend/inst_vga_backend/inst_clkgen/vga_clk0" TNM_NET = "vga_clk";
|
||||
#TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 7.5 ns HIGH 50 %;
|
||||
TIMESPEC TS_unrelate = FROM clk TO vga_clk TIG;
|
||||
|
||||
NET "sys_clk_in" LOC = "AE14";
|
||||
NET sys_clk_in IOSTANDARD = LVCMOS33;
|
||||
NET "sys_rst_n_in" LOC = "D6";
|
||||
NET sys_rst_n_in PULLUP;
|
||||
NET "sys_rst_n_in" TIG;
|
||||
NET "rst" TIG;
|
||||
|
||||
# Locate DCM/BUFG - Tools can probably figure them out automatically
|
||||
# but just LOC them down to be safe
|
||||
#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_0 LOC = DCM_ADV_X0Y2;
|
||||
#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_1 LOC = DCM_ADV_X0Y1;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
// Misc Board Signals
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
NET sys_error<0> LOC = V6;
|
||||
NET sys_error<1> LOC = L24;
|
||||
NET sys_error<*> IOSTANDARD = LVCMOS33;
|
||||
NET sys_error<*> DRIVE = 2;
|
||||
NET sys_error<*> TIG;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
// RS-232
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
NET sys_rx LOC = W2;
|
||||
NET sys_rx IOSTANDARD = LVCMOS33;
|
||||
NET sys_rx TIG;
|
||||
NET "sys_tx" LOC = "W1";
|
||||
NET sys_tx IOSTANDARD = LVCMOS33;
|
||||
NET "sys_tx" TIG;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
// Buttons, LEDs, and DIP Switches
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
# GPLED 0-3
|
||||
NET "sys_led<0>" LOC = "G5"; #GPLED0
|
||||
NET "sys_led<1>" LOC = "G6"; #GPLED1
|
||||
NET "sys_led<2>" LOC = "A11"; #GPLED2
|
||||
NET "sys_led<3>" LOC = "A12"; #GPLED3
|
||||
# North-East-South-West-Center LEDs
|
||||
NET "sys_led<4>" LOC = "F9"; # W LED
|
||||
NET "sys_led<5>" LOC = "E2"; # N LED
|
||||
NET "sys_led<6>" LOC = "E10"; # E LED
|
||||
NET "sys_led<7>" LOC = "A5"; # S LED
|
||||
NET "sys_led<8>" LOC = "C6"; # C LED
|
||||
NET "sys_led<*>" TIG;
|
||||
NET "sys_led<*>" SLEW = SLOW;
|
||||
NET "sys_led<*>" DRIVE = 2;
|
||||
#NET "sys_led<*>" IOSTANDARD = LVCMOS33;
|
||||
# North-East-South-West-Center Buttons
|
||||
NET "sys_btn<0>" LOC = "E9"; # W Button
|
||||
NET "sys_btn<1>" LOC = "E7"; # N Button
|
||||
NET "sys_btn<2>" LOC = "F10"; # E Button
|
||||
NET "sys_btn<3>" LOC = "A6"; # S Button
|
||||
NET "sys_btn<4>" LOC = "B6"; # C Button
|
||||
NET "sys_btn<*>" TIG;
|
||||
NET "sys_btn<*>" PULLDOWN;
|
||||
#NET "sys_btn<*>" IOSTANDARD = LVCMOS33;
|
||||
# Dip Switches 1-8
|
||||
NET "sys_dip<7>" LOC = "U24"; # DIP SW 8
|
||||
NET "sys_dip<6>" LOC = "U25"; # DIP SW 7
|
||||
NET "sys_dip<5>" LOC = "V23"; # DIP SW 6
|
||||
NET "sys_dip<4>" LOC = "U23"; # DIP SW 5
|
||||
NET "sys_dip<3>" LOC = "U26"; # DIP SW 4
|
||||
NET "sys_dip<2>" LOC = "T26"; # DIP SW 3
|
||||
NET "sys_dip<1>" LOC = "R19"; # DIP SW 2
|
||||
NET "sys_dip<0>" LOC = "R20"; # DIP SW 1
|
||||
NET "sys_dip<*>" PULLDOWN;
|
||||
NET "sys_dip<*>" IOSTANDARD = LVCMOS33;
|
||||
NET "sys_dip<*>" TIG;
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
// LCD
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
NET sys_lcd_e LOC = AE13; # LCD_E
|
||||
NET sys_lcd_e IOSTANDARD = LVCMOS33;
|
||||
NET sys_lcd_e SLEW = SLOW;
|
||||
NET sys_lcd_e DRIVE = 2;
|
||||
NET sys_lcd_e TIG;
|
||||
NET sys_lcd_rs LOC = AC17; # LCD_RS
|
||||
NET sys_lcd_rs IOSTANDARD = LVCMOS33;
|
||||
NET sys_lcd_rs SLEW = SLOW;
|
||||
NET sys_lcd_rs DRIVE = 2;
|
||||
NET sys_lcd_rs TIG;
|
||||
NET sys_lcd_rw LOC = AB17; # LCD_RW
|
||||
NET sys_lcd_rw IOSTANDARD = LVCMOS33;
|
||||
NET sys_lcd_rw SLEW = SLOW;
|
||||
NET sys_lcd_rw DRIVE = 2;
|
||||
NET sys_lcd_rw TIG;
|
||||
NET sys_lcd_d<3> LOC = AF12; # LCD_DB7
|
||||
NET sys_lcd_d<2> LOC = AE12; # LCD_DB6
|
||||
NET sys_lcd_d<1> LOC = AC10; # LCD_DB5
|
||||
NET sys_lcd_d<0> LOC = AB10; # LCD_DB4
|
||||
NET sys_lcd_d<*> IOSTANDARD = LVCMOS33;
|
||||
NET sys_lcd_d<*> SLEW = SLOW;
|
||||
NET sys_lcd_d<*> DRIVE = 2;
|
||||
NET sys_lcd_d<*> PULLDOWN;
|
||||
NET sys_lcd_d<*> TIG;
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
# IO Pad Location Constraints / Properties for DDR Controllers
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
NET sys_sdr_a_q<0> LOC = C26; # DDR_A0
|
||||
NET sys_sdr_a_q<1> LOC = E17; # DDR_A1
|
||||
NET sys_sdr_a_q<2> LOC = D18; # DDR_A2
|
||||
NET sys_sdr_a_q<3> LOC = C19; # DDR_A3
|
||||
NET sys_sdr_a_q<4> LOC = F17; # DDR_A4
|
||||
NET sys_sdr_a_q<5> LOC = B18; # DDR_A5
|
||||
NET sys_sdr_a_q<6> LOC = B20; # DDR_A6
|
||||
NET sys_sdr_a_q<7> LOC = C20; # DDR_A7
|
||||
NET sys_sdr_a_q<8> LOC = D20; # DDR_A8
|
||||
NET sys_sdr_a_q<9> LOC = C21; # DDR_A9
|
||||
NET sys_sdr_a_q<10> LOC = A18; # DDR_A10
|
||||
NET sys_sdr_a_q<11> LOC = B21; # DDR_A11
|
||||
NET sys_sdr_a_q<12> LOC = A24; # DDR_A12
|
||||
NET sys_sdr_ba_q<0> LOC = B12; # DDR_BA0
|
||||
NET sys_sdr_ba_q<1> LOC = A16; # DDR_BA1
|
||||
NET sys_sdr_cas_qn LOC = F23; # DDR_CAS_N
|
||||
NET sys_sdr_cke_q LOC = G22; # DDR_CKE
|
||||
NET sys_sdr_cs_qn LOC = G21; # DDR_CS_N
|
||||
NET sys_sdr_ras_qn LOC = F24; # DDR_RAS_N
|
||||
NET sys_sdr_we_qn LOC = A23; # DDR_WE_N
|
||||
|
||||
NET sys_sdr_clk_p LOC = A10; # DDR_CK1_P
|
||||
NET sys_sdr_clk_fb LOC = B13; # DDR_CK1_P (FEEDBACK)
|
||||
NET sys_sdr_clk_n LOC = B10; # DDR_CK1_N
|
||||
|
||||
NET sys_sdr_dm_q<0> LOC = G19; # DDR_DM0
|
||||
NET sys_sdr_dm_q<1> LOC = G24; # DDR_DM1
|
||||
NET sys_sdr_dm_q<2> LOC = G20; # DDR_DM2
|
||||
NET sys_sdr_dm_q<3> LOC = C22; # DDR_DM3
|
||||
|
||||
NET sys_sdr_dqs_q<0> LOC = D25; # DDR_DQS0
|
||||
NET sys_sdr_dqs_q<1> LOC = G18; # DDR_DQS1
|
||||
NET sys_sdr_dqs_q<2> LOC = G17; # DDR_DQS2
|
||||
NET sys_sdr_dqs_q<3> LOC = D26; # DDR_DQS3
|
||||
|
||||
NET sys_sdr_data<0> LOC = H20; # DDR_D0
|
||||
NET sys_sdr_data<1> LOC = E23; # DDR_D1
|
||||
NET sys_sdr_data<2> LOC = H26; # DDR_D2
|
||||
NET sys_sdr_data<3> LOC = H22; # DDR_D3
|
||||
NET sys_sdr_data<4> LOC = E25; # DDR_D4
|
||||
NET sys_sdr_data<5> LOC = E26; # DDR_D5
|
||||
NET sys_sdr_data<6> LOC = F26; # DDR_D6
|
||||
NET sys_sdr_data<7> LOC = E24; # DDR_D7
|
||||
NET sys_sdr_data<8> LOC = E20; # DDR_D8
|
||||
NET sys_sdr_data<9> LOC = A22; # DDR_D9
|
||||
NET sys_sdr_data<10> LOC = C23; # DDR_D10
|
||||
NET sys_sdr_data<11> LOC = C24; # DDR_D11
|
||||
NET sys_sdr_data<12> LOC = A20; # DDR_D12
|
||||
NET sys_sdr_data<13> LOC = A21; # DDR_D13
|
||||
NET sys_sdr_data<14> LOC = D24; # DDR_D14
|
||||
NET sys_sdr_data<15> LOC = E18; # DDR_D15
|
||||
NET sys_sdr_data<16> LOC = F18; # DDR_D16
|
||||
NET sys_sdr_data<17> LOC = A19; # DDR_D17
|
||||
NET sys_sdr_data<18> LOC = F19; # DDR_D18
|
||||
NET sys_sdr_data<19> LOC = B23; # DDR_D19
|
||||
NET sys_sdr_data<20> LOC = E21; # DDR_D20
|
||||
NET sys_sdr_data<21> LOC = D22; # DDR_D21
|
||||
NET sys_sdr_data<22> LOC = D23; # DDR_D22
|
||||
NET sys_sdr_data<23> LOC = B24; # DDR_D23
|
||||
NET sys_sdr_data<24> LOC = E22; # DDR_D24
|
||||
NET sys_sdr_data<25> LOC = F20; # DDR_D25
|
||||
NET sys_sdr_data<26> LOC = H23; # DDR_D26
|
||||
NET sys_sdr_data<27> LOC = G25; # DDR_D27
|
||||
NET sys_sdr_data<28> LOC = G26; # DDR_D28
|
||||
NET sys_sdr_data<29> LOC = H25; # DDR_D29
|
||||
NET sys_sdr_data<30> LOC = H24; # DDR_D30
|
||||
NET sys_sdr_data<31> LOC = H21; # DDR_D31
|
||||
|
||||
NET sys_sdr_a_q<*> IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_a_q<*> FAST;
|
||||
|
||||
NET sys_sdr_ba_q<*> IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_ba_q<*> FAST;
|
||||
|
||||
NET sys_sdr_cas_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_cas_qn FAST;
|
||||
|
||||
NET sys_sdr_cke_q IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_cke_q FAST;
|
||||
|
||||
NET sys_sdr_clk_p IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_clk_p FAST;
|
||||
NET sys_sdr_clk_fb IOSTANDARD = LVCMOS25;
|
||||
NET sys_sdr_clk_fb IOBDELAY = NONE;
|
||||
NET sys_sdr_clk_n IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_clk_n FAST;
|
||||
|
||||
NET sys_sdr_cas_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_cas_qn FAST;
|
||||
|
||||
NET sys_sdr_cs_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_cs_qn FAST;
|
||||
|
||||
NET sys_sdr_ras_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_ras_qn FAST;
|
||||
|
||||
NET sys_sdr_we_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_we_qn FAST;
|
||||
|
||||
NET sys_sdr_dqs_q<*> IOSTANDARD = SSTL2_II;
|
||||
NET sys_sdr_dqs_q<*> IOBDELAY = NONE;
|
||||
NET sys_sdr_dqs_q<*> FAST;
|
||||
|
||||
NET sys_sdr_dm_q<*> IOSTANDARD = SSTL2_II;
|
||||
NET sys_sdr_dm_q<*> IOBDELAY = NONE;
|
||||
NET sys_sdr_dm_q<*> FAST;
|
||||
|
||||
NET sys_sdr_data<*> IOSTANDARD = SSTL2_II;
|
||||
NET sys_sdr_data<*> IOBDELAY = NONE;
|
||||
NET sys_sdr_data<*> FAST;
|
||||
|
||||
#NET "sys_sdr_data<*>" OFFSET=OUT 2.5 ns BEFORE "sys_sdr_clk_n";
|
||||
|
||||
NET "sys_sdr_clk_p" TNM_NET = "ddr_clk_p";
|
||||
NET "sys_sdr_clk_n" TNM_NET = "ddr_clk_n";
|
||||
|
||||
# Timing Constraint for DDR Feedback Clock
|
||||
NET sys_sdr_clk_fb FEEDBACK = 1 ns NET sys_sdr_clk_p;
|
||||
|
||||
# USB
|
||||
NET sys_usb_a<0> LOC = Y10;
|
||||
NET sys_usb_a<1> LOC = AA10;
|
||||
NET sys_usb_a<*> IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET sys_usb_d<0> LOC = AB7;
|
||||
NET sys_usb_d<1> LOC = AC9;
|
||||
NET sys_usb_d<2> LOC = AB9;
|
||||
NET sys_usb_d<3> LOC = AE6;
|
||||
NET sys_usb_d<4> LOC = AD6;
|
||||
NET sys_usb_d<5> LOC = AF9;
|
||||
NET sys_usb_d<6> LOC = AE9;
|
||||
NET sys_usb_d<7> LOC = AD8;
|
||||
NET sys_usb_d<8> LOC = AC8;
|
||||
NET sys_usb_d<9> LOC = AF4;
|
||||
NET sys_usb_d<10> LOC = AE4;
|
||||
NET sys_usb_d<11> LOC = AD3;
|
||||
NET sys_usb_d<12> LOC = AC3;
|
||||
NET sys_usb_d<13> LOC = AF6;
|
||||
NET sys_usb_d<14> LOC = AF5;
|
||||
NET sys_usb_d<15> LOC = AA7;
|
||||
NET sys_usb_d<*> IOSTANDARD = LVCMOS33;
|
||||
NET sys_usb_d<*> SLEW = FAST;
|
||||
NET sys_usb_d<*> DRIVE = 8;
|
||||
NET sys_usb_d<*> PULLDOWN;
|
||||
|
||||
NET sys_usb_rdn LOC = AA8;
|
||||
NET sys_usb_rdn IOSTANDARD = LVCMOS33;
|
||||
NET sys_usb_rdn SLEW = FAST;
|
||||
NET sys_usb_rdn DRIVE = 8;
|
||||
|
||||
NET sys_usb_wrn LOC = Y8;
|
||||
NET sys_usb_wrn IOSTANDARD = LVCMOS33;
|
||||
NET sys_usb_wrn SLEW = FAST;
|
||||
NET sys_usb_wrn DRIVE = 8;
|
||||
|
||||
NET sys_usb_csn LOC = AF10;
|
||||
NET sys_usb_csn IOSTANDARD = LVCMOS33;
|
||||
NET sys_usb_csn SLEW = FAST;
|
||||
NET sys_usb_csn DRIVE = 8;
|
||||
|
||||
NET sys_usb_rstn LOC = A7;
|
||||
NET sys_usb_rstn IOSTANDARD = LVCMOS25;
|
||||
NET sys_usb_rstn TIG;
|
||||
|
||||
NET sys_usb_int LOC = V5;
|
||||
NET sys_usb_int IOSTANDARD = LVCMOS33;
|
||||
NET sys_usb_int PULLDOWN;
|
||||
NET sys_usb_int TIG;
|
||||
|
||||
# FLASH
|
||||
NET sys_flash_ssram_a<24> LOC = T21;
|
||||
NET sys_flash_ssram_a<23> LOC = U20;
|
||||
NET sys_flash_ssram_a<22> LOC = T19;
|
||||
NET sys_flash_ssram_a<21> LOC = AC5;
|
||||
NET sys_flash_ssram_a<20> LOC = AB5;
|
||||
NET sys_flash_ssram_a<19> LOC = AC4;
|
||||
NET sys_flash_ssram_a<18> LOC = AB4;
|
||||
NET sys_flash_ssram_a<17> LOC = AB3;
|
||||
NET sys_flash_ssram_a<16> LOC = AA4;
|
||||
NET sys_flash_ssram_a<15> LOC = AA3;
|
||||
NET sys_flash_ssram_a<14> LOC = W5;
|
||||
NET sys_flash_ssram_a<13> LOC = W6;
|
||||
NET sys_flash_ssram_a<12> LOC = W3;
|
||||
NET sys_flash_ssram_a<11> LOC = AF3;
|
||||
NET sys_flash_ssram_a<10> LOC = AE3;
|
||||
NET sys_flash_ssram_a<9> LOC = AD2;
|
||||
NET sys_flash_ssram_a<8> LOC = AD1;
|
||||
NET sys_flash_ssram_a<7> LOC = AC2;
|
||||
NET sys_flash_ssram_a<6> LOC = AC1;
|
||||
NET sys_flash_ssram_a<5> LOC = AB2;
|
||||
NET sys_flash_ssram_a<4> LOC = AB1;
|
||||
NET sys_flash_ssram_a<3> LOC = AA1;
|
||||
NET sys_flash_ssram_a<2> LOC = Y2;
|
||||
NET sys_flash_ssram_a<1> LOC = Y1;
|
||||
NET sys_flash_ssram_a<0> LOC = T20;
|
||||
NET sys_flash_ssram_a<*> IOSTANDARD = LVDCI_33;
|
||||
NET sys_flash_ssram_a<*> SLEW = FAST;
|
||||
NET sys_flash_ssram_a<*> DRIVE = 8;
|
||||
|
||||
|
||||
NET sys_flash_ssram_d<31> LOC = F14;
|
||||
NET sys_flash_ssram_d<30> LOC = F13;
|
||||
NET sys_flash_ssram_d<29> LOC = F12;
|
||||
NET sys_flash_ssram_d<28> LOC = F11;
|
||||
NET sys_flash_ssram_d<27> LOC = F16;
|
||||
NET sys_flash_ssram_d<26> LOC = F15;
|
||||
NET sys_flash_ssram_d<25> LOC = D14;
|
||||
NET sys_flash_ssram_d<24> LOC = D13;
|
||||
NET sys_flash_ssram_d<23> LOC = D15;
|
||||
NET sys_flash_ssram_d<22> LOC = E14;
|
||||
NET sys_flash_ssram_d<21> LOC = C11;
|
||||
NET sys_flash_ssram_d<20> LOC = D11;
|
||||
NET sys_flash_ssram_d<19> LOC = D16;
|
||||
NET sys_flash_ssram_d<18> LOC = C16;
|
||||
NET sys_flash_ssram_d<17> LOC = E13;
|
||||
NET sys_flash_ssram_d<16> LOC = D12;
|
||||
NET sys_flash_ssram_d<15> LOC = AA14;
|
||||
NET sys_flash_ssram_d<14> LOC = AB14;
|
||||
NET sys_flash_ssram_d<13> LOC = AC12;
|
||||
NET sys_flash_ssram_d<12> LOC = AC11;
|
||||
NET sys_flash_ssram_d<11> LOC = AA16;
|
||||
NET sys_flash_ssram_d<10> LOC = AA15;
|
||||
NET sys_flash_ssram_d<9> LOC = AB13;
|
||||
NET sys_flash_ssram_d<8> LOC = AA13;
|
||||
NET sys_flash_ssram_d<7> LOC = AC14;
|
||||
NET sys_flash_ssram_d<6> LOC = AD14;
|
||||
NET sys_flash_ssram_d<5> LOC = AA12;
|
||||
NET sys_flash_ssram_d<4> LOC = AA11;
|
||||
NET sys_flash_ssram_d<3> LOC = AC16;
|
||||
NET sys_flash_ssram_d<2> LOC = AC15;
|
||||
NET sys_flash_ssram_d<1> LOC = AC13;
|
||||
NET sys_flash_ssram_d<0> LOC = AD13;
|
||||
NET sys_flash_ssram_d<*> IOSTANDARD = LVCMOS33;
|
||||
NET sys_flash_ssram_d<*> DRIVE = 12;
|
||||
NET sys_flash_ssram_d<*> SLEW = FAST;
|
||||
NET sys_flash_ssram_d<*> PULLDOWN;
|
||||
|
||||
NET sys_flash_ssram_oe_n LOC = AC6;
|
||||
NET sys_flash_ssram_oe_n IOSTANDARD = LVDCI_33;
|
||||
NET sys_flash_ssram_oe_n SLEW = FAST;
|
||||
NET sys_flash_ssram_oe_n DRIVE = 8;
|
||||
|
||||
NET sys_flash_ssram_we_n LOC = AB6;
|
||||
NET sys_flash_ssram_we_n IOSTANDARD = LVDCI_33;
|
||||
NET sys_flash_ssram_we_n SLEW = FAST;
|
||||
NET sys_flash_ssram_we_n DRIVE = 8;
|
||||
|
||||
NET sys_flash_ce LOC = W7;
|
||||
NET sys_flash_ce IOSTANDARD = LVDCI_33;
|
||||
NET sys_flash_ce SLEW = FAST;
|
||||
NET sys_flash_ce DRIVE = 8;
|
||||
|
||||
NET sys_flash_rstn LOC = AD10;
|
||||
NET sys_flash_rstn IOSTANDARD = LVCMOS33;
|
||||
NET sys_flash_rstn DRIVE = 8;
|
||||
NET sys_flash_rstn SLEW = FAST;
|
||||
NET sys_flash_rstn TIG;
|
||||
|
||||
NET sys_flash_byten LOC = N22;
|
||||
NET sys_flash_byten IOSTANDARD = LVCMOS33;
|
||||
NET sys_flash_byten DRIVE = 8;
|
||||
NET sys_flash_byten SLEW = FAST;
|
||||
NET sys_flash_byten TIG;
|
||||
|
||||
# SSRAM
|
||||
NET sys_ssram_clk LOC = AF7;
|
||||
NET sys_ssram_clk IOSTANDARD = LVCMOS33;
|
||||
NET sys_ssram_clk DRIVE = 16;
|
||||
NET sys_ssram_clk SLEW = FAST;
|
||||
|
||||
NET "sys_ssram_clk" TNM_NET = "ssram_clk";
|
||||
#TIMESPEC "TS_ssram_clk" = PERIOD "ssram_clk" 9.95 ns HIGH 50 %;
|
||||
|
||||
|
||||
NET sys_ssram_clk_fb LOC = AD17;
|
||||
NET sys_ssram_clk_fb IOSTANDARD = LVCMOS33;
|
||||
|
||||
# Timing Constraint for Feedback Clock
|
||||
NET sys_ssram_clk_fb FEEDBACK = 1 ns NET sys_ssram_clk;
|
||||
|
||||
NET sys_ssram_ce_n LOC = V7;
|
||||
NET sys_ssram_ce_n IOSTANDARD = LVDCI_33;
|
||||
NET sys_ssram_ce_n SLEW = FAST;
|
||||
NET sys_ssram_ce_n DRIVE = 8;
|
||||
|
||||
NET sys_ssram_bw_n<3> LOC = Y3; #Y4;
|
||||
NET sys_ssram_bw_n<2> LOC = Y4; #Y3;
|
||||
NET sys_ssram_bw_n<1> LOC = Y5; #Y6;
|
||||
NET sys_ssram_bw_n<0> LOC = Y6; #Y5;
|
||||
NET sys_ssram_bw_n<*> IOSTANDARD = LVDCI_33;
|
||||
NET sys_ssram_bw_n<*> SLEW = FAST;
|
||||
NET sys_ssram_bw_n<*> DRIVE = 8;
|
||||
|
||||
NET sys_ssram_adv LOC = W4;
|
||||
NET sys_ssram_adv IOSTANDARD = LVDCI_33;
|
||||
NET sys_ssram_adv SLEW = FAST;
|
||||
NET sys_ssram_adv DRIVE = 8;
|
||||
|
||||
NET sys_ssram_mode LOC = V26;
|
||||
NET sys_ssram_mode IOSTANDARD = LVDCI_33;
|
||||
NET sys_ssram_mode SLEW = FAST;
|
||||
NET sys_ssram_mode DRIVE = 8;
|
||||
|
||||
|
||||
# VGA
|
||||
NET sys_vga_blue<0> LOC = M21; # VGA_B0
|
||||
NET sys_vga_blue<1> LOC = M26; # VGA_B1
|
||||
NET sys_vga_blue<2> LOC = L26; # VGA_B2
|
||||
NET sys_vga_blue<3> LOC = C5; # VGA_B3
|
||||
NET sys_vga_blue<4> LOC = C7; # VGA_B4
|
||||
NET sys_vga_blue<5> LOC = B7; # VGA_B5
|
||||
NET sys_vga_blue<6> LOC = G8; # VGA_B6
|
||||
NET sys_vga_blue<7> LOC = F8; # VGA_B7
|
||||
NET sys_vga_blue<0> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_blue<1> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_blue<2> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_blue<*> SLEW = FAST;
|
||||
NET sys_vga_blue<*> DRIVE = 8;
|
||||
|
||||
NET sys_vga_clk LOC = AF8;
|
||||
NET sys_vga_clk IOSTANDARD = LVDCI_33;
|
||||
NET sys_vga_clk SLEW = FAST;
|
||||
NET sys_vga_clk DRIVE = 8;
|
||||
|
||||
NET sys_vga_green<0> LOC = M22; # VGA_G0
|
||||
NET sys_vga_green<1> LOC = M23; # VGA_G1
|
||||
NET sys_vga_green<2> LOC = M20; # VGA_G2
|
||||
NET sys_vga_green<3> LOC = E4; # VGA_G3
|
||||
NET sys_vga_green<4> LOC = D3; # VGA_G4
|
||||
NET sys_vga_green<5> LOC = H7; # VGA_G5
|
||||
NET sys_vga_green<6> LOC = H8; # VGA_G6
|
||||
NET sys_vga_green<7> LOC = C1; # VGA_G7
|
||||
NET sys_vga_green<0> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_green<1> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_green<2> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_green<*> SLEW = FAST;
|
||||
NET sys_vga_green<*> DRIVE = 8;
|
||||
|
||||
NET sys_vga_hsync LOC = C10;
|
||||
NET sys_vga_hsync SLEW = FAST;
|
||||
NET sys_vga_hsync DRIVE = 8;
|
||||
#NET sys_vga_hsync IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET sys_vga_red<0> LOC = N23; #VGA_R0
|
||||
NET sys_vga_red<1> LOC = N24; #VGA_R1
|
||||
NET sys_vga_red<2> LOC = N25; #VGA_R2
|
||||
NET sys_vga_red<3> LOC = C2; #VGA_R3
|
||||
NET sys_vga_red<4> LOC = G7; #VGA_R4
|
||||
NET sys_vga_red<5> LOC = F7; #VGA_R5
|
||||
NET sys_vga_red<6> LOC = E5; #VGA_R6
|
||||
NET sys_vga_red<7> LOC = E6; #VGA_R7
|
||||
NET sys_vga_red<0> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_red<1> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_red<2> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_red<*> SLEW = FAST;
|
||||
NET sys_vga_red<*> DRIVE = 8;
|
||||
|
||||
NET sys_vga_vsync LOC = A8;
|
||||
NET sys_vga_vsync SLEW = FAST;
|
||||
NET sys_vga_vsync DRIVE = 8;
|
||||
#NET sys_vga_vsync IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET sys_vga_blank_n LOC = M24;
|
||||
NET sys_vga_blank_n SLEW = FAST;
|
||||
NET sys_vga_blank_n DRIVE = 8;
|
||||
NET sys_vga_blank_n IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET sys_vga_sync_n LOC = L23;
|
||||
NET sys_vga_sync_n SLEW = FAST;
|
||||
NET sys_vga_sync_n DRIVE = 8;
|
||||
NET sys_vga_sync_n IOSTANDARD = LVCMOS33;
|
||||
@@ -0,0 +1,484 @@
|
||||
#
|
||||
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
|
||||
# SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
|
||||
# XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
# AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
|
||||
# OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
|
||||
# IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
|
||||
# AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
|
||||
# FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
|
||||
# WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
|
||||
# IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
|
||||
# REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
|
||||
# INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
# FOR A PARTICULAR PURPOSE.
|
||||
#
|
||||
# (c) Copyright 2005 Xilinx, Inc.
|
||||
# All rights reserved.
|
||||
#
|
||||
|
||||
CONFIG STEPPING = "ES";
|
||||
|
||||
# Bus clock nets
|
||||
NET "clk" TNM_NET = "clk";
|
||||
TIMESPEC "TS_clk" = PERIOD "clk" 9.95 ns HIGH 50 %;
|
||||
|
||||
NET "inst_vga_frontend/inst_vga_backend/inst_clkgen/vga_clk0" TNM_NET = "vga_clk";
|
||||
#TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 7.5 ns HIGH 50 %;
|
||||
TIMESPEC TS_unrelate = FROM clk TO vga_clk TIG;
|
||||
|
||||
NET "sys_clk_in" LOC = "AE14";
|
||||
NET sys_clk_in IOSTANDARD = LVCMOS33;
|
||||
NET "sys_rst_n_in" LOC = "D6";
|
||||
NET sys_rst_n_in PULLUP;
|
||||
NET "sys_rst_n_in" TIG;
|
||||
NET "rst" TIG;
|
||||
|
||||
NET "sys_clk_in" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||
PIN "inst_clockgen/inst_DCM_BASE_0.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||
|
||||
# Locate DCM/BUFG - Tools can probably figure them out automatically
|
||||
# but just LOC them down to be safe
|
||||
#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_0 LOC = DCM_ADV_X0Y2;
|
||||
#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_1 LOC = DCM_ADV_X0Y1;
|
||||
|
||||
INST "inst_mips_top" AREA_GROUP = "AG_inst_mips_top" ;
|
||||
# GOOD 1
|
||||
#AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y85:SLICE_X39Y0 ;
|
||||
#AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y10, RAMB16_X1Y0:RAMB16_X1Y10, RAMB16_X2Y0:RAMB16_X2Y10, RAMB16_X3Y0:RAMB16_X3Y10 ;
|
||||
|
||||
# GOOD 2 (smaller)
|
||||
#AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y69:SLICE_X39Y0 ;
|
||||
#AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y8, RAMB16_X1Y0:RAMB16_X1Y8, RAMB16_X2Y0:RAMB16_X2Y8, RAMB16_X3Y0:RAMB16_X3Y8 ;
|
||||
|
||||
# GOOD 3 (even smaller)
|
||||
#AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y61:SLICE_X39Y0 ;
|
||||
#AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y7, RAMB16_X1Y0:RAMB16_X1Y7, RAMB16_X2Y0:RAMB16_X2Y7, RAMB16_X3Y0:RAMB16_X3Y7 ;
|
||||
|
||||
# GOOD 4 (even more smaller)
|
||||
AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y53:SLICE_X39Y0 ;
|
||||
AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y6, RAMB16_X1Y0:RAMB16_X1Y6, RAMB16_X2Y0:RAMB16_X2Y6, RAMB16_X3Y0:RAMB16_X3Y6 ;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
// Misc Board Signals
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
NET sys_error<0> LOC = V6;
|
||||
NET sys_error<1> LOC = L24;
|
||||
NET sys_error<*> IOSTANDARD = LVCMOS33;
|
||||
NET sys_error<*> DRIVE = 2;
|
||||
NET sys_error<*> TIG;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
// RS-232
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
NET sys_rx LOC = W2;
|
||||
NET sys_rx IOSTANDARD = LVCMOS33;
|
||||
NET sys_rx TIG;
|
||||
NET "sys_tx" LOC = "W1";
|
||||
NET sys_tx IOSTANDARD = LVCMOS33;
|
||||
NET "sys_tx" TIG;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
// Buttons, LEDs, and DIP Switches
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
# GPLED 0-3
|
||||
NET "sys_led<0>" LOC = "G5"; #GPLED0
|
||||
NET "sys_led<1>" LOC = "G6"; #GPLED1
|
||||
NET "sys_led<2>" LOC = "A11"; #GPLED2
|
||||
NET "sys_led<3>" LOC = "A12"; #GPLED3
|
||||
# North-East-South-West-Center LEDs
|
||||
NET "sys_led<4>" LOC = "F9"; # W LED
|
||||
NET "sys_led<5>" LOC = "E2"; # N LED
|
||||
NET "sys_led<6>" LOC = "E10"; # E LED
|
||||
NET "sys_led<7>" LOC = "A5"; # S LED
|
||||
NET "sys_led<8>" LOC = "C6"; # C LED
|
||||
NET "sys_led<*>" TIG;
|
||||
NET "sys_led<*>" SLEW = SLOW;
|
||||
NET "sys_led<*>" DRIVE = 2;
|
||||
#NET "sys_led<*>" IOSTANDARD = LVCMOS33;
|
||||
# North-East-South-West-Center Buttons
|
||||
NET "sys_btn<0>" LOC = "E9"; # W Button
|
||||
NET "sys_btn<1>" LOC = "E7"; # N Button
|
||||
NET "sys_btn<2>" LOC = "F10"; # E Button
|
||||
NET "sys_btn<3>" LOC = "A6"; # S Button
|
||||
NET "sys_btn<4>" LOC = "B6"; # C Button
|
||||
NET "sys_btn<*>" TIG;
|
||||
NET "sys_btn<*>" PULLDOWN;
|
||||
#NET "sys_btn<*>" IOSTANDARD = LVCMOS33;
|
||||
# Dip Switches 1-8
|
||||
NET "sys_dip<7>" LOC = "U24"; # DIP SW 8
|
||||
NET "sys_dip<6>" LOC = "U25"; # DIP SW 7
|
||||
NET "sys_dip<5>" LOC = "V23"; # DIP SW 6
|
||||
NET "sys_dip<4>" LOC = "U23"; # DIP SW 5
|
||||
NET "sys_dip<3>" LOC = "U26"; # DIP SW 4
|
||||
NET "sys_dip<2>" LOC = "T26"; # DIP SW 3
|
||||
NET "sys_dip<1>" LOC = "R19"; # DIP SW 2
|
||||
NET "sys_dip<0>" LOC = "R20"; # DIP SW 1
|
||||
NET "sys_dip<*>" PULLDOWN;
|
||||
NET "sys_dip<*>" IOSTANDARD = LVCMOS33;
|
||||
NET "sys_dip<*>" TIG;
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
// LCD
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
NET sys_lcd_e LOC = AE13; # LCD_E
|
||||
NET sys_lcd_e IOSTANDARD = LVCMOS33;
|
||||
NET sys_lcd_e SLEW = SLOW;
|
||||
NET sys_lcd_e DRIVE = 2;
|
||||
NET sys_lcd_e TIG;
|
||||
NET sys_lcd_rs LOC = AC17; # LCD_RS
|
||||
NET sys_lcd_rs IOSTANDARD = LVCMOS33;
|
||||
NET sys_lcd_rs SLEW = SLOW;
|
||||
NET sys_lcd_rs DRIVE = 2;
|
||||
NET sys_lcd_rs TIG;
|
||||
NET sys_lcd_rw LOC = AB17; # LCD_RW
|
||||
NET sys_lcd_rw IOSTANDARD = LVCMOS33;
|
||||
NET sys_lcd_rw SLEW = SLOW;
|
||||
NET sys_lcd_rw DRIVE = 2;
|
||||
NET sys_lcd_rw TIG;
|
||||
NET sys_lcd_d<3> LOC = AF12; # LCD_DB7
|
||||
NET sys_lcd_d<2> LOC = AE12; # LCD_DB6
|
||||
NET sys_lcd_d<1> LOC = AC10; # LCD_DB5
|
||||
NET sys_lcd_d<0> LOC = AB10; # LCD_DB4
|
||||
NET sys_lcd_d<*> IOSTANDARD = LVCMOS33;
|
||||
NET sys_lcd_d<*> SLEW = SLOW;
|
||||
NET sys_lcd_d<*> DRIVE = 2;
|
||||
NET sys_lcd_d<*> PULLDOWN;
|
||||
NET sys_lcd_d<*> TIG;
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
# IO Pad Location Constraints / Properties for DDR Controllers
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
NET sys_sdr_a_q<0> LOC = C26; # DDR_A0
|
||||
NET sys_sdr_a_q<1> LOC = E17; # DDR_A1
|
||||
NET sys_sdr_a_q<2> LOC = D18; # DDR_A2
|
||||
NET sys_sdr_a_q<3> LOC = C19; # DDR_A3
|
||||
NET sys_sdr_a_q<4> LOC = F17; # DDR_A4
|
||||
NET sys_sdr_a_q<5> LOC = B18; # DDR_A5
|
||||
NET sys_sdr_a_q<6> LOC = B20; # DDR_A6
|
||||
NET sys_sdr_a_q<7> LOC = C20; # DDR_A7
|
||||
NET sys_sdr_a_q<8> LOC = D20; # DDR_A8
|
||||
NET sys_sdr_a_q<9> LOC = C21; # DDR_A9
|
||||
NET sys_sdr_a_q<10> LOC = A18; # DDR_A10
|
||||
NET sys_sdr_a_q<11> LOC = B21; # DDR_A11
|
||||
NET sys_sdr_a_q<12> LOC = A24; # DDR_A12
|
||||
NET sys_sdr_ba_q<0> LOC = B12; # DDR_BA0
|
||||
NET sys_sdr_ba_q<1> LOC = A16; # DDR_BA1
|
||||
NET sys_sdr_cas_qn LOC = F23; # DDR_CAS_N
|
||||
NET sys_sdr_cke_q LOC = G22; # DDR_CKE
|
||||
NET sys_sdr_cs_qn LOC = G21; # DDR_CS_N
|
||||
NET sys_sdr_ras_qn LOC = F24; # DDR_RAS_N
|
||||
NET sys_sdr_we_qn LOC = A23; # DDR_WE_N
|
||||
|
||||
NET sys_sdr_clk_p LOC = A10; # DDR_CK1_P
|
||||
NET sys_sdr_clk_fb LOC = B13; # DDR_CK1_P (FEEDBACK)
|
||||
NET sys_sdr_clk_n LOC = B10; # DDR_CK1_N
|
||||
|
||||
NET sys_sdr_dm_q<0> LOC = G19; # DDR_DM0
|
||||
NET sys_sdr_dm_q<1> LOC = G24; # DDR_DM1
|
||||
NET sys_sdr_dm_q<2> LOC = G20; # DDR_DM2
|
||||
NET sys_sdr_dm_q<3> LOC = C22; # DDR_DM3
|
||||
|
||||
NET sys_sdr_dqs_q<0> LOC = D25; # DDR_DQS0
|
||||
NET sys_sdr_dqs_q<1> LOC = G18; # DDR_DQS1
|
||||
NET sys_sdr_dqs_q<2> LOC = G17; # DDR_DQS2
|
||||
NET sys_sdr_dqs_q<3> LOC = D26; # DDR_DQS3
|
||||
|
||||
NET sys_sdr_data<0> LOC = H20; # DDR_D0
|
||||
NET sys_sdr_data<1> LOC = E23; # DDR_D1
|
||||
NET sys_sdr_data<2> LOC = H26; # DDR_D2
|
||||
NET sys_sdr_data<3> LOC = H22; # DDR_D3
|
||||
NET sys_sdr_data<4> LOC = E25; # DDR_D4
|
||||
NET sys_sdr_data<5> LOC = E26; # DDR_D5
|
||||
NET sys_sdr_data<6> LOC = F26; # DDR_D6
|
||||
NET sys_sdr_data<7> LOC = E24; # DDR_D7
|
||||
NET sys_sdr_data<8> LOC = E20; # DDR_D8
|
||||
NET sys_sdr_data<9> LOC = A22; # DDR_D9
|
||||
NET sys_sdr_data<10> LOC = C23; # DDR_D10
|
||||
NET sys_sdr_data<11> LOC = C24; # DDR_D11
|
||||
NET sys_sdr_data<12> LOC = A20; # DDR_D12
|
||||
NET sys_sdr_data<13> LOC = A21; # DDR_D13
|
||||
NET sys_sdr_data<14> LOC = D24; # DDR_D14
|
||||
NET sys_sdr_data<15> LOC = E18; # DDR_D15
|
||||
NET sys_sdr_data<16> LOC = F18; # DDR_D16
|
||||
NET sys_sdr_data<17> LOC = A19; # DDR_D17
|
||||
NET sys_sdr_data<18> LOC = F19; # DDR_D18
|
||||
NET sys_sdr_data<19> LOC = B23; # DDR_D19
|
||||
NET sys_sdr_data<20> LOC = E21; # DDR_D20
|
||||
NET sys_sdr_data<21> LOC = D22; # DDR_D21
|
||||
NET sys_sdr_data<22> LOC = D23; # DDR_D22
|
||||
NET sys_sdr_data<23> LOC = B24; # DDR_D23
|
||||
NET sys_sdr_data<24> LOC = E22; # DDR_D24
|
||||
NET sys_sdr_data<25> LOC = F20; # DDR_D25
|
||||
NET sys_sdr_data<26> LOC = H23; # DDR_D26
|
||||
NET sys_sdr_data<27> LOC = G25; # DDR_D27
|
||||
NET sys_sdr_data<28> LOC = G26; # DDR_D28
|
||||
NET sys_sdr_data<29> LOC = H25; # DDR_D29
|
||||
NET sys_sdr_data<30> LOC = H24; # DDR_D30
|
||||
NET sys_sdr_data<31> LOC = H21; # DDR_D31
|
||||
|
||||
NET sys_sdr_a_q<*> IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_a_q<*> FAST;
|
||||
|
||||
NET sys_sdr_ba_q<*> IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_ba_q<*> FAST;
|
||||
|
||||
NET sys_sdr_cas_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_cas_qn FAST;
|
||||
|
||||
NET sys_sdr_cke_q IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_cke_q FAST;
|
||||
|
||||
NET sys_sdr_clk_p IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_clk_p FAST;
|
||||
NET sys_sdr_clk_fb IOSTANDARD = LVCMOS25;
|
||||
NET sys_sdr_clk_fb IOBDELAY = NONE;
|
||||
NET sys_sdr_clk_n IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_clk_n FAST;
|
||||
|
||||
NET sys_sdr_cas_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_cas_qn FAST;
|
||||
|
||||
NET sys_sdr_cs_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_cs_qn FAST;
|
||||
|
||||
NET sys_sdr_ras_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_ras_qn FAST;
|
||||
|
||||
NET sys_sdr_we_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_we_qn FAST;
|
||||
|
||||
NET sys_sdr_dqs_q<*> IOSTANDARD = SSTL2_II;
|
||||
NET sys_sdr_dqs_q<*> IOBDELAY = NONE;
|
||||
NET sys_sdr_dqs_q<*> FAST;
|
||||
|
||||
NET sys_sdr_dm_q<*> IOSTANDARD = SSTL2_II;
|
||||
NET sys_sdr_dm_q<*> IOBDELAY = NONE;
|
||||
NET sys_sdr_dm_q<*> FAST;
|
||||
|
||||
NET sys_sdr_data<*> IOSTANDARD = SSTL2_II;
|
||||
NET sys_sdr_data<*> IOBDELAY = NONE;
|
||||
NET sys_sdr_data<*> FAST;
|
||||
|
||||
#NET "sys_sdr_data<*>" OFFSET=OUT 2.5 ns BEFORE "sys_sdr_clk_n";
|
||||
|
||||
NET "sys_sdr_clk_p" TNM_NET = "ddr_clk_p";
|
||||
NET "sys_sdr_clk_n" TNM_NET = "ddr_clk_n";
|
||||
|
||||
# Timing Constraint for DDR Feedback Clock
|
||||
NET sys_sdr_clk_fb FEEDBACK = 1 ns NET sys_sdr_clk_p;
|
||||
|
||||
# USB
|
||||
NET sys_usb_a<0> LOC = Y10;
|
||||
NET sys_usb_a<1> LOC = AA10;
|
||||
NET sys_usb_a<*> IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET sys_usb_d<0> LOC = AB7;
|
||||
NET sys_usb_d<1> LOC = AC9;
|
||||
NET sys_usb_d<2> LOC = AB9;
|
||||
NET sys_usb_d<3> LOC = AE6;
|
||||
NET sys_usb_d<4> LOC = AD6;
|
||||
NET sys_usb_d<5> LOC = AF9;
|
||||
NET sys_usb_d<6> LOC = AE9;
|
||||
NET sys_usb_d<7> LOC = AD8;
|
||||
NET sys_usb_d<8> LOC = AC8;
|
||||
NET sys_usb_d<9> LOC = AF4;
|
||||
NET sys_usb_d<10> LOC = AE4;
|
||||
NET sys_usb_d<11> LOC = AD3;
|
||||
NET sys_usb_d<12> LOC = AC3;
|
||||
NET sys_usb_d<13> LOC = AF6;
|
||||
NET sys_usb_d<14> LOC = AF5;
|
||||
NET sys_usb_d<15> LOC = AA7;
|
||||
NET sys_usb_d<*> IOSTANDARD = LVCMOS33;
|
||||
NET sys_usb_d<*> SLEW = FAST;
|
||||
NET sys_usb_d<*> DRIVE = 8;
|
||||
NET sys_usb_d<*> PULLDOWN;
|
||||
|
||||
NET sys_usb_rdn LOC = AA8;
|
||||
NET sys_usb_rdn IOSTANDARD = LVCMOS33;
|
||||
NET sys_usb_rdn SLEW = FAST;
|
||||
NET sys_usb_rdn DRIVE = 8;
|
||||
|
||||
NET sys_usb_wrn LOC = Y8;
|
||||
NET sys_usb_wrn IOSTANDARD = LVCMOS33;
|
||||
NET sys_usb_wrn SLEW = FAST;
|
||||
NET sys_usb_wrn DRIVE = 8;
|
||||
|
||||
NET sys_usb_csn LOC = AF10;
|
||||
NET sys_usb_csn IOSTANDARD = LVCMOS33;
|
||||
NET sys_usb_csn SLEW = FAST;
|
||||
NET sys_usb_csn DRIVE = 8;
|
||||
|
||||
NET sys_usb_rstn LOC = A7;
|
||||
NET sys_usb_rstn IOSTANDARD = LVCMOS25;
|
||||
NET sys_usb_rstn TIG;
|
||||
|
||||
NET sys_usb_int LOC = V5;
|
||||
NET sys_usb_int IOSTANDARD = LVCMOS33;
|
||||
NET sys_usb_int PULLDOWN;
|
||||
NET sys_usb_int TIG;
|
||||
|
||||
# FLASH
|
||||
NET sys_flash_a<24> LOC = T21;
|
||||
NET sys_flash_a<23> LOC = U20;
|
||||
NET sys_flash_a<22> LOC = T19;
|
||||
NET sys_flash_a<21> LOC = AC5;
|
||||
NET sys_flash_a<20> LOC = AB5;
|
||||
NET sys_flash_a<19> LOC = AC4;
|
||||
NET sys_flash_a<18> LOC = AB4;
|
||||
NET sys_flash_a<17> LOC = AB3;
|
||||
NET sys_flash_a<16> LOC = AA4;
|
||||
NET sys_flash_a<15> LOC = AA3;
|
||||
NET sys_flash_a<14> LOC = W5;
|
||||
NET sys_flash_a<13> LOC = W6;
|
||||
NET sys_flash_a<12> LOC = W3;
|
||||
NET sys_flash_a<11> LOC = AF3;
|
||||
NET sys_flash_a<10> LOC = AE3;
|
||||
NET sys_flash_a<9> LOC = AD2;
|
||||
NET sys_flash_a<8> LOC = AD1;
|
||||
NET sys_flash_a<7> LOC = AC2;
|
||||
NET sys_flash_a<6> LOC = AC1;
|
||||
NET sys_flash_a<5> LOC = AB2;
|
||||
NET sys_flash_a<4> LOC = AB1;
|
||||
NET sys_flash_a<3> LOC = AA1;
|
||||
NET sys_flash_a<2> LOC = Y2;
|
||||
NET sys_flash_a<1> LOC = Y1;
|
||||
NET sys_flash_a<0> LOC = T20;
|
||||
|
||||
NET sys_flash_d<31> LOC = F14;
|
||||
NET sys_flash_d<30> LOC = F13;
|
||||
NET sys_flash_d<29> LOC = F12;
|
||||
NET sys_flash_d<28> LOC = F11;
|
||||
NET sys_flash_d<27> LOC = F16;
|
||||
NET sys_flash_d<26> LOC = F15;
|
||||
NET sys_flash_d<25> LOC = D14;
|
||||
NET sys_flash_d<24> LOC = D13;
|
||||
NET sys_flash_d<23> LOC = D15;
|
||||
NET sys_flash_d<22> LOC = E14;
|
||||
NET sys_flash_d<21> LOC = C11;
|
||||
NET sys_flash_d<20> LOC = D11;
|
||||
NET sys_flash_d<19> LOC = D16;
|
||||
NET sys_flash_d<18> LOC = C16;
|
||||
NET sys_flash_d<17> LOC = E13;
|
||||
NET sys_flash_d<16> LOC = D12;
|
||||
NET sys_flash_d<15> LOC = AA14;
|
||||
NET sys_flash_d<14> LOC = AB14;
|
||||
NET sys_flash_d<13> LOC = AC12;
|
||||
NET sys_flash_d<12> LOC = AC11;
|
||||
NET sys_flash_d<11> LOC = AA16;
|
||||
NET sys_flash_d<10> LOC = AA15;
|
||||
NET sys_flash_d<9> LOC = AB13;
|
||||
NET sys_flash_d<8> LOC = AA13;
|
||||
NET sys_flash_d<7> LOC = AC14;
|
||||
NET sys_flash_d<6> LOC = AD14;
|
||||
NET sys_flash_d<5> LOC = AA12;
|
||||
NET sys_flash_d<4> LOC = AA11;
|
||||
NET sys_flash_d<3> LOC = AC16;
|
||||
NET sys_flash_d<2> LOC = AC15;
|
||||
NET sys_flash_d<1> LOC = AC13;
|
||||
NET sys_flash_d<0> LOC = AD13;
|
||||
NET sys_flash_rdn LOC = AC6;
|
||||
NET sys_flash_wrn LOC = AB6;
|
||||
NET sys_flash_ce LOC = W7;
|
||||
NET sys_flash_rstn LOC = AD10;
|
||||
NET sys_flash_byten LOC = N22;
|
||||
|
||||
NET sys_flash_a<*> IOSTANDARD = LVDCI_33;
|
||||
NET sys_flash_a<*> SLEW = FAST;
|
||||
NET sys_flash_a<*> DRIVE = 8;
|
||||
|
||||
NET sys_flash_d<*> IOSTANDARD = LVCMOS33;
|
||||
NET sys_flash_d<*> DRIVE = 12;
|
||||
NET sys_flash_d<*> SLEW = FAST;
|
||||
NET sys_flash_d<*> PULLDOWN;
|
||||
|
||||
NET sys_flash_rdn IOSTANDARD = LVDCI_33;
|
||||
NET sys_flash_rdn SLEW = FAST;
|
||||
NET sys_flash_rdn DRIVE = 8;
|
||||
|
||||
NET sys_flash_wrn IOSTANDARD = LVDCI_33;
|
||||
NET sys_flash_wrn SLEW = FAST;
|
||||
NET sys_flash_wrn DRIVE = 8;
|
||||
|
||||
NET sys_flash_ce IOSTANDARD = LVDCI_33;
|
||||
NET sys_flash_ce SLEW = FAST;
|
||||
NET sys_flash_ce DRIVE = 8;
|
||||
|
||||
NET sys_flash_rstn IOSTANDARD = LVCMOS33;
|
||||
NET sys_flash_rstn DRIVE = 8;
|
||||
NET sys_flash_rstn SLEW = FAST;
|
||||
NET sys_flash_rstn TIG;
|
||||
|
||||
NET sys_flash_byten IOSTANDARD = LVCMOS33;
|
||||
NET sys_flash_byten DRIVE = 8;
|
||||
NET sys_flash_byten SLEW = FAST;
|
||||
NET sys_flash_byten TIG;
|
||||
|
||||
# VGA
|
||||
NET sys_vga_blue<0> LOC = M21; # VGA_B0
|
||||
NET sys_vga_blue<1> LOC = M26; # VGA_B1
|
||||
NET sys_vga_blue<2> LOC = L26; # VGA_B2
|
||||
NET sys_vga_blue<3> LOC = C5; # VGA_B3
|
||||
NET sys_vga_blue<4> LOC = C7; # VGA_B4
|
||||
NET sys_vga_blue<5> LOC = B7; # VGA_B5
|
||||
NET sys_vga_blue<6> LOC = G8; # VGA_B6
|
||||
NET sys_vga_blue<7> LOC = F8; # VGA_B7
|
||||
NET sys_vga_blue<0> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_blue<1> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_blue<2> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_blue<*> SLEW = FAST;
|
||||
NET sys_vga_blue<*> DRIVE = 8;
|
||||
|
||||
NET sys_vga_clk LOC = AF8;
|
||||
NET sys_vga_clk IOSTANDARD = LVDCI_33;
|
||||
NET sys_vga_clk SLEW = FAST;
|
||||
NET sys_vga_clk DRIVE = 8;
|
||||
|
||||
NET sys_vga_green<0> LOC = M22; # VGA_G0
|
||||
NET sys_vga_green<1> LOC = M23; # VGA_G1
|
||||
NET sys_vga_green<2> LOC = M20; # VGA_G2
|
||||
NET sys_vga_green<3> LOC = E4; # VGA_G3
|
||||
NET sys_vga_green<4> LOC = D3; # VGA_G4
|
||||
NET sys_vga_green<5> LOC = H7; # VGA_G5
|
||||
NET sys_vga_green<6> LOC = H8; # VGA_G6
|
||||
NET sys_vga_green<7> LOC = C1; # VGA_G7
|
||||
NET sys_vga_green<0> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_green<1> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_green<2> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_green<*> SLEW = FAST;
|
||||
NET sys_vga_green<*> DRIVE = 8;
|
||||
|
||||
NET sys_vga_hsync LOC = C10;
|
||||
NET sys_vga_hsync SLEW = FAST;
|
||||
NET sys_vga_hsync DRIVE = 8;
|
||||
#NET sys_vga_hsync IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET sys_vga_red<0> LOC = N23; #VGA_R0
|
||||
NET sys_vga_red<1> LOC = N24; #VGA_R1
|
||||
NET sys_vga_red<2> LOC = N25; #VGA_R2
|
||||
NET sys_vga_red<3> LOC = C2; #VGA_R3
|
||||
NET sys_vga_red<4> LOC = G7; #VGA_R4
|
||||
NET sys_vga_red<5> LOC = F7; #VGA_R5
|
||||
NET sys_vga_red<6> LOC = E5; #VGA_R6
|
||||
NET sys_vga_red<7> LOC = E6; #VGA_R7
|
||||
NET sys_vga_red<0> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_red<1> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_red<2> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_red<*> SLEW = FAST;
|
||||
NET sys_vga_red<*> DRIVE = 8;
|
||||
|
||||
NET sys_vga_vsync LOC = A8;
|
||||
NET sys_vga_vsync SLEW = FAST;
|
||||
NET sys_vga_vsync DRIVE = 8;
|
||||
#NET sys_vga_vsync IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET sys_vga_blank_n LOC = M24;
|
||||
NET sys_vga_blank_n SLEW = FAST;
|
||||
NET sys_vga_blank_n DRIVE = 8;
|
||||
NET sys_vga_blank_n IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET sys_vga_sync_n LOC = L23;
|
||||
NET sys_vga_sync_n SLEW = FAST;
|
||||
NET sys_vga_sync_n DRIVE = 8;
|
||||
NET sys_vga_sync_n IOSTANDARD = LVCMOS33;
|
||||
Reference in New Issue
Block a user