- Back to current work

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git-svn-id: http://moon:8086/svn/vhdl/trunk@775 cc03376c-175c-47c8-b038-4cd826a8556b

lib/CPUs/MIPS/dist/files.dist

@@ -1,8 +1,11 @@
 ../../../misc/dpram_2w2r.vhd
 ../../../misc/dpram_1w1r.vhd
 ../../../FIFO/src/fifo_ctrl_pkg.vhd
+../../../FIFO/src/gray_counter.vhd
 ../../../FIFO/src/fifo_sync_ctrl.vhd
 ../../../FIFO/src/fifo_sync.vhd
+../../../FIFO/src/fifo_async_ctrl.vhd
+../../../FIFO/src/fifo_async.vhd
 
 ../../../uart/bbfifo_16x8.vhd
 ../../../uart/kcuart_rx.vhd

lib/CPUs/MIPS/dist/mdist

@@ -2,7 +2,7 @@
 
 PROJECT="mips_sys"
 DIST_FILE="./files.dist"
-DIST_DIR="./release/mips.r12"
+DIST_DIR="./release/mips.r13"
 
 # ---------------------------------------------------------------
 mkdir -p $DIST_DIR/src

lib/CPUs/MIPS/dist/tmpl/mips_sys.vhd

@@ -200,6 +200,7 @@ inst_mips_top: entity work.mips_top
 		debug	=> debug,
 		nmi		=> nmi,
 		eb		=> eb,
+		cpu_clk	=> clk,
 		RST_I	=> rst,
 		CLK_I	=> clk,
 		ACK_I	=> ACK_I,

lib/CPUs/MIPS/dist/tmpl/notes.txt

@@ -1,3 +1,8 @@
+-----------------------------------------------------------------
+Changes in release 12
+-----------------------------------------------------------------
+- mips_biu.vhd: added asynchronous BUS-FIFOs to support different clocks for CPU and BUS
+
 -----------------------------------------------------------------
 Changes in release 12
 -----------------------------------------------------------------

lib/CPUs/MIPS/doc/J-MIPS.txt

@@ -15,6 +15,7 @@ J-MIPS Features
 - J-Bus kompatible Bus Interface Unit (J-Bus ist im wesentlichen FIFO interface mit 'wichtigen' Signalnamen)
 - 1,2 DMIPS/MHz mit 16Kbyte I/D-Cache (Dhrystone 2.1, GCC 4.3)
 - Endianness umschaltbar zur Hard-reset Zeit
+- Unterschiedliche Frequenzen für CPU und BUS möglich
 
 -----------------------------------------------------------------
 Known Limitations