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Minor changes to max cycle count

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git-svn-id: http://moon:8086/svn/vhdl/trunk@738 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-02-09 09:56:44 +00:00
parent b6dcc8cc48
commit 80dbbd7024
2 changed files with 6 additions and 6 deletions
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lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd
+3 -3
View File
@@ -57,7 +57,7 @@ architecture behaviour of sdram_cmd is
signal st_sdr, st_sdr_next : sdr_state_t;
signal cc_preset : natural range 0 to 10;
signal cc_preset : natural range 0 to 15;
signal cc_load_en : std_logic;
signal cycle_finished : std_logic;
@@ -65,7 +65,7 @@ architecture behaviour of sdram_cmd is
signal burst_load_en : std_logic;
signal burst_finished : std_logic;
subtype cycle_cnt_t is natural range 0 to 10;
subtype cycle_cnt_t is natural range 0 to 15;
type part_timing_array_t is array (sdr_cmd_t) of cycle_cnt_t;
constant TIMING : part_timing_array_t :=
@@ -249,7 +249,7 @@ fsm_sdr_state_next:
------------------------------------------------------------------------------------------
cycle_counter:
process (rst, clk)
variable cycle_cnt : natural range 0 to 10;
variable cycle_cnt : natural range 0 to 15;
begin
if rst = '1' then
cycle_cnt := 0;
lib/misc/async_port_wb.vhd
+3 -3
View File
@@ -1,5 +1,5 @@
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.15 2010-02-09 07:46:19 Jens Exp $
-- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.16 2010-02-09 09:56:37 Jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
@@ -57,8 +57,8 @@ architecture Behavioral of async_port_wb is
signal as : async_t;
signal ack : std_logic;
signal cc_rst : std_logic;
signal cycle_cnt : natural range 0 to 15;
signal cycle_reload : natural range 0 to 15;
signal cycle_cnt : natural range 0 to 31;
signal cycle_reload : natural range 0 to 31;
signal rdy : std_logic;
signal rdyo : std_logic;
signal en : std_logic;