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git-svn-id: http://moon:8086/svn/vhdl/trunk@796 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-03-16 21:00:16 +00:00
parent 2369919996
commit afcfc8c13a
3 changed files with 222 additions and 0 deletions
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lib/emac/sim/tb_emac_jb.fdo
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## NOTE: Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Thu Jul 06 20:49:07 Westeuropäische Sommerzeit 2006
##
vlib work
vcom -explicit -93 "../../misc/utils_pkg.vhd"
vcom -explicit -93 "../../misc/dpram_1w1r.vhd"
vcom -explicit -93 "../../FIFO/src/fifo_ctrl_pkg.vhd"
vcom -explicit -93 "../../FIFO/src/gray_counter.vhd"
vcom -explicit -93 "../../FIFO/src/fifo_async_ctrl.vhd"
vcom -explicit -93 "../../FIFO/src/fifo_async.vhd"
vcom -explicit -93 "../src/emac_jb.vhd"
vcom -explicit -93 "../src/tb_emac_jb.vhd"
vsim -t 1ps -lib work tb_emac_jb
view wave
do {tb_emac_jb.wdo}
view structure
view signals
run 20 us
lib/emac/sim/tb_emac_jb.wdo
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onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_emac_jb/clk
add wave -noupdate -format Logic /tb_emac_jb/rst
add wave -noupdate -format Logic /tb_emac_jb/cyc_i
add wave -noupdate -format Logic /tb_emac_jb/stb_i
add wave -noupdate -format Logic /tb_emac_jb/we_i
add wave -noupdate -format Literal /tb_emac_jb/sel_i
add wave -noupdate -format Logic /tb_emac_jb/ack_o
add wave -noupdate -format Logic /tb_emac_jb/int_o
add wave -noupdate -format Logic /tb_emac_jb/mrdy_i
add wave -noupdate -format Logic /tb_emac_jb/srdy_o
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/addr_i
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/dat_i
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/dat_o
add wave -noupdate -format Logic /tb_emac_jb/mii_rx_clk
add wave -noupdate -format Logic /tb_emac_jb/mii_tx_clk
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/mii_rx
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/mii_tx
add wave -noupdate -format Logic /tb_emac_jb/mii_rx_dv
add wave -noupdate -format Logic /tb_emac_jb/mii_rx_er
add wave -noupdate -format Logic /tb_emac_jb/mii_tx_en
add wave -noupdate -format Logic /tb_emac_jb/mii_tx_er
add wave -noupdate -format Logic /tb_emac_jb/mii_crs
add wave -noupdate -format Logic /tb_emac_jb/mii_col
add wave -noupdate -format Logic /tb_emac_jb/mii_gtx_clk
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_fifo_re
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_fifo_dout
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {9863780 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 100
configure wave -griddelta 40
configure wave -timeline 1
update
WaveRestoreZoom {0 ps} {10500 ns}
lib/emac/src/tb_emac_jb.vhd
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-------------------------------------------------------------------------
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-- This file: testbench for system test using Xilinx ML-402
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY tb_emac_jb IS
END tb_emac_jb;
ARCHITECTURE behavior OF tb_emac_jb IS
constant CLK_PERIOD : time := 10 ns;
constant MII_CLK_PERIOD : time := 40 ns;
signal CLK : std_logic := '1';
signal RST : std_logic := '1';
-- Slave
signal CYC_I : std_logic := '0';
signal STB_I : std_logic := '0';
signal WE_I : std_logic := '0';
signal SEL_I : unsigned(3 downto 0);
signal ACK_O : std_logic;
signal INT_O : std_logic;
signal MRDY_I : std_logic;
signal SRDY_O : std_logic;
signal ADDR_I : unsigned(31 downto 0) := (others => '-');
signal DAT_I : unsigned(31 downto 0) := (others => '-');
signal DAT_O : unsigned(31 downto 0) := (others => '-');
-- MII signals
signal mii_rx_clk_board : std_logic := '1';
signal mii_tx_clk_board : std_logic := '1';
signal mii_rx_clk : std_logic := '1';
signal mii_tx_clk : std_logic := '1';
signal mii_rx : unsigned(7 downto 0) := (others => '-');
signal mii_tx : unsigned(7 downto 0);
signal mii_rx_dv : std_logic := '0';
signal mii_rx_er : std_logic := '0';
signal mii_tx_en : std_logic;
signal mii_tx_er : std_logic;
signal mii_crs : std_logic := '0';
signal mii_col : std_logic := '0';
signal mii_gtx_clk : std_logic;
BEGIN
inst_emac_jb : entity work.emac_jb
GENERIC MAP
(
f_sysclk => 100.0
)
PORT MAP
(
CLK_I => CLK,
RST_I => RST,
INT_O => INT_O,
CYC_I => CYC_I,
STB_I => STB_I,
SEL_I => SEL_I,
WE_I => WE_I,
ACK_O => ACK_O,
SRDY_O => SRDY_O,
MRDY_I => MRDY_I,
ADDR_I => ADDR_I,
DAT_I => DAT_I,
DAT_O => DAT_O,
mii_rx_clk => mii_rx_clk_board,
mii_rx_dv => mii_rx_dv,
mii_rx_er => mii_rx_er,
mii_rx => mii_rx,
mii_tx_clk => mii_tx_clk_board,
mii_tx_en => mii_tx_en,
mii_tx_er => mii_tx_er,
mii_tx => mii_tx,
mii_gtx_clk => mii_gtx_clk,
mii_crs => mii_crs,
mii_col => mii_col
);
CLK_GEN: process
begin
wait for CLK_PERIOD/2;
CLK <= not CLK;
end process;
MII_CLK_GEN: process
begin
wait for MII_CLK_PERIOD/2;
mii_rx_clk <= not mii_rx_clk after 3000 ps;
mii_tx_clk <= not mii_tx_clk after 3000 ps;
end process;
mii_rx_clk_board <= mii_rx_clk after 3000 ps;
mii_tx_clk_board <= mii_tx_clk after 3000 ps;
-- Master
STIMULUS: process
begin
wait for 6*CLK_PERIOD;
RST <= '0';
wait for 60*CLK_PERIOD;
-- FILL TX data
CYC_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1';
DAT_I <= X"0000_0001";
ADDR_I <= X"0000_0008";
WE_I <= '1';
for i in 0 to 240 loop
STB_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1';
DAT_I <= DAT_I + 1;
end loop;
wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '0';
-- Trigger TX
CYC_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1';
DAT_I <= X"0000_0002";
STB_I <= '1';
WE_I <= '1';
ADDR_I <= X"0000_0000";
wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '0';
wait;
end process;
END;