jens d5254aa0d7 - writes have at least lead-in of one cycle if lead-in is speifified to 0 ...

- no data drive during lead-out
- no instant data drive in idle on 'en'
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git-svn-id: http://moon:8086/svn/vhdl/trunk@564 cc03376c-175c-47c8-b038-4cd826a8556b

2009-10-30 12:26:42 +00:00

Common

- Intital revision

2008-10-26 23:52:49 +00:00

lib

- writes have at least lead-in of one cycle if lead-in is speifified to 0

2009-10-30 12:26:42 +00:00

projects/mips_sys

- now 30 ns

2009-10-29 22:57:11 +00:00

S

Description

No description provided

23 MiB

Languages

VHDL 90.1%

Verilog 4.2%

Tcl 2.5%

SystemVerilog 0.8%

IGOR Pro 0.5%

Other 1.5%