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- added dedicated DPRAM for COEFFS

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git-svn-id: http://moon:8086/svn/vhdl/trunk@204 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-01-05 09:32:27 +00:00
parent 650e5db110
commit 9832fbfac9
1 changed files with 43 additions and 31 deletions
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lib/filter/src/fir_semi_parallel.vhd
+43 -31
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@@ -72,9 +72,6 @@ architecture Behavioral of fir_semi_parallel is
constant pipe_latency : natural := mul_latency + 1;
subtype coef_t is sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
type coef_stage_t is array (0 to nstages-1) of coef_t;
type coef_stage_array_t is array (0 to ntaps_per_stage-1) of coef_t;
type coef_array_t is array (0 to nstages-1) of coef_stage_array_t;
subtype count_t is natural range 0 to ntaps_per_stage-1;
type count_array_t is array (nstages-1 downto 0) of count_t;
@@ -82,8 +79,6 @@ architecture Behavioral of fir_semi_parallel is
type stage_array_t is array (0 to nstages) of stage_t;
signal count_array : count_array_t;
signal coef_array : coef_array_t;
signal coef_stage : coef_stage_t;
signal count0 : count_t;
signal ce0 : std_logic;
signal ce_array : unsigned(nstages downto 0);
@@ -100,6 +95,11 @@ architecture Behavioral of fir_semi_parallel is
signal accu_ld_pipe : unsigned(input_latency+coef_latency+pipe_latency downto 0);
signal din_r : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
signal coef_we : unsigned(nstages-1 downto 0);
type coef_array_t is array (0 to nstages-1) of unsigned(nbits_stages-1 downto 0);
signal coef_din : unsigned(nbits_stages-1 downto 0);
signal coef_dout : coef_array_t;
-------------------------------------------------------------------------------
begin
@@ -115,6 +115,8 @@ begin
accu_load <= accu_ld_pipe(accu_ld_pipe'left);
coef_din <= unsigned(h_in);
din_register:
process(clk)
begin
@@ -137,33 +139,14 @@ accu_load_pipe:
end if;
end process;
coef_write:
process(clk)
variable i : natural range 0 to nstages-1;
variable j : natural range 0 to ntaps_per_stage-1;
begin
if rising_edge(clk) then
i := to_integer(stage_addr);
j := to_integer(coef_addr(NextExpBaseTwo(ntaps_per_stage)-1 downto 0));
if h_we = '1' then
coef_array(i)(j) <= h_in;
end if;
end if;
end process;
coef_read:
process(clk)
coef_we_gen:
process(stage_addr)
variable i : natural range 0 to nstages-1;
begin
if rising_edge(clk) then
if en = '1' then
for i in 0 to nstages-1 loop
coef_stage(i) <= coef_array(i)(count_array(i));
end loop;
end if;
end if;
i := to_integer(stage_addr);
coef_we <= (others => '0');
coef_we(i) <= '1';
end process;
counter:
@@ -216,9 +199,38 @@ ce_pipe:
end if;
end process;
gen_coef_ram:
for i in 0 to nstages-1 generate
signal addr_a : unsigned (NextExpBaseTwo(ntaps_per_stage)-1 downto 0);
signal addr_b : unsigned (NextExpBaseTwo(ntaps_per_stage)-1 downto 0);
begin
addr_a <= coef_addr(addr_a'length-1 downto 0);
addr_b <= to_unsigned(count_array(i), addr_b'length);
inst_coef_ram: entity work.dpram_1w1r
GENERIC MAP
(
addr_width => NextExpBaseTwo(ntaps_per_stage),
data_width => nbits_stages
)
PORT MAP (
clka => clk,
clkb => clk,
en_a => '1',
en_b => en,
we_a => coef_we(i),
addr_a => addr_a,
addr_b => addr_b,
din_a => coef_din,
dout_b => coef_dout(i)
);
end generate;
gen_stages:
for i in 0 to nstages-1 generate
signal h_in : coef_t;
begin
h_in <= sfixed(coef_dout(i));
inst_fir_stage: entity work.fir_stage_sys
GENERIC MAP
(
@@ -236,7 +248,7 @@ gen_stages:
ce => en,
x_in => x(i+1),
y_in => y(i),
h_in => coef_stage(i),
h_in => h_in,
x_out => xo(i+1),
y_out => y(i+1)
);
@@ -274,7 +286,7 @@ acumulator:
elsif en = '1' then
dout_vld <= accu_load;
if accu_load = '1' then
dout <= resize(accu, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac));
dout <= resize(accu, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac));
accu <= y(nstages);
else
accu <= resize(accu + y(nstages), accu);