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- added unfiltered output at ddc for eval

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git-svn-id: http://moon:8086/svn/vhdl/trunk@214 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-01-09 11:50:40 +00:00
parent 5f40d70789
commit 8106295641
3 changed files with 33 additions and 23 deletions
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lib/radio/ddc/src/ddc.vhd
+7 -7
View File
@@ -50,9 +50,9 @@ ENTITY ddc IS
din_i : in sfixed;
din_q : in sfixed;
din_vld : in std_logic;
-- dec_i : out sfixed;
-- dec_q : out sfixed;
-- dec_vld : out std_logic;
dec_i : out sfixed;
dec_q : out sfixed;
dec_vld : out std_logic;
dout_i : out sfixed;
dout_q : out sfixed;
dout_vld : out std_logic
@@ -149,7 +149,7 @@ ARCHITECTURE behavior OF ddc IS
constant cic_nbits_out : integer := nbits_out+1;
constant cic_nbits_out_frac : integer := nbits_out_frac+1;
constant cfir_mul_latency : integer := 2;
constant cfir_mul_latency : integer := 5;
constant cfir_ntaps : integer := 63;
constant cfir_nstages : integer := 2;
constant cfir_nbits_in : integer := cic_nbits_out;
@@ -200,9 +200,9 @@ ARCHITECTURE behavior OF ddc IS
BEGIN
-- assert false report "cfir_h_addr_i'length = " & natural'image(cfir_h_addr_i'length) & "." severity note;
-- dec_vld <= dec_dout_vld_i and dec_dout_vld_q;
-- dec_i <= resize(dec_dout_i, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac), fixed_wrap, fixed_round);
-- dec_q <= resize(dec_dout_q, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac), fixed_wrap, fixed_round);
dec_vld <= dec_dout_vld_i and dec_dout_vld_q;
dec_i <= resize(dec_dout_i, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac), fixed_wrap, fixed_round);
dec_q <= resize(dec_dout_q, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac), fixed_wrap, fixed_round);
dout_vld <= cfir_vld_i and cfir_vld_q;
dout_i <= resize(cfir_dout_i, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac), fixed_wrap, fixed_round);
lib/radio/ddc/src/syn_ddc.vhd
+16 -6
View File
@@ -77,12 +77,15 @@ ARCHITECTURE behavior OF syn_ddc IS
lo_nco_en : in std_logic;
lo_freq_in : in unsigned(lo_nbits_freq-1 downto 0);
lo_phase_in : in unsigned(lo_nbits_phase-1 downto 0);
din_vld : in std_logic;
din_i : in sfixed;
din_q : in sfixed;
dec_vld : out std_logic;
dec_i : out sfixed;
dec_q : out sfixed;
dout_vld : out std_logic;
dout_i : out sfixed;
dout_q : out sfixed;
din_vld : in std_logic;
dout_vld : out std_logic
dout_q : out sfixed
);
END COMPONENT;
@@ -92,6 +95,10 @@ ARCHITECTURE behavior OF syn_ddc IS
SIGNAL ddc_dout_i : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
SIGNAL ddc_dout_q : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
SIGNAL dec_vld : std_logic;
SIGNAL ddc_dec_i : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
SIGNAL ddc_dec_q : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
BEGIN
-- Instantiate the Unit Under Test (UUT)
@@ -116,12 +123,15 @@ BEGIN
lo_nco_en => lo_nco_en,
lo_freq_in => lo_freq_in,
lo_phase_in => lo_phase_in,
din_vld => din_vld,
din_i => ddc_din_i,
din_q => ddc_din_q,
dec_vld => dec_vld,
dec_i => ddc_dec_i,
dec_q => ddc_dec_q,
dout_vld => dout_vld,
dout_i => ddc_dout_i,
dout_q => ddc_dout_q,
din_vld => din_vld,
dout_vld => dout_vld
dout_q => ddc_dout_q
);
ddc_din_i <= to_sfixed(din_i, ddc_din_i);
lib/radio/ddc/src/tb_ddc.vhd
+10 -10
View File
@@ -70,9 +70,9 @@ ARCHITECTURE behavior OF tb_ddc IS
din_i : in sfixed;
din_q : in sfixed;
din_vld : in std_logic;
-- dec_i : out sfixed;
-- dec_q : out sfixed;
-- dec_vld : out std_logic;
dec_i : out sfixed;
dec_q : out sfixed;
dec_vld : out std_logic;
dout_i : out sfixed;
dout_q : out sfixed;
dout_vld : out std_logic
@@ -109,10 +109,10 @@ ARCHITECTURE behavior OF tb_ddc IS
--Constants
constant fa : REAL := 100.0E6;
constant frf1 : REAL := 29.9E6;
constant frf2 : REAL := 30.0E6;
constant frf3 : REAL := 30.1E6;
constant flo : REAL := 30.0E6;
constant frf1 : REAL := 1.99E6;
constant frf2 : REAL := 1.00E6;
constant frf3 : REAL := 1.01E6;
constant flo : REAL := 1.00E6;
constant PERIOD : time := 10 ns;
SIGNAL rfgen1_freq_word : integer := integer(frf1/fa*2.0**rfgen_nbits_freq);
@@ -200,9 +200,9 @@ BEGIN
din_i => ddc_din_i,
din_q => ddc_din_q,
din_vld => ddc_din_vld,
-- dec_i => ddc_dec_i,
-- dec_q => ddc_dec_q,
-- dec_vld => ddc_dec_vld,
dec_i => ddc_dec_i,
dec_q => ddc_dec_q,
dec_vld => ddc_dec_vld,
dout_i => ddc_dout_i,
dout_q => ddc_dout_q,
dout_vld => ddc_dout_vld