Initial version
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Release 10.1.03 par K.39 (nt)
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Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
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JUPITER:: Sun Feb 07 20:01:09 2010
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par -w -intstyle ise -ol high -xe n -t 1 mips_sys_map.ncd mips_sys.ncd
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mips_sys.pcf
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Constraints file: mips_sys.pcf.
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Loading device for application Rf_Device from file '4vsx35.nph' in environment C:\Programme\Xilinx101\ISE.
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"mips_sys" is an NCD, version 3.2, device xc4vsx35, package ff668, speed -10
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The STEPPING level for this design is ES.
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Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
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Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
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Device speed data version: "PRODUCTION 1.68 2008-07-25".
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Device Utilization Summary:
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Number of BSCANs 1 out of 4 25%
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Number of BUFGs 12 out of 32 37%
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Number of DCM_ADVs 4 out of 8 50%
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Number of ILOGICs 99 out of 448 22%
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Number of External IOBs 226 out of 448 50%
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Number of LOCed IOBs 226 out of 226 100%
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Number of OLOGICs 182 out of 448 40%
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Number of RAMB16s 51 out of 192 26%
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Number of Slices 5888 out of 15360 38%
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Number of SLICEMs 561 out of 7680 7%
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Overall effort level (-ol): High
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Router effort level (-rl): High
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Starting initial Timing Analysis. REAL time: 14 secs
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Finished initial Timing Analysis. REAL time: 14 secs
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Starting Router
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Phase 1: 47772 unrouted; REAL time: 16 secs
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Phase 2: 40729 unrouted; REAL time: 16 secs
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Phase 3: 15700 unrouted; REAL time: 23 secs
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Phase 4: 15700 unrouted; (296275) REAL time: 23 secs
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Phase 5: 16428 unrouted; (12142) REAL time: 30 secs
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Phase 6: 16484 unrouted; (815) REAL time: 30 secs
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Phase 7: 0 unrouted; (10463) REAL time: 1 mins 3 secs
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Updating file: mips_sys.ncd with current fully routed design.
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Phase 8: 0 unrouted; (10463) REAL time: 2 mins 52 secs
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Phase 9: 0 unrouted; (6271) REAL time: 3 mins 5 secs
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Phase 10: 0 unrouted; (6221) REAL time: 3 mins 12 secs
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Phase 11: 0 unrouted; (6221) REAL time: 3 mins 12 secs
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Updating file: mips_sys.ncd with current fully routed design.
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Phase 12: 0 unrouted; (5742) REAL time: 4 mins 33 secs
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Phase 13: 0 unrouted; (5742) REAL time: 4 mins 48 secs
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Updating file: mips_sys.ncd with current fully routed design.
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Phase 14: 0 unrouted; (483) REAL time: 5 mins 13 secs
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Phase 15: 0 unrouted; (483) REAL time: 5 mins 18 secs
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Phase 16: 0 unrouted; (483) REAL time: 5 mins 23 secs
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Total REAL time to Router completion: 5 mins 26 secs
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Total CPU time to Router completion: 5 mins 11 secs
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Partition Implementation Status
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-------------------------------
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No Partitions were found in this design.
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-------------------------------
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Generating "PAR" statistics.
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**************************
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Generating Clock Report
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**************************
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+---------------------+--------------+------+------+------------+-------------+
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| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
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+---------------------+--------------+------+------+------------+-------------+
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| cpu_clk |BUFGCTRL_X0Y12| No | 1616 | 0.434 | 4.046 |
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+---------------------+--------------+------+------+------------+-------------+
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| CLK_O | BUFGCTRL_X0Y2| No | 2299 | 0.544 | 3.933 |
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+---------------------+--------------+------+------+------------+-------------+
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| vga_clk |BUFGCTRL_X0Y11| No | 170 | 0.400 | 3.881 |
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+---------------------+--------------+------+------+------------+-------------+
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| sys_clk_in_IBUFG | BUFGCTRL_X0Y1| No | 67 | 0.241 | 3.697 |
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+---------------------+--------------+------+------+------------+-------------+
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| sdram_clk0 |BUFGCTRL_X0Y31| No | 237 | 0.383 | 3.933 |
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+---------------------+--------------+------+------+------------+-------------+
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|inst_rom_wb/inst_rom | | | | | |
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| /bs_clk1 | BUFGCTRL_X0Y0| No | 71 | 0.159 | 3.562 |
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+---------------------+--------------+------+------+------------+-------------+
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|sys_ac97_bit_clk_IBU | | | | | |
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| F | BUFGCTRL_X0Y8| No | 253 | 0.397 | 3.865 |
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+---------------------+--------------+------+------+------------+-------------+
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| sdram_clk270 |BUFGCTRL_X0Y16| No | 66 | 0.173 | 3.932 |
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+---------------------+--------------+------+------+------------+-------------+
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| sdram_clk270var |BUFGCTRL_X0Y28| No | 32 | 0.025 | 3.930 |
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+---------------------+--------------+------+------+------------+-------------+
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|inst_rom_wb/inst_rom | | | | | |
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| /bs_update1 |BUFGCTRL_X0Y26| No | 4 | 0.035 | 3.487 |
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+---------------------+--------------+------+------+------------+-------------+
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* Net Skew is the difference between the minimum and maximum routing
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only delays for the net. Note this is different from Clock Skew which
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is reported in TRCE timing report. Clock Skew is the difference between
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the minimum and maximum path delays which includes logic delays.
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Timing Score: 483
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WARNING:Par:62 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in
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your design.
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Review the timing report using Timing Analyzer (In ISE select "Post-Place &
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Route Static Timing Report"). Go to the failing constraint(s) and select
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the "Timing Improvement Wizard" link for suggestions to correct each problem.
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Try the Design Goal and Strategies for Timing Performance (In ISE select Project -> Design Goals & Strategies) to
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ensure the best options are set in the tools for timing closure.
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Use the Xilinx "SmartXplorer" script to try special combinations of
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options known to produce very good results.
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INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no
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requested value.
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Asterisk (*) preceding a constraint indicates it was not met.
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This may be due to a setup or hold violation.
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------------------------------------------------------------------------------------------------------
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Constraint | Check | Worst Case | Best Case | Timing | Timing
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| | Slack | Achievable | Errors | Score
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------------------------------------------------------------------------------------------------------
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* TS_cpu_clk = PERIOD TIMEGRP "cpu_clk" 9.9 | SETUP | -0.118ns| 10.018ns| 5| 483
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ns HIGH 50% | HOLD | 0.383ns| | 0| 0
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------------------------------------------------------------------------------------------------------
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TS_vga_clk = PERIOD TIMEGRP "vga_clk" 8 n | SETUP | 0.010ns| 7.990ns| 0| 0
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s HIGH 50% | HOLD | 0.508ns| | 0| 0
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------------------------------------------------------------------------------------------------------
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TS_sdram_clk = PERIOD TIMEGRP "sdram_clk" | SETUP | 0.072ns| 7.356ns| 0| 0
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7.5 ns HIGH 50% | HOLD | 0.515ns| | 0| 0
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------------------------------------------------------------------------------------------------------
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TS_clk = PERIOD TIMEGRP "sys_clk" 9.9 ns | SETUP | 0.164ns| 9.736ns| 0| 0
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HIGH 50% | HOLD | 0.326ns| | 0| 0
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------------------------------------------------------------------------------------------------------
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NET "sys_ac97_bit_clk_IBUF1" PERIOD = 80 | SETUP | 36.549ns| 6.902ns| 0| 0
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ns HIGH 50% | HOLD | 0.480ns| | 0| 0
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------------------------------------------------------------------------------------------------------
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TSACBITCLK = PERIOD TIMEGRP "ac97_clk" 80 | SETUP | 74.795ns| 5.205ns| 0| 0
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ns HIGH 50% | HOLD | 0.824ns| | 0| 0
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------------------------------------------------------------------------------------------------------
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PATH "TS_unrelate_SDRAM_path" TIG | SETUP | N/A| 9.446ns| N/A| 0
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------------------------------------------------------------------------------------------------------
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PATH "TS_unrelate_VGA_path" TIG | SETUP | N/A| 6.486ns| N/A| 0
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------------------------------------------------------------------------------------------------------
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PATH "TS_unrelate_CPU_path" TIG | MAXDELAY| N/A| 8.192ns| N/A| 0
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------------------------------------------------------------------------------------------------------
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1 constraint not met.
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INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
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constraint does not cover any paths or that it has no requested value.
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Generating Pad Report.
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All signals are completely routed.
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Total REAL time to PAR completion: 5 mins 35 secs
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Total CPU time to PAR completion: 5 mins 17 secs
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Peak Memory Usage: 418 MB
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Placer: Placement generated during map.
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Routing: Completed - No errors found.
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Timing: Completed - 5 errors found.
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Number of error messages: 0
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Number of warning messages: 1
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Number of info messages: 1
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Writing design to file mips_sys.ncd
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PAR done!
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
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