- added to_01() to timer counter, to avoid simulation warnings

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git-svn-id: http://moon:8086/svn/vhdl/trunk@755 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
2010-02-17 10:54:19 +00:00
parent 943e7e9388
commit 359869bc2d
+3 -3
View File
@@ -42,7 +42,7 @@ ARCHITECTURE behavior OF gpio_wb IS
signal gpi1_reg : unsigned(31 downto 0);
-- Signals to form an timer generating an interrupt every microsecond
subtype tick_usec_t is natural range 0 to ncycles_usec-1;
signal tick_usec : tick_usec_t;
signal tick_usec : tick_usec_t := 0;
signal cnt_usec : unsigned(31 downto 0);
signal cnt_sec : unsigned(31 downto 0);
signal cnt_usec_preset : unsigned(31 downto 0);
@@ -256,7 +256,7 @@ cnt_usec_clock:
if cnt_usec_we = '1' then
cnt_usec <= reg_data_wr;
elsif cnt_usec_en = '1' then
if cnt_usec >= to_unsigned(1E6 - 1, 32) then
if to_01(cnt_usec) >= to_unsigned(1E6 - 1, 32) then
cnt_usec <= (others => '0');
cnt_sec_en <= '1';
else
@@ -293,7 +293,7 @@ proc_int_timer:
elsif timer_cnt_we(i) = '1' then
timer_cnt(i) <= reg_data_wr;
elsif timer_en(i) = '1' then
if timer_cnt(i) >= timer_cmp(i) then
if to_01(timer_cnt(i)) >= timer_cmp(i) then
timer_cnt(i) <= (others => '0');
if timer_inten(i) = '1' then
if timer_irq(i) = '1' then