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- removed unused 'en' pin.

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git-svn-id: http://moon:8086/svn/vhdl/trunk@680 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-11-24 11:30:36 +00:00
parent c0592b8ef4
commit 3eef19bb28
2 changed files with 49 additions and 5 deletions
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lib/CPUs/MIPS/src/core/dcache.vhd
+25 -3
View File
@@ -1,3 +1,26 @@
--------------------------------------------------------------------------
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
-- This file: JIPS top file
--
-- Copyright (C) 2008 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
@@ -22,7 +45,6 @@ ENTITY dcache IS
STB_O : out STD_LOGIC;
CYC_O : out STD_LOGIC;
ctrl : in cache_ctrl_t;
en : in STD_LOGIC;
cpu_en : in STD_LOGIC;
cpu_we : in STD_LOGIC;
cpu_be : in unsigned(3 downto 0);
@@ -216,7 +238,7 @@ cpu_request_register:
if RST_I = '1' then
cpu_we_reg <= '0';
cache_req <= '0';
elsif cpu_en = '1' and en = '1' then
elsif cpu_en = '1' then
if cache_busy = '0' then
cpu_we2 <= cpu_we;
cache_req <= '1';
@@ -237,7 +259,7 @@ instant_raw_logic:
if rising_edge(CLK_I) then
instant_raw <= '0';
if cpu_word_index = word_index_reg then
instant_raw <= cpu_hit_we and cpu_en and en and not cpu_we;
instant_raw <= cpu_hit_we and cpu_en and not cpu_we;
end if;
end if;
end process;
lib/CPUs/MIPS/src/core/icache.vhd
+24 -2
View File
@@ -1,3 +1,26 @@
--------------------------------------------------------------------------
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
-- This file: JIPS top file
--
-- Copyright (C) 2008 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
@@ -22,7 +45,6 @@ ENTITY icache IS
STB_O : out STD_LOGIC;
CYC_O : out STD_LOGIC;
ctrl : in cache_ctrl_t;
en : in STD_LOGIC;
cpu_en : in STD_LOGIC;
cpu_addr : in word_t;
cpu_dout : out word_t;
@@ -212,7 +234,7 @@ cpu_request_register:
cache_req <= '0';
elsif cpu_en = '1' then
if cache_busy = '0' then
cache_req <= en;
cache_req <= '1';
end if;
elsif cache_ack = '1' then
cache_req <= '0';