- cleaned up
Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@753 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -21,6 +21,13 @@ add wave -noupdate -format Logic /tb_mips_top/uut/biu_rst
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add wave -noupdate -format Logic /tb_mips_top/uut/cpu_rst
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add wave -noupdate -format Logic /tb_mips_top/uut/cpu_run
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add wave -noupdate -divider BIU
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/bout_fifo_din
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/bout_fifo_dout
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add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bout_fifo_re
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add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bout_fifo_we
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add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bout_fifo_full
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add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bout_fifo_empty
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add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bout_rdy
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add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/bus_timeout_cnt
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add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bus_timeout
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add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/cpu_imem_err
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@@ -51,7 +58,6 @@ add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/write_fifo_re
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add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/write_fifo_we
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add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/write_fifo_full
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add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/write_fifo_empty
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add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/write_busy
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add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/read_cycle
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add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/dcached
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add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/dcache_en2
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@@ -158,27 +164,32 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/
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add wave -noupdate -format Logic /tb_mips_top/clk
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add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cpu_en
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cpu_addr
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/request_addr
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/fill_addr
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cpu_dout
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add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cpu_busy
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add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/s
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add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cache_busy
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add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cache_miss
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add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/tag_match
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/word_index_reg
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cache_index_reg
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add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/was_miss
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add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/cache_entry_out
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add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/request_count
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add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/fill_count
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add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cache_req
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add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cache_ack
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add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/inst_tag_ram/ram
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add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/inst_tag_ram/addr_a
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add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/inst_tag_ram/addr_b
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add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/inst_tag_ram/din_a
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add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/inst_tag_ram/din_b
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add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/inst_tag_ram/dout_a
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add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/inst_tag_ram/dout_b
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/data_ram_addr_rd
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/data_ram_data_rd
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/data_ram_addr_wr
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/data_ram_data_wr
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add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/data_ram_we
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/inst_tag_ram/ram
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/inst_tag_ram/addr_a
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/inst_tag_ram/addr_b
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/inst_tag_ram/din_a
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/inst_tag_ram/din_b
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/inst_tag_ram/dout_a
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/inst_tag_ram/dout_b
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add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/inst_tag_ram/we_a
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add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/inst_tag_ram/we_b
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add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/inst_tag_ram/en_b
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@@ -195,25 +206,24 @@ add wave -noupdate -format Logic /tb_mips_top/clk
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add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_biu/inst_dcache/ctrl
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo0
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo1
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/request_addr
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/fill_addr
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add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/dcached
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add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_busy
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add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_en
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add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_we
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add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_be
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_addr
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_din
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_dout
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add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_busy
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add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cache_hit
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add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cache_busy
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add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/was_miss
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add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_hit_we
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add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/instant_raw
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add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/s
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_addr
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_din
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_dout
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add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_biu/inst_dcache/cache_entry_out
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add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/tag_match
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/tag_reg
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/word_index_reg
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/addr_windex_reg
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cache_index_reg
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add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/fill_count
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add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/fill_count_en
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add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/fill_count_rdy
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@@ -238,7 +248,7 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_cache_index
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add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_word_index
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 1} {2763568773 ps} 0} {{Cursor 2} {107733 ps} 0}
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WaveRestoreCursors {{Cursor 1} {12375000 ps} 0} {{Cursor 2} {3884295000 ps} 0}
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configure wave -namecolwidth 188
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configure wave -valuecolwidth 100
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configure wave -justifyvalue left
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@@ -252,4 +262,4 @@ configure wave -gridperiod 100
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configure wave -griddelta 40
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configure wave -timeline 1
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update
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WaveRestoreZoom {0 ps} {4200 us}
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WaveRestoreZoom {3856155513 ps} {4007570763 ps}
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@@ -99,9 +99,10 @@ COMPONENT dpram_2w2r is
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);
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END COMPONENT;
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constant addr_width : natural := 32;
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constant word_index_width : natural := lg2(line_size);
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constant cache_index_width : natural := lg2(cache_size) - word_index_width;
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constant tag_width : natural := 32 - word_index_width - cache_index_width - 2;
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constant tag_width : natural := addr_width - word_index_width - cache_index_width - 2;
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constant tag_parity_width : natural := 3;
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constant tag_ram_data_width : natural := 1 + tag_parity_width + tag_width;
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constant tag_ram_addr_width : natural := cache_index_width;
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@@ -114,10 +115,6 @@ END COMPONENT;
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tag : unsigned(tag_width-1 downto 0);
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end record;
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alias cpu_word_index is cpu_addr(word_index_width+1 downto 2);
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alias cpu_cache_index is cpu_addr(cache_index_width+word_index_width+1 downto word_index_width+2);
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alias cpu_tag is cpu_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2);
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function to_dcache_entry(x : tag_ram_data_t) return dcache_entry_t is
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variable result : dcache_entry_t;
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begin
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@@ -148,11 +145,11 @@ END COMPONENT;
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signal tag_match : std_logic;
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signal cache_hit_inv : std_logic;
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signal tag_match_inv : std_logic;
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signal word_index_reg : unsigned(word_index_width-1 downto 0);
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signal addr_windex_reg : unsigned(word_index_width-1 downto 0);
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signal cache_index_reg : unsigned(cache_index_width-1 downto 0);
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signal request_addr : unsigned(addr_width-1 downto 0);
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signal fill_addr : unsigned(addr_width-1 downto 0);
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signal cache_index_inv : unsigned(cache_index_width-1 downto 0);
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signal tag_reg : unsigned(tag_width-1 downto 0);
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signal tag_inv : unsigned(tag_width-1 downto 0);
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signal tag_reg_inv : unsigned(tag_width-1 downto 0);
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@@ -194,6 +191,18 @@ END COMPONENT;
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signal cpu_hit_we : std_logic;
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signal instant_raw : std_logic;
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alias cpu_word_index is cpu_addr(word_index_width+1 downto 2);
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alias cpu_cache_index is cpu_addr(cache_index_width+word_index_width+1 downto word_index_width+2);
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alias cpu_tag is cpu_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2);
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alias fill_word_index is fill_addr(word_index_width+1 downto 2);
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alias fill_cache_index is fill_addr(cache_index_width+word_index_width+1 downto word_index_width+2);
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alias fill_tag is fill_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2);
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alias req_word_index is request_addr(word_index_width+1 downto 2);
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alias req_cache_index is request_addr(cache_index_width+word_index_width+1 downto word_index_width+2);
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alias req_tag is request_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2);
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begin
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cache_index_inv <= ctrl.inv_addr(cache_index_width+word_index_width+1 downto word_index_width+2);
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@@ -201,32 +210,30 @@ begin
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cpu_hit_we <= cpu_we2 and cache_hit;
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cpu_index_register:
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fill_address_register:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if fill_count_en = '1' then
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if ACK_I = '1' then
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word_index_reg <= word_index_reg + 1;
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fill_word_index <= fill_word_index + 1;
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end if;
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elsif cache_busy = '0' then
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word_index_reg <= cpu_word_index;
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cache_index_reg <= cpu_cache_index;
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tag_reg <= cpu_tag;
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fill_addr <= cpu_addr(addr_width-1 downto 2) & "00";
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end if;
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end if;
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end process;
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addr_windex_register:
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request_address_register:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if request_count_en = '1'then
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if SRDY_I = '1' then
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addr_windex_reg <= addr_windex_reg + 1;
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req_word_index <= req_word_index + 1;
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end if;
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elsif cache_busy = '0' then
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addr_windex_reg <= cpu_word_index;
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request_addr <= cpu_addr(addr_width-1 downto 2) & "00";
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end if;
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end if;
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end process;
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@@ -258,7 +265,7 @@ instant_raw_logic:
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begin
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if rising_edge(CLK_I) then
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instant_raw <= '0';
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if cpu_word_index = word_index_reg then
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if cpu_word_index = fill_word_index then
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instant_raw <= cpu_hit_we and cpu_en and not cpu_we;
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end if;
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end if;
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@@ -342,28 +349,29 @@ cache_state_next:
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end if;
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end process;
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ADDR_O <= request_addr;
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cpu_busy <= cache_busy;
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cpu_dout <= cpu_data_ram_dout;
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tag_match <= '1' when tag_reg = cache_entry_out.tag else '0';
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tag_match <= '1' when fill_tag = cache_entry_out.tag else '0';
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cache_hit <= tag_match and cache_entry_out.valid;
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tag_match_inv <= '1' when tag_reg_inv = cache_entry_out_inv.tag else '0';
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cache_hit_inv <= tag_match_inv and cache_entry_out_inv.valid;
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tag_ram_din <= to_tag_ram_data(cache_entry_in);
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tag_ram_addr_wr <= to_unsigned(flush_count, cache_index_width) when invalidate_en = '1' else cache_index_reg;
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tag_ram_addr_rd <= cpu_cache_index when (was_miss = '0' and instant_raw = '0') else cache_index_reg;
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tag_ram_addr_wr <= to_unsigned(flush_count, cache_index_width) when invalidate_en = '1' else fill_cache_index;
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tag_ram_addr_rd <= cpu_cache_index when (was_miss = '0' and instant_raw = '0') else fill_cache_index;
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cache_entry_out <= to_dcache_entry(tag_ram_dout);
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cache_entry_out_inv <= to_dcache_entry(tag_ram_dout_inv);
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cpu_data_ram_addr <= (cpu_cache_index & cpu_word_index) when (was_miss = '0' and instant_raw = '0' and fill_count_en = '0') else (cache_index_reg & word_index_reg);
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ADDR_O <= tag_reg & cache_index_reg & addr_windex_reg & "00";
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ctrl_data_ram_addr <= cache_index_reg & word_index_reg;
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cpu_data_ram_addr <= (cpu_cache_index & cpu_word_index) when (was_miss = '0' and instant_raw = '0' and fill_count_en = '0') else (fill_cache_index & fill_word_index);
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ctrl_data_ram_addr <= fill_cache_index & fill_word_index;
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ctrl_data_ram_we <= (others => fill_count_en and ACK_I);
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cpu_data_ram_we <= cpu_be_reg when (cpu_hit_we = '1') else (others => '0');
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cache_state:
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process(s, cache_req, instant_raw, cache_hit, cache_hit_inv, flush_count_rdy, fill_count_rdy, request_count_rdy, tag_reg, SRDY_I, cpu_we_reg, invalidate_req, invalidate_all)
|
||||
process(s, cache_req, instant_raw, cache_hit, cache_hit_inv, flush_count_rdy, fill_count_rdy, request_count_rdy, fill_tag, SRDY_I, cpu_we_reg, invalidate_req, invalidate_all)
|
||||
begin
|
||||
cache_busy <= cache_req;
|
||||
cache_ack <= '0';
|
||||
@@ -379,7 +387,7 @@ cache_state:
|
||||
invalidate_ack <= '0';
|
||||
|
||||
cache_entry_in.tv_p <= (others => '0');
|
||||
cache_entry_in.tag <= tag_reg;
|
||||
cache_entry_in.tag <= fill_tag;
|
||||
cache_entry_in.valid <= '0';
|
||||
sn <= s;
|
||||
|
||||
|
||||
@@ -96,9 +96,10 @@ COMPONENT dpram_2w2r is
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
constant addr_width : natural := 32;
|
||||
constant word_index_width : natural := lg2(line_size);
|
||||
constant cache_index_width : natural := lg2(cache_size) - word_index_width;
|
||||
constant tag_width : natural := 32 - word_index_width - cache_index_width - 2;
|
||||
constant tag_width : natural := addr_width - word_index_width - cache_index_width - 2;
|
||||
constant tag_parity_width : natural := 3;
|
||||
constant tag_ram_data_width : natural := 1 + tag_parity_width + tag_width;
|
||||
constant tag_ram_addr_width : natural := cache_index_width;
|
||||
@@ -111,10 +112,6 @@ END COMPONENT;
|
||||
tag : unsigned(tag_width-1 downto 0);
|
||||
end record;
|
||||
|
||||
alias cpu_word_index is cpu_addr(word_index_width+1 downto 2);
|
||||
alias cpu_cache_index is cpu_addr(cache_index_width+word_index_width+1 downto word_index_width+2);
|
||||
alias cpu_tag is cpu_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2);
|
||||
|
||||
function to_icache_entry(x : tag_ram_data_t) return icache_entry_t is
|
||||
variable result : icache_entry_t;
|
||||
begin
|
||||
@@ -145,11 +142,10 @@ END COMPONENT;
|
||||
signal tag_match : std_logic;
|
||||
signal cache_miss_inv : std_logic;
|
||||
signal tag_match_inv : std_logic;
|
||||
signal word_index_reg : unsigned(word_index_width-1 downto 0);
|
||||
signal addr_windex_reg : unsigned(word_index_width-1 downto 0);
|
||||
signal cache_index_reg : unsigned(cache_index_width-1 downto 0);
|
||||
signal request_addr : unsigned(addr_width-1 downto 0);
|
||||
signal fill_addr : unsigned(addr_width-1 downto 0);
|
||||
|
||||
signal cache_index_inv : unsigned(cache_index_width-1 downto 0);
|
||||
signal tag_reg : unsigned(tag_width-1 downto 0);
|
||||
signal tag_inv : unsigned(tag_width-1 downto 0);
|
||||
signal tag_reg_inv : unsigned(tag_width-1 downto 0);
|
||||
|
||||
@@ -186,6 +182,18 @@ END COMPONENT;
|
||||
signal invalidate_en : std_logic;
|
||||
signal invalidate_req : std_logic;
|
||||
|
||||
alias cpu_word_index is cpu_addr(word_index_width+1 downto 2);
|
||||
alias cpu_cache_index is cpu_addr(cache_index_width+word_index_width+1 downto word_index_width+2);
|
||||
alias cpu_tag is cpu_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2);
|
||||
|
||||
alias fill_word_index is fill_addr(word_index_width+1 downto 2);
|
||||
alias fill_cache_index is fill_addr(cache_index_width+word_index_width+1 downto word_index_width+2);
|
||||
alias fill_tag is fill_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2);
|
||||
|
||||
alias req_word_index is request_addr(word_index_width+1 downto 2);
|
||||
alias req_cache_index is request_addr(cache_index_width+word_index_width+1 downto word_index_width+2);
|
||||
alias req_tag is request_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2);
|
||||
|
||||
begin
|
||||
|
||||
ram_read_en <= cpu_en or was_miss;
|
||||
@@ -193,35 +201,30 @@ begin
|
||||
tag_inv <= ctrl.inv_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2);
|
||||
|
||||
|
||||
cpu_index_reg:
|
||||
fill_address_register:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if RST_I = '1' then
|
||||
cache_index_reg <= (others => '0');
|
||||
tag_reg <= (others => '0');
|
||||
elsif fill_count_en = '1' then
|
||||
if fill_count_en = '1' then
|
||||
if ACK_I = '1' then
|
||||
word_index_reg <= word_index_reg + 1;
|
||||
fill_word_index <= fill_word_index + 1;
|
||||
end if;
|
||||
elsif cache_busy = '0' then
|
||||
word_index_reg <= cpu_word_index;
|
||||
cache_index_reg <= cpu_cache_index;
|
||||
tag_reg <= cpu_tag;
|
||||
fill_addr <= cpu_addr(addr_width-1 downto 2) & "00";
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
addr_windex_register:
|
||||
request_address_register:
|
||||
process(CLK_I)
|
||||
begin
|
||||
if rising_edge(CLK_I) then
|
||||
if request_count_en = '1'then
|
||||
if SRDY_I = '1' then
|
||||
addr_windex_reg <= addr_windex_reg + 1;
|
||||
req_word_index <= req_word_index + 1;
|
||||
end if;
|
||||
elsif cache_busy = '0' then
|
||||
addr_windex_reg <= cpu_word_index;
|
||||
request_addr <= cpu_addr(addr_width-1 downto 2) & "00";
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
@@ -310,12 +313,12 @@ cache_state_next:
|
||||
end if;
|
||||
end process;
|
||||
|
||||
ADDR_O <= tag_reg & cache_index_reg & addr_windex_reg & "00";
|
||||
ADDR_O <= fill_tag & fill_cache_index & req_word_index & "00";
|
||||
cpu_busy <= cache_busy;
|
||||
cpu_dout <= data_ram_data_rd;
|
||||
|
||||
cache_entry_out <= to_icache_entry(tag_ram_data_rd);
|
||||
tag_match <= '1' when tag_reg = cache_entry_out.tag else '0';
|
||||
tag_match <= '1' when fill_tag = cache_entry_out.tag else '0';
|
||||
cache_miss <= not (tag_match and cache_entry_out.valid);
|
||||
|
||||
cache_entry_out_inv <= to_icache_entry(tag_ram_data_rd_inv);
|
||||
@@ -323,15 +326,15 @@ cache_state_next:
|
||||
cache_miss_inv <= not (tag_match_inv and cache_entry_out_inv.valid);
|
||||
|
||||
tag_ram_data_wr <= to_tag_ram_data(cache_entry_in);
|
||||
tag_ram_addr_wr <= to_unsigned(flush_count, cache_index_width) when invalidate_en = '1' else cache_index_reg;
|
||||
tag_ram_addr_rd <= cpu_cache_index when was_miss = '0' else cache_index_reg;
|
||||
data_ram_addr_rd <= (cpu_cache_index & cpu_word_index) when was_miss = '0' else (cache_index_reg & word_index_reg);
|
||||
data_ram_addr_wr <= cache_index_reg & word_index_reg;
|
||||
tag_ram_addr_wr <= to_unsigned(flush_count, cache_index_width) when invalidate_en = '1' else fill_cache_index;
|
||||
tag_ram_addr_rd <= cpu_cache_index when was_miss = '0' else fill_cache_index;
|
||||
data_ram_addr_rd <= (cpu_cache_index & cpu_word_index) when was_miss = '0' else (fill_cache_index & fill_word_index);
|
||||
data_ram_addr_wr <= fill_cache_index & fill_word_index;
|
||||
data_ram_data_wr <= DAT_I;
|
||||
data_ram_we <= fill_count_en and ACK_I;
|
||||
|
||||
cache_state:
|
||||
process(s, cache_req, cache_miss, cache_miss_inv, flush_count_rdy, fill_count_rdy, request_count_rdy, tag_reg, SRDY_I, invalidate_req, invalidate_all)
|
||||
process(s, cache_req, cache_miss, cache_miss_inv, flush_count_rdy, fill_count_rdy, request_count_rdy, fill_tag, SRDY_I, invalidate_req, invalidate_all)
|
||||
begin
|
||||
cache_busy <= cache_req;
|
||||
cache_ack <= '0';
|
||||
@@ -347,7 +350,7 @@ cache_state:
|
||||
invalidate_ack <= '0';
|
||||
|
||||
cache_entry_in.tv_p <= (others => '0');
|
||||
cache_entry_in.tag <= tag_reg;
|
||||
cache_entry_in.tag <= fill_tag;
|
||||
cache_entry_in.valid <= '0';
|
||||
sn <= s;
|
||||
|
||||
|
||||
Reference in New Issue
Block a user