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- made time specs in nano seconds

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git-svn-id: http://moon:8086/svn/vhdl/trunk@722 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-02-07 15:53:23 +00:00
parent 149140cad7
commit f42e562e14
4 changed files with 26 additions and 26 deletions
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lib/SDRAM/ddr_sdr_v1_5/src/sdram_config.vhd
+7 -7
View File
@@ -54,18 +54,18 @@ package sdram_config is
-- DDR-SDR TIMING constants ------------------------------------------------------------------
-- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh
constant REFRESH_INTERVAL : real := 7.8125E-6; -- [s]
constant REFRESH_INTERVAL : real := 7.8125E3; -- [ns]
-- These values are for your SDRAM part (see datasheet)
constant TCAS : positive := 2; -- CAS latency [clocks]
constant TRP : real := 20.0E-9; -- precharge command period [s]
constant TRAS : real := 45.0E-9; -- active to precharge delay [s]
constant TRFC : real := 75.0E-9; -- auto refresh command period [s]
constant TRP : real := 20.0; -- precharge command period [ns]
constant TRAS : real := 45.0; -- active to precharge delay [ns]
constant TRFC : real := 75.0; -- auto refresh command period [ns]
constant TMRD : positive := 2; -- load mode register command cylce time [clocks]
constant TRCD : real := 20.0E-9; -- active to read or write delay [s]
constant TWR : real := 15.0E-9; -- write recovery time [s]
constant TRCD : real := 20.0; -- active to read or write delay [ns]
constant TWR : real := 15.0; -- write recovery time [ns]
constant PWR_UP_WAIT : real := 1.0E-6; -- [s]
constant PWR_UP_WAIT : real := 1.0E3; -- [ns]
subtype user_tag_t is unsigned(3 downto 0);
lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd
+3 -3
View File
@@ -113,16 +113,16 @@ package sdram_types is
wait_cycle : natural;
end record init_seq_t;
function to_cycles(T_s : real; f_hz : natural) return natural;
function to_cycles(T_ns : real; f_hz : natural) return natural;
end sdram_types;
package body sdram_types is
function to_cycles(T_s : real; f_hz : natural) return natural is
function to_cycles(T_ns : real; f_hz : natural) return natural is
begin
return natural(0.5 + T_s*real(f_hz));
return natural(0.5 + 1.0E-9*T_ns*real(f_hz));
end to_cycles;
projects/mips_sys/src/sdram_config.vhd
+8 -8
View File
@@ -54,18 +54,18 @@ package sdram_config is
-- DDR-SDR TIMING constants ------------------------------------------------------------------
-- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh
constant REFRESH_INTERVAL : real := 7.8125E-6; -- [s]
constant REFRESH_INTERVAL : real := 7.8125E3; -- [ns]
-- These values are for your SDRAM part (see datasheet)
constant TCAS : positive := 2; -- CAS latency [clocks]
constant TRP : real := 20.0E-9; -- precharge command period [s]
constant TRAS : real := 45.0E-9; -- active to precharge delay [s]
constant TRFC : real := 75.0E-9; -- auto refresh command period [s]
constant TCAS : positive := 2; -- CAS latency [clocks]
constant TRP : real := 20.0; -- precharge command period [ns]
constant TRAS : real := 45.0; -- active to precharge delay [ns]
constant TRFC : real := 75.0; -- auto refresh command period [ns]
constant TMRD : positive := 2; -- load mode register command cylce time [clocks]
constant TRCD : real := 20.0E-9; -- active to read or write delay [s]
constant TWR : real := 15.0E-9; -- write recovery time [s]
constant TRCD : real := 20.0; -- active to read or write delay [ns]
constant TWR : real := 15.0; -- write recovery time [ns]
constant PWR_UP_WAIT : real := 220.0E-6; -- [s]
constant PWR_UP_WAIT : real := 220.0E3; -- [ns]
subtype user_tag_t is unsigned(3 downto 0);
projects/mips_sys/src/sdram_config_sim.vhd
+8 -8
View File
@@ -54,18 +54,18 @@ package sdram_config is
-- DDR-SDR TIMING constants ------------------------------------------------------------------
-- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh
constant REFRESH_INTERVAL : real := 7.8125E-6; -- [s]
constant REFRESH_INTERVAL : real := 7.8125E3; -- [ns]
-- These values are for your SDRAM part (see datasheet)
constant TCAS : positive := 2; -- CAS latency [clocks]
constant TRP : real := 20.0E-9; -- precharge command period [s]
constant TRAS : real := 45.0E-9; -- active to precharge delay [s]
constant TRFC : real := 75.0E-9; -- auto refresh command period [s]
constant TCAS : positive := 2; -- CAS latency [clocks]
constant TRP : real := 20.0; -- precharge command period [ns]
constant TRAS : real := 45.0; -- active to precharge delay [ns]
constant TRFC : real := 75.0; -- auto refresh command period [ns]
constant TMRD : positive := 2; -- load mode register command cylce time [clocks]
constant TRCD : real := 20.0E-9; -- active to read or write delay [s]
constant TWR : real := 15.0E-9; -- write recovery time [s]
constant TRCD : real := 20.0; -- active to read or write delay [ns]
constant TWR : real := 15.0; -- write recovery time [ns]
constant PWR_UP_WAIT : real := 22.0E-6; -- [s]
constant PWR_UP_WAIT : real := 22.0E3; -- [ns]
subtype user_tag_t is unsigned(3 downto 0);